# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-rtwo-base.dts"
# 1 "<built-in>" 1
# 1 "<built-in>" 3
# 10 "<built-in>" 3
# 1 "<command line>" 1
# 1 "<built-in>" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-rtwo-base.dts" 2
# 13 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-rtwo-base.dts"
/dts-v1/;

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-moto-common-base.dtsi" 1
# 15 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-moto-common-base.dtsi"
/dts-v1/;

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 1
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1








# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 2 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-kalama.h" 1
# 3 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,dispcc-kalama.h" 1
# 4 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-kalama.h" 1
# 5 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gpucc-kalama.h" 1
# 6 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,rpmh.h" 1
# 7 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,tcsrcc-kalama.h" 1
# 8 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,videocc-kalama.h" 1
# 9 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/regulator/qcom,rpmh-regulator-levels.h" 1
# 10 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,kalama.h" 1
# 11 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,ipcc.h" 1
# 12 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,rpmh-rsc.h" 1
# 13 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,icc.h" 1
# 14 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/spmi/spmi.h" 1
# 15 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/power/qcom-aoss-qmp.h" 1
# 16 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,aop-qmp.h" 1
# 17 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2

/ {
 model = "Qualcomm Technologies, Inc. Kalama";
 compatible = "qcom,kalama";
 qcom,msm-id = <519 0x10000>;
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;
 memory { device_type = "memory"; reg = <0 0 0 0>; };
 ddr-regions { };


 chosen: chosen {
   bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=0 log_buf_len=256K kernel.panic_on_rcu_stall=1 service_locator.enable=1 msm_rtb.filter=0x237 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops swiotlb=noforce loop.max_part=7 fw_devlink.strict=1 allow_mismatched_32bit_el0 cpufreq.default_governor=performance printk.console_no_auto_verbose=1 kasan=off sysctl.kernel.sched_pelt_multiplier=4 can.stats_timer=0 pcie_ports=compat irqaffinity=0-2 disable_dma32=on no-steal-acc cgroup.memory=nokmem,nosocket slub_debug=-";
   stdout-path = "/soc/qcom,qupv3_1_geni_se@ac0000/qcom,qup_uart@a9c000";
 };

 reserved_memory: reserved-memory { };

 mem_offline: mem-offline {
  compatible = "qcom,mem-offline";
  offline-sizes = <0x2 0xc0000000 0x1 0x00000000>;
  granule = <512>;
  mboxes = <&qmp_aop 0>;
 };

 aliases: aliases {
  serial0 = &qupv3_se7_2uart;
  hsuart0 = &qupv3_se14_4uart;
  hsuart1 = &qupv3_se4_4uart;
  mmc1 = &sdhc_2;
  ufshc1 = &ufshc_mem;
 };

 sram: sram@17D09400 {
  #address-cells = <2>;
  #size-cells = <2>;
  compatible = "mmio-sram";
  reg = <0x0 0x17D09400 0x0 0x400>;
  ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>;

  cpu_scp_lpri: scmi-shmem@0 {
   compatible = "arm,scmi-shmem";
   reg = <0x0 0x0 0x0 0x400>;
  };
 };

 firmware: firmware { };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  CPU0: cpu@0 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x0>;
   enable-method = "psci";
   cpu-idle-states = <&SILVER_OFF>;
   power-domains = <&CPU_PD0>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <820>;
   dynamic-power-coefficient = <100>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_0>;
   L2_0: l2-cache {
         compatible = "arm,arch-cache";
         cache-level = <2>;
         next-level-cache = <&L3_0>;

    L3_0: l3-cache {
     compatible = "arm,arch-cache";
     cache-level = <3>;
    };
   };
  };

  CPU1: cpu@100 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x100>;
   enable-method = "psci";
   cpu-idle-states = <&SILVER_OFF>;
   power-domains = <&CPU_PD1>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <820>;
   dynamic-power-coefficient = <100>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_1>;
   L2_1: l2-cache {
         compatible = "arm,arch-cache";
         cache-level = <2>;
         next-level-cache = <&L3_0>;
   };
  };

  CPU2: cpu@200 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x200>;
   enable-method = "psci";
   cpu-idle-states = <&SILVER_OFF>;
   power-domains = <&CPU_PD2>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   capacity-dmips-mhz = <820>;
   dynamic-power-coefficient = <100>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_1>;
  };

  CPU3: cpu@300 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x300>;
   enable-method = "psci";
   cpu-idle-states = <&GOLD_OFF>;
   power-domains = <&CPU_PD3>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1800>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_3>;
   L2_3: l2-cache {
         compatible = "arm,arch-cache";
         cache-level = <2>;
         next-level-cache = <&L3_0>;
   };
  };

  CPU4: cpu@400 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x400>;
   enable-method = "psci";
   cpu-idle-states = <&GOLD_OFF>;
   power-domains = <&CPU_PD4>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1800>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_4>;
   L2_4: l2-cache {
         compatible = "arm,arch-cache";
         cache-level = <2>;
         next-level-cache = <&L3_0>;

   };
  };

  CPU5: cpu@500 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x500>;
   enable-method = "psci";
   cpu-idle-states = <&GOLD_OFF>;
   power-domains = <&CPU_PD5>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1800>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_5>;
   L2_5: l2-cache {
         compatible = "arm,arch-cache";
         cache-level = <2>;
         next-level-cache = <&L3_0>;
   };
  };

  CPU6: cpu@600 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x600>;
   enable-method = "psci";
   cpu-idle-states = <&GOLD_OFF>;
   power-domains = <&CPU_PD6>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   capacity-dmips-mhz = <1800>;
   dynamic-power-coefficient = <270>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_6>;
   L2_6: l2-cache {
         compatible = "arm,arch-cache";
         cache-level = <2>;
         next-level-cache = <&L3_0>;
   };
  };

  CPU7: cpu@700 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x700>;
   enable-method = "psci";
   cpu-idle-states = <&GOLD_PLUS_OFF>;
   power-domains = <&CPU_PD7>;
   power-domain-names = "psci";
   cpu-release-addr = <0x0 0xE3940000>;
   qcom,freq-domain = <&cpufreq_hw 2>;
   capacity-dmips-mhz = <1894>;
   dynamic-power-coefficient = <588>;
   #cooling-cells = <2>;
   next-level-cache = <&L2_7>;
   L2_7: l2-cache {
         compatible = "arm,arch-cache";
         cache-level = <2>;
         next-level-cache = <&L3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&CPU0>;
    };

    core1 {
     cpu = <&CPU1>;
    };

    core2 {
     cpu = <&CPU2>;
    };
   };

   cluster1 {
    core0 {
     cpu = <&CPU3>;
    };

    core1 {
     cpu = <&CPU4>;
    };

    core2 {
     cpu = <&CPU5>;
    };

    core3 {
     cpu = <&CPU6>;
    };
   };

   cluster2 {
    core0 {
     cpu = <&CPU7>;
    };
   };
  };
 };

 idle-states {
  entry-method = "psci";

  SILVER_OFF: silver-c4 {
   compatible = "arm,idle-state";
   idle-state-name = "rail-pc";
   entry-latency-us = <550>;
   exit-latency-us = <750>;
   min-residency-us = <6700>;
   arm,psci-suspend-param = <0x40000004>;
   local-timer-stop;
  };

  GOLD_OFF: gold-c4 {
   compatible = "arm,idle-state";
   idle-state-name = "rail-pc";
   entry-latency-us = <600>;
   exit-latency-us = <1300>;
   min-residency-us = <8136>;
   arm,psci-suspend-param = <0x40000004>;
   local-timer-stop;
  };

  GOLD_PLUS_OFF: gold-plus-c4 {
   compatible = "arm,idle-state";
   idle-state-name = "rail-pc";
   entry-latency-us = <500>;
   exit-latency-us = <1350>;
   min-residency-us = <7480>;
   arm,psci-suspend-param = <0x40000004>;
   local-timer-stop;
  };

  CLUSTER_PWR_DN: cluster-d4 {
   compatible = "domain-idle-state";
   idle-state-name = "l3-off";
   entry-latency-us = <750>;
   exit-latency-us = <2350>;
   min-residency-us = <9144>;
   arm,psci-suspend-param = <0x41000044>;
  };

  APSS_OFF: cluster-e3 {
   compatible = "domain-idle-state";
   idle-state-name = "llcc-off";
   entry-latency-us = <2800>;
   exit-latency-us = <4400>;
   min-residency-us = <10150>;
   arm,psci-suspend-param = <0x4100c344>;
  };
 };


 soc: soc { };
};

&reserved_memory {
 #address-cells = <2>;
 #size-cells = <2>;
 ranges;

 gunyah_hyp_mem: gunyah_hyp_region@80000000 {
  no-map;
  reg = <0x0 0x80000000 0x0 0xa00000>;
 };

 cpusys_vm_mem: cpusys_vm_region@80a00000 {
  no-map;
  reg = <0x0 0x80a00000 0x0 0x400000>;
 };
# 359 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi"
 xbl_dt_log_merged_mem: xbl_dt_log_merged@81a00000 {
  no-map;
  reg = <0x0 0x81a00000 0x0 0x260000>;
 };

 aop_cmd_db_mem: aop_cmd_db_region@81c60000 {
  compatible = "qcom,cmd-db";
  no-map;
  reg = <0x0 0x81c60000 0x0 0x20000>;
 };


 aop_config_merged_mem: aop_config_merged_region@81c80000 {
  no-map;
  reg = <0x0 0x81c80000 0x0 0x74000>;
 };

 chipinfo_mem: chipinfo_region@81cf4000 {
  no-map;
  reg = <0x0 0x81cf4000 0x0 0x1000>;
 };



 smem_mem: smem_region@81d00000 {
  no-map;
  reg = <0x0 0x81d00000 0x0 0x200000>;
 };

 adsp_mhi_mem: adsp_mhi_region@81f00000 {
  no-map;
  reg = <0x0 0x81f00000 0x0 0x20000>;
 };

 global_sync_mem: global_sync_region@82600000 {
  no-map;
  reg = <0x0 0x82600000 0x0 0x100000>;
 };

 tz_stat_mem: tz_stat_region@82700000 {
  no-map;
  reg = <0x0 0x82700000 0x0 0x100000>;
 };

 mpss_mem: mpss_region@89800000 {
  no-map;
  reg = <0x0 0x8a800000 0x0 0x10800000>;
 };

 q6_mpss_dtb_mem: q6_mpss_dtb_region@9b000000 {
  no-map;
  reg = <0x0 0x9b000000 0x0 0x80000>;
 };

 ipa_fw_mem: ipa_fw_region@9b080000 {
  no-map;
  reg = <0x0 0x9b080000 0x0 0x10000>;
 };

 ipa_gsi_mem: ipa_gsi_region@9b090000 {
  no-map;
  reg = <0x0 0x9b090000 0x0 0xa000>;
 };

 gpu_micro_code_mem: gpu_micro_code_region@9b09a000 {
  no-map;
  reg = <0x0 0x9b09a000 0x0 0x2000>;
 };

 spss_region_mem: spss_region_region@9b100000 {
  no-map;
  reg = <0x0 0x9b100000 0x0 0x180000>;
 };


 spu_tz_shared_mem: spu_tz_shared_mem@9b280000 {
  no-map;
  reg = <0x0 0x9b280000 0x0 0x60000>;
 };


 spu_modem_shared_mem: spu_modem_shared_mem@9b2e0000 {
  no-map;
  reg = <0x0 0x9b2e0000 0x0 0x20000>;
 };

 camera_mem: camera_region@9b300000 {
  no-map;
  reg = <0x0 0x9b300000 0x0 0x800000>;
 };

 video_mem: video_region@9bb00000 {
  no-map;
  reg = <0x0 0x9bb00000 0x0 0x700000>;
 };

 cvp_mem: cvp_region@9c200000 {
  no-map;
  reg = <0x0 0x9c200000 0x0 0x700000>;
 };

 cdsp_mem: cdsp_region@9c900000 {
  no-map;
  reg = <0x0 0x9c900000 0x0 0x2000000>;
 };

 q6_cdsp_dtb_mem: q6_cdsp_dtb_region@9e900000 {
  no-map;
  reg = <0x0 0x9e900000 0x0 0x80000>;
 };

 q6_adsp_dtb_mem: q6_adsp_dtb_region@9e980000 {
  no-map;
  reg = <0x0 0x9e980000 0x0 0x80000>;
 };

 adspslpi_mem: adspslpi_region@9ea00000 {
  no-map;
  reg = <0x0 0x9ea00000 0x0 0x4080000>;
 };





 mpss_dsm_mem: mpss_dsm_region@d4d00000 {
  no-map;
  reg = <0x0 0xd4d00000 0x0 0x3300000>;
 };

 tz_reserved_mem: tz_reserved_region@d8000000 {
  no-map;
  reg = <0x0 0xd8000000 0x0 0x100000>;
 };

 xbl_sc_mem: xbl_sc_region@d8100000 {
  no-map;
  reg = <0x0 0xd8100000 0x0 0x40000>;
 };

 cpucp_fw_mem: cpucp_fw_region@d8140000 {
  no-map;
  reg = <0x0 0xd8140000 0x0 0x1c0000>;
 };

 qtee_mem: qtee_region@d8300000 {
  no-map;
  reg = <0x0 0xd8300000 0x0 0x500000>;
 };






 hwfence_shbuf: hwfence-shmem {
  no-map;
  reg = <0x0 0xe6440000 0x0 0x2dd000>;
 };

 trust_ui_vm_mem: trust_ui_vm_region@f3800000 {
  no-map;

 };

 trust_ui_vm_dump: trust_ui_vm_dump@0xf78ee000 {
  no-map;

 };

 trust_ui_vm_qrtr: trust_ui_vm_qrtr@0xf78ef000 {
  no-map;

 };

 trust_ui_vm_vblk0_ring: trust_ui_vm_vblk0_ring@0xf78f8000 {
  no-map;

  gunyah-label = <0x11>;
 };

 trust_ui_vm_vblk1_ring: trust_ui_vm_vblk1_ring@0xf78fc000 {
  no-map;

  gunyah-label = <0x10>;
 };

 trust_ui_vm_swiotlb: trust_ui_vm_swiotlb@0xf7900000 {
  no-map;

  gunyah-label = <0x12>;
 };

 oem_vm_vblk0_ring: oem_vm_vblk0_ring@f7afc000 {
  no-map;

  gunyah-label = <0x13>;
 };

 oem_vm_swiotlb: oem_vm_swiotlb@f7b00000 {
  no-map;

  gunyah-label = <0x14>;
 };

 oem_vm_mem: oem_vm_region@f7c00000 {
  compatible = "shared-dma-pool";
  reg = <0x0 0xf7c00000 0x0 0x4800000>;
  reusable;
  alignment = <0x0 0x400000>;
 };

 llcc_lpi_mem: llcc_lpi_region@ff800000 {
  no-map;
  reg = <0x0 0xff800000 0x0 0x600000>;
 };

 va_md_mem: va_md_mem_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  size = <0 0x1000000>;
 };

 sp_mem: sp_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x1000000>;
 };

 cdsp_eva_mem: cdsp_eva_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x400000>;
 };

 adsp_mem_heap: adsp_heap_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0xC00000>;
 };

 user_contig_mem: user_contig_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x1000000>;
 };

 qseecom_mem: qseecom_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x1800000>;
 };

 cdsp_secure_heap: secure_cdsp_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x4800000>;
 };

 non_secure_display_memory: non_secure_display_region {
  compatible = "shared-dma-pool";
  reusable;
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  size = <0x0 0xa400000>;
  alignment = <0x0 0x400000>;
 };

 demura_heap_memory: demura_heap_region {
  compatible = "shared-dma-pool";
  reusable;
  alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
  size = <0x0 0x2800000>;
  alignment = <0x0 0x400000>;
 };

 qseecom_ta_mem: qseecom_ta_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x2000000>;
 };

 qmc_dma_mem: qmc_dma_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x1400000>;
 };

 ramoops_mem: ramoops_region {
  compatible = "ramoops";
  alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
  size = <0x0 0x200000>;
  pmsg-size = <0x200000>;
  mem-type = <2>;
 };

 audio_cma_mem: audio_cma_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x1C00000>;
 };

 sdsp_mem: sdsp_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x800000>;
 };


 system_cma: linux,cma {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0x0 0x2000000>;
  linux,cma-default;
 };

 kinfo_mem: debug_kinfo_region {
  alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
  size = <0x0 0x1000>;
  no-map;
 };
};

&soc {
 #address-cells = <1>;
 #size-cells = <1>;
 ranges = <0 0 0 0xffffffff>;
 compatible = "simple-bus";

 disp_rdump_region@b8000000 {
 };

 dsi_pll_codes {
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  CPU_PD0: cpu-pd0 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CPU_PD1: cpu-pd1 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CPU_PD2: cpu-pd2 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CPU_PD3: cpu-pd3 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CPU_PD4: cpu-pd4 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CPU_PD5: cpu-pd5 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CPU_PD6: cpu-pd6 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CPU_PD7: cpu-pd7 {
   #power-domain-cells = <0>;
   power-domains = <&CLUSTER_PD>;
  };

  CLUSTER_PD: cluster-pd {
   #power-domain-cells = <0>;
   domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
  };
 };

 qcom,power-state {
  compatible = "qcom,power-state";
  qcom,subsys-name = "lpass", "cdsp", "mpss";
  qcom,rproc-handle = <&adsp_pas>, <&cdsp_pas>, <&modem_pas>;
 };

 slimbam: bamdma@6C04000 {
  compatible = "qcom,bam-v1.7.0";
  qcom,controlled-remotely;
  reg = <0x6C04000 0x20000>, <0x6C8B000 0x1000>;
  reg-names = "bam", "bam_remote_mem";
  num-channels = <31>;
  interrupts = <0 164 4>;
  #dma-cells = <1>;
  qcom,ee = <1>;
  qcom,num-ees = <2>;
 };

 slim_msm: slim@6C40000 {
  compatible = "qcom,slim-ngd-v1.5.0";
  reg = <0x6C40000 0x2C000>, <0x6C8A000 0x1000>;
  reg-names = "ctrl", "slimbus_remote_mem";
  interrupts = <0 163 4>;
  qcom,apps-ch-pipes = <0x0>;
  qcom,ea-pc = <0x430>;
  dmas = <&slimbam 3>, <&slimbam 4>;
  dma-names = "rx", "tx";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };


 intc: interrupt-controller@17100000 {
  compatible = "arm,gic-v3";
  #interrupt-cells = <3>;
  interrupt-controller;
  ranges;
  #redistributor-regions = <1>;
  redistributor-stride = <0x0 0x40000>;
  reg = <0x17100000 0x10000>,
        <0x17180000 0x200000>;
  interrupts = <1 9 4>;

  #address-cells = <1>;
  #size-cells = <1>;
  gic_its: msi-controller@17140000 {
   compatible = "arm,gic-v3-its";
   msi-controller;
   #msi-cells = <1>;
   reg = <0x17140000 0x20000>;
  };
 };

 apps_rsc: apps_rsc@17a00000 {
  label = "apps_rsc";
  compatible = "qcom,rpmh-rsc";
  reg = <0x17a00000 0x10000>,
        <0x17a10000 0x10000>,
        <0x17a20000 0x10000>;
  reg-names = "drv-0", "drv-1", "drv-2";
  qcom,drv-count = <3>;
  interrupts = <0 3 4>,
        <0 4 4>,
        <0 5 4>;
  power-domains = <&CLUSTER_PD>;

  apps_rsc_drv2: drv@2 {
   qcom,drv-id = <2>;
   qcom,tcs-offset = <0xd00>;
   channel@0 {
    qcom,tcs-config = <2 3>,
        <0 2>,
        <1 2>,
        <3 0>,
        <4 1>;
   };

   apps_bcm_voter: bcm_voter {
    compatible = "qcom,bcm-voter";
   };

   rpmhcc: clock-controller {
    compatible = "qcom,kalama-rpmh-clk";
    #clock-cells = <1>;
   };

   dcvs_fp: qcom,dcvs-fp {
    compatible = "qcom,dcvs-fp";
    qcom,ddr-bcm-name = "MC4";
    qcom,llcc-bcm-name = "SH5";
   };
  };
 };

 arch_timer: timer {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 ((((1 << (8)) - 1) << 8) | 8)>,
        <1 14 ((((1 << (8)) - 1) << 8) | 8)>,
        <1 11 ((((1 << (8)) - 1) << 8) | 8)>,
        <1 12 ((((1 << (8)) - 1) << 8) | 8)>;
  clock-frequency = <19200000>;
 };

 cam_rsc: cam_rsc@add9000 {
  label = "cam_rsc";
  compatible = "qcom,rpmh-rsc";
  reg = <0xadd9000 0x1000>,
        <0xadda000 0x1000>,
        <0xaddb000 0x1000>;
  reg-names = "drv-0", "drv-1", "drv-2";
  qcom,drv-count = <3>;
  qcom,hw-channel;
  interrupts = <0 368 4>,
        <0 369 4>,
        <0 370 4>;
  clocks = <&camcc 58>;

  cam_rsc_drv0: drv@0 {
   qcom,drv-id = <0>;
   qcom,tcs-offset = <0x520>;
   channel@0 {
    qcom,tcs-config = <2 0>,
        <1 1>,
        <0 1>,
        <3 0>,
        <4 0>;
   };

   channel@1 {
    qcom,tcs-config = <2 0>,
        <1 1>,
        <0 1>,
        <3 0>,
        <4 0>;
   };

   cam_bcm_voter0: bcm_voter {
    compatible = "qcom,bcm-voter";
   };
  };

  cam_rsc_drv1: drv@1 {
   qcom,drv-id = <1>;
   qcom,tcs-offset = <0x520>;
   channel@0 {
    qcom,tcs-config = <2 0>,
        <1 1>,
        <0 1>,
        <3 0>,
        <4 0>;
   };

   channel@1 {
    qcom,tcs-config = <2 0>,
        <1 1>,
        <0 1>,
        <3 0>,
        <4 0>;
   };

   cam_bcm_voter1: bcm_voter {
    compatible = "qcom,bcm-voter";
   };
  };

  cam_rsc_drv2: drv@2 {
   qcom,drv-id = <2>;
   qcom,tcs-offset = <0x520>;
   channel@0 {
    qcom,tcs-config = <2 0>,
        <1 1>,
        <0 1>,
        <3 0>,
        <4 0>;
   };

   channel@1 {
    qcom,tcs-config = <2 0>,
        <1 1>,
        <0 1>,
        <3 0>,
        <4 0>;
   };

   cam_bcm_voter2: bcm_voter {
    compatible = "qcom,bcm-voter";
   };
  };
 };

 disp_rsc: disp_rsc@af20000 {
  label = "disp_rsc";
  compatible = "qcom,rpmh-rsc";
  reg = <0xaf20000 0x10000>;
  reg-names = "drv-0";
  qcom,drv-count = <1>;
  interrupts = <0 129 4>;
  clocks = <&dispcc 70>;

  disp_rsc_drv0: drv@0 {
   qcom,drv-id = <0>;
   qcom,tcs-offset = <0x1c00>;
   channel@0 {
    qcom,tcs-config = <2 0>,
        <0 1>,
        <1 1>,
        <3 0>,
        <4 0>;
   };

   disp_bcm_voter: bcm_voter {
    compatible = "qcom,bcm-voter";
    qcom,tcs-wait = <(1 << 0)>;
   };
  };
 };

 memtimer: timer@17420000 {
  #address-cells = <1>;
  #size-cells = <1>;
  ranges;
  compatible = "arm,armv7-timer-mem";
  reg = <0x17420000 0x1000>;
  clock-frequency = <19200000>;

  frame@17421000 {
   frame-number = <0>;
   interrupts = <0 8 4>,
         <0 6 4>;
   reg = <0x17421000 0x1000>,
         <0x17422000 0x1000>;
  };

  frame@17423000 {
   frame-number = <1>;
   interrupts = <0 9 4>;
   reg = <0x17423000 0x1000>;
   status = "disabled";
  };

  frame@17425000 {
   frame-number = <2>;
   interrupts = <0 10 4>;
   reg = <0x17425000 0x1000>;
   status = "disabled";
  };

  frame@17427000 {
   frame-number = <3>;
   interrupts = <0 11 4>;
   reg = <0x17427000 0x1000>;
   status = "disabled";
  };

  frame@17429000 {
   frame-number = <4>;
   interrupts = <0 12 4>;
   reg = <0x17429000 0x1000>;
   status = "disabled";
  };

  frame@1742b000 {
   frame-number = <5>;
   interrupts = <0 13 4>;
   reg = <0x1742b000 0x1000>;
   status = "disabled";
  };

  frame@1742d000 {
   frame-number = <6>;
   interrupts = <0 14 4>;
   reg = <0x1742d000 0x1000>;
   status = "disabled";
  };
 };

 rimps: qcom,rimps@17400000 {
  #address-cells = <2>;
  #size-cells = <2>;
  compatible = "qcom,rimps";
  reg = <0x17400000 0x10>,
   <0x17d90000 0x2000>;
  #mbox-cells = <1>;
  interrupts = <0 62 4>;
 };

 scmi: qcom,scmi {
  #address-cells = <1>;
  #size-cells = <0>;
  compatible = "arm,scmi";
  mboxes = <&rimps 0>;
  mbox-names = "tx";
  shmem = <&cpu_scp_lpri>;

  scmi_memlat: protocol@80 {
   reg = <0x80>;
   #clock-cells = <1>;
  };

  scmi_plh: protocol@81 {
   reg = <0x81>;
   #clock-cells = <1>;
  };

  scmi_cpufreqstat: protocol@84 {
   reg = <0x84>;
   #clock-cells = <1>;
  };

  scmi_pmu: protocol@86 {
   reg = <0x86>;
   #clock-cells = <1>;
  };

  scmi_c1dcvs: protocol@87 {
   reg = <0x87>;
   #clock-cells = <1>;
  };

 };

 rimps_log: qcom,rimps_log@d8140000 {
  compatible = "qcom,rimps-log";
  reg = <0xd8140000 0x10000>, <0xd8150000 0x10000>;
  mboxes = <&rimps 1>;
 };

 cpu_pmu: cpu-pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <1 7 4>;
 };

 dmesg-dump {
  compatible = "qcom,dmesg-dump";
  qcom,primary-vm;
  gunyah-label = <7>;
  peer-name = <2>;
  shared-buffer = <&trust_ui_vm_dump>;
 };

 clk_virt: interconnect@0 {
  compatible = "qcom,kalama-clk_virt";
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mc_virt: interconnect@1 {
  compatible = "qcom,kalama-mc_virt";
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2";
  qcom,bcm-voters = <&apps_bcm_voter>,
      <&disp_bcm_voter>,
      <&cam_bcm_voter0>,
      <&cam_bcm_voter1>,
      <&cam_bcm_voter2>;
 };

 config_noc: interconnect@1600000 {
  compatible = "qcom,kalama-cnoc_cfg";
  reg = <0x1600000 0x6200>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 cnoc_main: interconnect@1500000 {
  compatible = "qcom,kalama-cnoc_main";
  reg = <0x1500000 0x13080>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 system_noc: interconnect@1680000 {
  compatible = "qcom,kalama-system_noc";
  reg = <0x1680000 0x1D080>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 pcie_noc: interconnect@16c0000 {
  compatible = "qcom,kalama-pcie_anoc";
  reg = <0x16c0000 0x12200>;
  #interconnect-cells = <1>;
  clocks = <&gcc 0>,
    <&gcc 10>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 aggre1_noc: interconnect@16e0000 {
  compatible = "qcom,kalama-aggre1_noc";
  reg = <0x16E0000 0x14400>;
  #interconnect-cells = <1>;
  clocks =
   <&gcc 1>,
   <&gcc 3>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 aggre2_noc: interconnect@1700000 {
  compatible = "qcom,kalama-aggre2_noc";
  reg = <0x1700000 0x1E400>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
  clocks = <&rpmhcc 12>;
 };

 mmss_noc: interconnect@1780000 {
  compatible = "qcom,kalama-mmss_noc";
  reg = <0x1780000 0x5B800>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2";
  qcom,bcm-voters = <&apps_bcm_voter>,
      <&disp_bcm_voter>,
      <&cam_bcm_voter0>,
      <&cam_bcm_voter1>,
      <&cam_bcm_voter2>;
 };

 gem_noc: interconnect@24100000 {
  compatible = "qcom,kalama-gem_noc";
  reg = <0x24100000 0xBB800>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos", "disp", "cam_ife_0", "cam_ife_1", "cam_ife_2";
  qcom,bcm-voters = <&apps_bcm_voter>,
      <&disp_bcm_voter>,
      <&cam_bcm_voter0>,
      <&cam_bcm_voter1>,
      <&cam_bcm_voter2>;
 };

 nsp_noc: interconnect@320c0000 {
  compatible = "qcom,kalama-nsp_noc";
  reg = <0x320C0000 0xE080>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 lpass_ag_noc: interconnect@7e40000 {
  compatible = "qcom,kalama-lpass_ag_noc";
  reg = <0x7e40000 0xE080>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 lpass_lpiaon_noc: interconnect@7400000 {
  compatible = "qcom,kalama-lpass_lpiaon_noc";
  reg = <0x7400000 0x19080>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 lpass_lpicx_noc: interconnect@7430000 {
  compatible = "qcom,kalama-lpass_lpicx_noc";
  reg = <0x7430000 0x3A200>;
  #interconnect-cells = <1>;
  qcom,bcm-voter-names = "hlos";
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 pdc: interrupt-controller@b220000 {
  compatible = "qcom,kalama-pdc", "qcom,pdc";
  reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
  qcom,pdc-ranges = <0 480 94>, <94 609 31>,
      <125 63 1>, <126 716 12>,
      <138 251 5>;
  #interrupt-cells = <2>;
  interrupt-parent = <&intc>;
  interrupt-controller;
 };

 vendor_hooks: qcom,cpu-vendor-hooks {
  compatible = "qcom,cpu-vendor-hooks";
 };

 logbuf: qcom,logbuf-vendor-hooks {
  compatible = "qcom,logbuf-vendor-hooks";
 };

 qcom,sps {
  compatible = "qcom,msm-sps-4k";
  qcom,pipe-attr-ee;
 };

 qcom_qseecom: qseecom@c1700000 {
  compatible = "qcom,qseecom";
  memory-region = <&qseecom_mem>;
  qseecom_mem = <&qseecom_mem>;
  qseecom_ta_mem = <&qseecom_ta_mem>;
  user_contig_mem = <&user_contig_mem>;
  qcom,hlos-num-ce-hw-instances = <1>;
  qcom,hlos-ce-hw-instance = <0>;
  qcom,qsee-ce-hw-instance = <0>;
  qcom,disk-encrypt-pipe-pair = <2>;
  qcom,no-clock-support;
  qcom,appsbl-qseecom-support;
  qcom,commonlib64-loaded-by-uefi;
  qcom,qsee-reentrancy-support = <2>;
 };

 qcom_tzlog: tz-log@146AA720 {
  compatible = "qcom,tz-log";
  reg = <0x146AA720 0x3000>;
  qcom,hyplog-enabled;
  hyplog-address-offset = <0x410>;
  hyplog-size-offset = <0x414>;
  tmecrashdump-address-offset = <0x81CA0000>;
 };

 qcom_cedev: qcedev@1de0000 {
  compatible = "qcom,qcedev";
  reg = <0x1de0000 0x20000>,
   <0x1dc4000 0x28000>;
  reg-names = "crypto-base","crypto-bam-base";
  interrupts = <0 272 4>;
  qcom,bam-pipe-pair = <2>;
  qcom,offload-ops-support;
  qcom,bam-pipe-offload-cpb-hlos = <1>;
  qcom,bam-pipe-offload-hlos-cpb = <3>;
  qcom,bam-pipe-offload-hlos-hlos = <4>;
  qcom,ce-hw-instance = <0>;
  qcom,ce-device = <0>;
  qcom,ce-hw-shared;
  qcom,bam-ee = <0>;
  qcom,smmu-s1-enable;
  qcom,no-clock-support;
  interconnect-names = "data_path";
  interconnects = <&aggre2_noc 39 &mc_virt 512>;
  iommus = <&apps_smmu 0x0480 0x0>,
   <&apps_smmu 0x0481 0x0>;
  qcom,iommu-dma = "atomic";
  dma-coherent;

  qcom_cedev_ns_cb {
   compatible = "qcom,qcedev,context-bank";
   label = "ns_context";
   iommus = <&apps_smmu 0x0481 0x0>;
   dma-coherent;
  };

  qcom_cedev_s_cb {
   compatible = "qcom,qcedev,context-bank";
   label = "secure_context";
   iommus = <&apps_smmu 0x0483 0x0>;
   qcom,iommu-vmid = <0x9>;
   qcom,secure-context-bank;
   dma-coherent;
  };
 };

 qcom_rng: qrng@10c3000 {
  compatible = "qcom,msm-rng";
  reg = <0x10c3000 0x1000>;
  qcom,no-qrng-config;
  qcom,no-clock-support;
 };

 qcom,msm-imem@146aa000 {
  compatible = "qcom,msm-imem";
  reg = <0x146aa000 0x1000>;
  ranges = <0x0 0x146aa000 0x1000>;
  #address-cells = <1>;
  #size-cells = <1>;

  mem_dump_table@10 {
   compatible = "qcom,msm-imem-mem_dump_table";
   reg = <0x10 0x8>;
  };

  restart_reason@65c {
   compatible = "qcom,msm-imem-restart_reason";
   reg = <0x65c 0x4>;
  };

  dload_type@1c {
   compatible = "qcom,msm-imem-dload-type";
   reg = <0x1c 0x4>;
  };

  boot_stats@6b0 {
   compatible = "qcom,msm-imem-boot_stats";
   reg = <0x6b0 0x20>;
  };

  kaslr_offset@6d0 {
   compatible = "qcom,msm-imem-kaslr_offset";
   reg = <0x6d0 0xc>;
  };

  pil@94c {
   compatible = "qcom,pil-reloc-info";
   reg = <0x94c 0xc8>;
  };

  pil@6dc {
   compatible = "qcom,msm-imem-pil-disable-timeout";
   reg = <0x6dc 0x4>;
  };

  diag_dload@c8 {
   compatible = "qcom,msm-imem-diag-dload";
   reg = <0xc8 0xc8>;
  };
 };


 spss_pas: remoteproc-spss@1880000 {
  compatible = "qcom,kalama-spss-pas";
  ranges;
  reg = <0x188101c 0x4>,
        <0x1881024 0x4>,
        <0x1881028 0x4>,
        <0x188103c 0x4>,
        <0x1881100 0x4>,
        <0x1882014 0x4>;
  reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
       "rmb_err", "rmb_general_purpose", "rmb_err_spare2";
  interrupts = <0 352 1>;

  cx-supply = <&VDD_CX_LEVEL>;
  cx-uV-uA = <384 100000>;

  clocks = <&rpmhcc 0>;
  clock-names = "xo";
  qcom,proxy-clock-names = "xo";
  status = "ok";

  memory-region = <&spss_region_mem>;

  qcom,signal-aop;
  qcom,qmp = <&aoss_qmp>;

  qcom,spss-scsr-bits = <24 25>;
  qcom,extra-size = <4096>;

  interconnects = <&aggre2_noc 39 &mc_virt 512>;
  interconnect-names = "crypto_ddr";

  glink-edge {
   qcom,remote-pid = <8>;
   mboxes = <&ipcc_mproc 16
      0>;
   mbox-names = "spss_spss";
   interrupt-parent = <&ipcc_mproc>;
   interrupts = <16
          0
          1>;

   reg = <0x1885008 0x8>,
         <0x1885010 0x4>;
   reg-names = "qcom,spss-addr",
        "qcom,spss-size";

   label = "spss";
   qcom,glink-label = "spss";
  };
 };

 qcom,spcom {
  compatible = "qcom,spcom";

  qcom,rproc-handle = <&spss_pas>;
  qcom,boot-enabled;

  qcom,spcom-ch-names = "sp_kernel", "sp_ssr";

  qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
  qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
  qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;

  qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
  qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
  status = "ok";
 };

 spss_utils: qcom,spss_utils {
  compatible = "qcom,spss-utils";

  qcom,rproc-handle = <&spss_pas>;
  qcom,spss-fuse1-addr = <0x221C8214>;
  qcom,spss-fuse1-bit = <8>;
  qcom,spss-fuse2-addr = <0x221C8214>;
  qcom,spss-fuse2-bit = <7>;
  qcom,spss-dev-firmware-name = "spss1d.mdt";
  qcom,spss-test-firmware-name = "spss1t.mdt";
  qcom,spss-prod-firmware-name = "spss1p.mdt";
  qcom,spss-debug-reg-addr = <0x01886020>;
  qcom,spss-debug-reg-addr1 = <0x01888020>;
  qcom,spss-debug-reg-addr3 = <0x0188C020>;
  qcom,spss-emul-type-reg-addr = <0x01fc8004>;
  pil-mem = <&spss_region_mem>;
  qcom,pil-size = <0x0F0000>;
  status = "ok";
 };

 qcom,msm-rtb {
  compatible = "qcom,msm-rtb";
  qcom,rtb-size = <0x100000>;
 };

 tlmm: pinctrl@f000000 {
  compatible = "qcom,kalama-pinctrl";
  reg = <0x0F000000 0x1000000>;
  interrupts = <0 208 4>;
  gpio-controller;
  #gpio-cells = <2>;
  interrupt-controller;
  #interrupt-cells = <2>;
  wakeup-parent = <&pdc>;
  qcom,gpios-reserved = <32 33 34 35 36 37 38 39>;
 };

 dload_mode {
  compatible = "qcom,dload-mode";
 };

 microdump_modem {
  compatible = "qcom,microdump_modem";
  };

 mini_dump_mode {
  compatible = "qcom,minidump";
  status = "ok";
 };

 va_mini_dump {
  compatible = "qcom,va-minidump";
  memory-region = <&va_md_mem>;
  status = "ok";
 };

 gic-interrupt-router {
  compatible = "qcom,gic-intr-routing";

  qcom,gic-class0-cpus = <0 1 2>;

  qcom,gic-class1-cpus = <3 4 5 6 7>;
 };

 qcom,secure-buffer {
  compatible = "qcom,secure-buffer";
  qcom,vmid-cp-camera-preview-ro;
 };

 qcom,mem-buf {
  compatible = "qcom,mem-buf";
  qcom,mem-buf-capabilities = "supplier";
  qcom,vmid = <3>;
 };

 qcom,mem-buf-msgq {
  compatible = "qcom,mem-buf-msgq";
 };

 qcom,memshare {
  compatible = "qcom,memshare";

  qcom,client_1 {
   compatible = "qcom,memshare-peripheral";
   qcom,peripheral-size = <0x0>;
   qcom,client-id = <0>;
   qcom,allocate-boot-time;
   label = "modem";
  };

  qcom,client_2 {
   compatible = "qcom,memshare-peripheral";
   qcom,peripheral-size = <0x0>;
   qcom,client-id = <2>;
   label = "modem";
  };

  mem_client_3: qcom,client_3 {
   compatible = "qcom,memshare-peripheral";
   qcom,peripheral-size = <0x500000>;
   qcom,client-id = <1>;
   qcom,allocate-on-request;
   label = "modem";
  };

  mem_client_4: qcom,client_4 {
   compatible = "qcom,memshare-peripheral";
   qcom,peripheral-size = <0x1000000>;
   qcom,client-id = <5>;
   qcom,allocate-on-request;
   qcom,shared;
   memory-region = <&qmc_dma_mem>;
   label = "modem";
  };

  mem_client_5: qcom,client_5 {
   compatible = "qcom,memshare-peripheral";
   qcom,peripheral-size = <0x400000>;
   qcom,client-id = <6>;
   qcom,allocate-on-request;
   qcom,shared;
   label = "modem";
  };
 };

 clocks {
  xo_board: xo_board {
   compatible = "fixed-clock";
   clock-frequency = <76800000>;
   clock-output-names = "xo_board";
   #clock-cells = <0>;
  };

  sleep_clk: sleep_clk {
   compatible = "fixed-clock";
   clock-frequency = <32000>;
   clock-output-names = "sleep_clk";
   #clock-cells = <0>;
  };
 };

 camcc: clock-controller@ade0000 {
  compatible = "qcom,kalama-camcc", "syscon";
  reg = <0xade0000 0x20000>;
  reg-name = "cc_base";
  vdd_mm-supply = <&VDD_MM_LEVEL>;
  vdd_mxa-supply = <&VDD_MXA_LEVEL>;
  vdd_mxc-supply = <&VDD_MXC_LEVEL>;
  clocks = <&rpmhcc 0>,
    <&rpmhcc 1>,
    <&sleep_clk>,
    <&gcc 6>;
  clock-names = "bi_tcxo",
         "bi_tcxo_ao",
         "sleep_clk",
         "iface";
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 cpuss-sleep-stats@17800054 {
       compatible = "qcom,cpuss-sleep-stats";
       reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
      <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
      <0x17860054 0x4>, <0x17870054 0x4>, <0x178a0098 0x4>,
      <0x178c0000 0x10000>;
       reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
     "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
     "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
     "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
     "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
       num-cpus = <8>;
 };

 dispcc: clock-controller@af00000 {
  compatible = "qcom,kalama-dispcc", "syscon";
  reg = <0xaf00000 0x20000>;
  reg-name = "cc_base";
  vdd_mm-supply = <&VDD_MM_LEVEL>;
  vdd_mxa-supply = <&VDD_MXA_LEVEL>;
  clocks = <&rpmhcc 0>,
    <&sleep_clk>,
    <&gcc 15>;
  clock-names = "bi_tcxo",
         "sleep_clk",
         "iface";
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 pcie_0_pipe_clk: pcie_0_pipe_clk {
  compatible = "fixed-clock";
  clock-frequency = <1000>;
  clock-output-names = "pcie_0_pipe_clk";
  #clock-cells = <0>;
 };

 pcie_1_phy_aux_clk: pcie_1_phy_aux_clk {
  compatible = "fixed-clock";
  clock-frequency = <1000>;
  clock-output-names = "pcie_1_phy_aux_clk";
  #clock-cells = <0>;
 };

 pcie_1_pipe_clk: pcie_1_pipe_clk {
  compatible = "fixed-clock";
  clock-frequency = <1000>;
  clock-output-names = "pcie_1_pipe_clk";
  #clock-cells = <0>;
 };

 ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
  compatible = "fixed-clock";
  clock-frequency = <1000>;
  clock-output-names = "ufs_phy_rx_symbol_0_clk";
  #clock-cells = <0>;
 };

 ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
  compatible = "fixed-clock";
  clock-frequency = <1000>;
  clock-output-names = "ufs_phy_rx_symbol_1_clk";
  #clock-cells = <0>;
 };

 ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
  compatible = "fixed-clock";
  clock-frequency = <1000>;
  clock-output-names = "ufs_phy_tx_symbol_0_clk";
  #clock-cells = <0>;
 };

 usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
  compatible = "fixed-clock";
  clock-frequency = <1000>;
  clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
  #clock-cells = <0>;
 };

 gcc: clock-controller@100000 {
  compatible = "qcom,kalama-gcc", "syscon";
  reg = <0x100000 0x1f4200>;
  reg-name = "cc_base";
  vdd_cx-supply = <&VDD_CX_LEVEL>;
  vdd_mxa-supply = <&VDD_MXA_LEVEL>;
  clocks = <&rpmhcc 0>,
    <&pcie_0_pipe_clk>,
    <&pcie_1_phy_aux_clk>,
    <&pcie_1_pipe_clk>,
    <&sleep_clk>,
    <&ufs_phy_rx_symbol_0_clk>,
    <&ufs_phy_rx_symbol_1_clk>,
    <&ufs_phy_tx_symbol_0_clk>,
    <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
  clock-names = "bi_tcxo",
         "pcie_0_pipe_clk",
         "pcie_1_phy_aux_clk",
         "pcie_1_pipe_clk",
         "sleep_clk",
         "ufs_phy_rx_symbol_0_clk",
         "ufs_phy_rx_symbol_1_clk",
         "ufs_phy_tx_symbol_0_clk",
         "usb3_phy_wrapper_gcc_usb30_pipe_clk";
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 gpucc: clock-controller@3d90000 {
  compatible = "qcom,kalama-gpucc", "syscon";
  reg = <0x3d90000 0xa000>;
  reg-name = "cc_base";
  vdd_cx-supply = <&VDD_CX_LEVEL>;
  vdd_mx-supply = <&VDD_MXA_LEVEL>;
  vdd_mxc-supply = <&VDD_MXC_LEVEL>;
  clocks = <&rpmhcc 0>,
    <&gcc 30>,
    <&gcc 31>;
  clock-names = "bi_tcxo",
         "gpll0_out_main",
         "gpll0_out_main_div";
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 tcsrcc: clock-controller@1fc0000 {
  compatible = "qcom,kalama-tcsrcc", "syscon";
  reg = <0x1fc0000 0x30000>;
  reg-name = "cc_base";
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 videocc: clock-controller@aaf0000 {
  compatible = "qcom,kalama-videocc", "syscon";
  reg = <0xaaf0000 0x10000>;
  reg-name = "cc_base";
  vdd_mm-supply = <&VDD_MM_LEVEL>;
  vdd_mxc-supply = <&VDD_MXC_LEVEL>;
  clocks = <&rpmhcc 0>,
    <&rpmhcc 1>,
    <&sleep_clk>,
    <&gcc 167>;
  clock-names = "bi_tcxo",
         "bi_tcxo_ao",
         "sleep_clk",
         "iface";
  #clock-cells = <1>;
  #reset-cells = <1>;
 };

 apsscc: syscon@17A80000 {
  compatible = "syscon";
  reg = <0x17A80000 0x21000>;
 };

 mccc: syscon@240ba000 {
  compatible = "syscon";
  reg = <0x240ba000 0x54>;
 };

 debugcc: clock-controller@0 {
  compatible = "qcom,kalama-debugcc";
  qcom,apsscc = <&apsscc>;
  qcom,camcc = <&camcc>;
  qcom,dispcc = <&dispcc>;
  qcom,gcc = <&gcc>;
  qcom,gpucc = <&gpucc>;
  qcom,tcsrcc = <&tcsrcc>;
  qcom,videocc = <&videocc>;
  qcom,mccc = <&mccc>;
  clocks = <&rpmhcc 0>,
    <&camcc 0>,
    <&dispcc 0>,
    <&gcc 0>,
    <&gpucc 0>,
    <&tcsrcc 0>,
    <&videocc 0>;
  clock-names = "xo_clk_src",
         "camcc",
         "dispcc",
         "gcc",
         "gpucc",
         "tcsrcc",
         "videocc";
  #clock-cells = <1>;
 };

 cpufreq_hw: qcom,cpufreq-hw {
  compatible = "qcom,cpufreq-epss";
  reg = <0x17D91000 0x1000>,
        <0x17D92000 0x1000>,
        <0x17D93000 0x1000>;
  reg-names = "freq-domain0",
       "freq-domain1",
       "freq-domain2";
  clocks = <&rpmhcc 0>, <&gcc 24>;
  clock-names = "xo", "alternate";
  interrupts = <0 30 4>,
        <0 31 4>,
        <0 19 4>;
  interrupt-names = "dcvsh0_int",
      "dcvsh1_int",
      "dcvsh2_int";
  #freq-domain-cells = <1>;
 };

 qcom,cpufreq-hw-debug {
  compatible = "qcom,cpufreq-hw-epss-debug";
  qcom,freq-hw-domain = <&cpufreq_hw 0>,
          <&cpufreq_hw 1>,
          <&cpufreq_hw 2>;
 };

 sdhc2_opp_table: sdhc2-opp-table {
  compatible = "operating-points-v2";

  opp-100000000 {
   opp-hz = /bits/ 64 <100000000>;
   opp-peak-kBps = <160000 100000>;
   opp-avg-kBps = <50000 0>;
  };

  opp-202000000 {
   opp-hz = /bits/ 64 <202000000>;
   opp-peak-kBps = <200000 120000>;
   opp-avg-kBps = <104000 0>;
  };
 };

 sdhc_2: sdhci@8804000 {
  status = "disabled";

  compatible = "qcom,sdhci-msm-v5";
  reg = <0x08804000 0x1000>;
  reg-names = "hc_mem";

  interrupts = <0 207 4>,
    <0 223 4>;
  interrupt-names = "hc_irq", "pwr_irq";

  bus-width = <4>;
  no-sdio;
  no-mmc;
  qcom,restore-after-cx-collapse;
  qcom,uses_level_shifter;
  qcom,dll_lock_bist_fail_wa;

  clocks = <&gcc 131>,
   <&gcc 132>;
  clock-names = "iface", "core";






  qcom,dll-hsr-list = <0x0007442C 0x0 0x10
     0x090106C0 0x80040868>;

  iommus = <&apps_smmu 0x540 0x0>;
  dma-coherent;

  interconnects = <&aggre2_noc 49 &mc_virt 512>,
         <&gem_noc 2 &config_noc
         543>;
  interconnect-names = "sdhc-ddr","cpu-sdhc";
  operating-points-v2 = <&sdhc2_opp_table>;

  qos0 {
   perf;
   vote = <44>;
  };

  qos1 {
   vote = <44>;
  };
 };

 ufsphy_mem: ufsphy_mem@1d80000 {
  reg = <0x1d80000 0x1934>;
  reg-names = "phy_mem";
  #phy-cells = <0>;

  lanes-per-direction = <2>;
  clock-names = "ref_clk_src",
   "ref_aux_clk", "qref_clk",
   "rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
   "rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
  clocks = <&rpmhcc 27>,
   <&gcc 144>,
   <&tcsrcc 2>,
   <&gcc 148>,
   <&gcc 150>,
   <&gcc 152>,
   <&gcc 147>,
   <&gcc 149>,
   <&gcc 151>;
  resets = <&ufshc_mem 0>;
  status = "disabled";
 };

 ice_cfg: shared_ice {
   alg1 {
        alg-name = "alg1";
        rx-alloc-percent = <60>;
        status = "disabled";
   };

   alg2 {
        alg-name = "alg2";
        status = "ok";
   };

   alg3 {
        alg-name = "alg3";
        num-core = <17 17 10 7>;
        status = "disabled";
   };
 };

 ufshc_mem: ufshc@1d84000 {
  compatible = "qcom,ufshc";
  reg = <0x1d84000 0x3000>,
        <0x1d88000 0x8000>,
        <0x1d90000 0x9000>;
  reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
  interrupts = <0 265 4>;
  phys = <&ufsphy_mem>;
  phy-names = "ufsphy";
  #reset-cells = <1>;

  qcom,dynamic-irq-affinity;
  lanes-per-direction = <2>;
  dev-ref-clk-freq = <0>;
  clock-names =
   "core_clk",
   "bus_aggr_clk",
   "iface_clk",
   "core_clk_unipro",
   "core_clk_ice",
   "ref_clk",
   "tx_lane0_sync_clk",
   "rx_lane0_sync_clk",
   "rx_lane1_sync_clk";
  clocks =
   <&gcc 138>,
   <&gcc 1>,
   <&gcc 137>,
   <&gcc 153>,
   <&gcc 141>,
   <&rpmhcc 4>,
   <&gcc 151>,
   <&gcc 147>,
   <&gcc 149>;
  freq-table-hz =
   <75000000 300000000>,
   <0 0>,
   <0 0>,
   <75000000 300000000>,
   <100000000 403000000>,
   <0 0>,
   <0 0>,
   <0 0>,
   <0 0>;

  interconnects = <&aggre1_noc 51 &mc_virt 512>,
        <&gem_noc 2 &config_noc 549>;
  interconnect-names = "ufs-ddr", "cpu-ufs";

  qcom,ufs-bus-bw,name = "ufshc_mem";
  qcom,ufs-bus-bw,num-cases = <30>;
  qcom,ufs-bus-bw,num-paths = <2>;
  qcom,ufs-bus-bw,vectors-KBps =
# 1993 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi"
  <0 0>, <0 0>,
  <922 0>, <1000 0>,
  <1844 0>, <1000 0>,
  <3688 0>, <1000 0>,
  <7376 0>, <1000 0>,
  <14752 0>, <1000 0>,
  <1844 0>, <1000 0>,
  <3688 0>, <1000 0>,
  <7376 0>, <1000 0>,
  <14752 0>, <1000 0>,
  <29504 0>, <1000 0>,
  <127796 0>, <1000 0>,
  <255591 0>, <1000 0>,
  <1492582 0>, <102400 0>,
  <2915200 0>, <204800 0>,
  <255591 0>, <1000 0>,
  <511181 0>, <1000 0>,
  <1492582 0>, <204800 0>,
  <2915200 0>, <409600 0>,
  <149422 0>, <1000 0>,
  <298189 0>, <1000 0>,
  <1492582 0>, <102400 0>,
  <2915200 0>, <204800 0>,
  <298189 0>, <1000 0>,
  <596378 0>, <1000 0>,






  <1492582 0>, <204800 409600>,
  <2915200 0>, <409600 409600>,
  <5836800 0>, <819200 0>,
  <5836800 0>, <819200 0>,
  <7643136 0>, <819200 0>;

  qcom,bus-vector-names = "MIN",
  "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G5_L1",
  "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "PWM_G5_L2",
  "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
  "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
  "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
  "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
  "HS_RA_G5_L2", "HS_RB_G5_L2",
  "MAX";

  iommus = <&apps_smmu 0x60 0x0>;
  qcom,iommu-dma = "fastmap";
  dma-coherent;


  qcom,bypass-pbl-rst-wa;

  shared-ice-cfg = <&ice_cfg>;
  qcom,vccq-lpm-uV = <1180000>;

  status = "disabled";
  qos0 {
   vote = <44>;
   perf;
  };

  qos1 {
   vote = <44>;
  };
 };

 tcsr_mutex_block: syscon@1f40000 {
  compatible = "syscon";
  reg = <0x1f40000 0x20000>;
 };

 tcsr_mutex: hwlock {
  compatible = "qcom,tcsr-mutex";
  syscon = <&tcsr_mutex_block 0 0x1000>;
  #hwlock-cells = <1>;
 };

 smem: qcom,smem {
  compatible = "qcom,smem";
  memory-region = <&smem_mem>;
  depends-on-supply = <&tcsr_mutex>;
  hwlocks = <&tcsr_mutex 3>;
 };

 qcom,rmtfs_sharedmem@0 {
  compatible = "qcom,sharedmem-uio";
  reg = <0x0 0x280000>;
  reg-names = "rmtfs";
  qcom,client-id = <0x00000001>;
 };

 aoss_qmp: power-controller@c300000 {
  compatible = "qcom,kalama-aoss-qmp";
  reg = <0xc300000 0x400>;
  interrupt-parent = <&ipcc_mproc>;
  interrupts = <0
         0
         1>;
  mboxes = <&ipcc_mproc 0
     0>;

  #power-domain-cells = <1>;
  #clock-cells = <0>;
 };

 qmp_aop: qcom,qmp-aop {
  compatible = "qcom,qmp-mbox";
  qcom,qmp = <&aoss_qmp>;
  label = "aop";
  #mbox-cells = <1>;
 };

 qmp_tme: qcom,qmp-tme {
  compatible = "qcom,qmp-mbox";
  qcom,remote-pid = <14>;
  mboxes = <&ipcc_mproc 23
     0>;
  mbox-names = "tme_qmp";
  interrupt-parent = <&ipcc_mproc>;
  interrupts = <23
         0
         1>;

  label = "tme";
  qcom,early-boot;
  priority = <0>;
  mbox-desc-offset = <0x0>;
  #mbox-cells = <1>;
 };

 qcom,tmecom-qmp-client {
  compatible = "qcom,tmecom-qmp-client";
  mboxes = <&qmp_tme 0>;
  mbox-names = "tmecom";
  label = "tmecom";
  depends-on-supply = <&qmp_tme>;
 };

 qcom,smp2p-adsp {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;
  interrupt-parent = <&ipcc_mproc>;
  interrupts = <3 2
         1>;
  mboxes = <&ipcc_mproc 3
     2>;
  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  adsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  adsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  sleepstate_smp2p_out: sleepstate-out {
   qcom,entry-name = "sleepstate";
   #qcom,smem-state-cells = <1>;
  };

  sleepstate_smp2p_in: qcom,sleepstate-in {
   qcom,entry-name = "sleepstate_see";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
   qcom,entry-name = "rdbg";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
   qcom,entry-name = "rdbg";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 qcom,smp2p-cdsp {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;
  interrupt-parent = <&ipcc_mproc>;
  interrupts = <6 2
         1>;
  mboxes = <&ipcc_mproc 6 2>;
  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  cdsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  cdsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
   qcom,entry-name = "rdbg";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
   qcom,entry-name = "rdbg";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 qcom,smp2p-modem {
  compatible = "qcom,smp2p";
  qcom,smem = <435>, <428>;
  interrupt-parent = <&ipcc_mproc>;
  interrupts = <2 2
         1>;
  mboxes = <&ipcc_mproc 2 2>;
  qcom,local-pid = <0>;
  qcom,remote-pid = <1>;

  modem_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  modem_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
   qcom,entry-name = "ipa";
   #qcom,smem-state-cells = <1>;
  };


  smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
   qcom,entry-name = "ipa";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 qcom,smp2p_sleepstate {
  compatible = "qcom,smp2p-sleepstate";
  qcom,smem-states = <&sleepstate_smp2p_out 0>;
  interrupt-parent = <&sleepstate_smp2p_in>;
  interrupts = <0 0>;
  interrupt-names = "smp2p-sleepstate-in";
 };

 qcom,glinkpkt {
  compatible = "qcom,glinkpkt";

  qcom,glinkpkt-at-mdm0 {
   qcom,glinkpkt-edge = "mpss";
   qcom,glinkpkt-ch-name = "DS";
   qcom,glinkpkt-dev-name = "at_mdm0";
  };

  qcom,glinkpkt-apr-apps2 {
   qcom,glinkpkt-edge = "adsp";
   qcom,glinkpkt-ch-name = "apr_apps2";
   qcom,glinkpkt-dev-name = "apr_apps2";
  };

  qcom,glinkpkt-data40-cntl {
   qcom,glinkpkt-edge = "mpss";
   qcom,glinkpkt-ch-name = "DATA40_CNTL";
   qcom,glinkpkt-dev-name = "smdcntl8";
  };

  qcom,glinkpkt-data1 {
   qcom,glinkpkt-edge = "mpss";
   qcom,glinkpkt-ch-name = "DATA1";
   qcom,glinkpkt-dev-name = "smd7";
  };

  qcom,glinkpkt-data4 {
   qcom,glinkpkt-edge = "mpss";
   qcom,glinkpkt-ch-name = "DATA4";
   qcom,glinkpkt-dev-name = "smd8";
  };

  qcom,glinkpkt-data11 {
   qcom,glinkpkt-edge = "mpss";
   qcom,glinkpkt-ch-name = "DATA11";
   qcom,glinkpkt-dev-name = "smd11";
  };
  qcom,glinkpkt-xpan_control {
   qcom,glinkpkt-edge = "adsp";
   qcom,glinkpkt-ch-name = "bt_cp_ctrl";
   qcom,glinkpkt-dev-name = "bt_cp_ctrl";
  };

  qcom,glinkpkt-qmc-dma {
   qcom,glinkpkt-edge = "mpss";
   qcom,glinkpkt-ch-name = "QMC_DMA_LINE";
   qcom,glinkpkt-dev-name = "qmc_dma";
   qcom,glinkpkt-enable-ch-close;
  };

  qcom,glinkpkt-qmc-cma {
   qcom,glinkpkt-edge = "mpss";
   qcom,glinkpkt-ch-name = "QMC_CMA_LINE";
   qcom,glinkpkt-dev-name = "qmc_cma";
   qcom,glinkpkt-enable-ch-close;
  };
 };

 qcom,glink {
  compatible = "qcom,glink";
 };

 qcom,qsee_ipc_irq_bridge {
  compatible = "qcom,qsee-ipc-irq-bridge";

  qcom,qsee-ipc-irq-spss {
   qcom,dev-name = "qsee_ipc_irq_spss";
   interrupt-parent = <&ipcc_mproc>;
   interrupts = <16
          1
          1>;
   label = "spss";
  };
 };

 qrtr-gunyah-tvm {
  compatible = "qcom,qrtr-gunyah";
  qcom,master;
  gunyah-label = <3>;
  peer-name = <2>;
  shared-buffer = <&trust_ui_vm_qrtr>;
 };

 qrtr-gunyah-oemvm {
  compatible = "qcom,qrtr-gunyah";
  qcom,master;
  gunyah-label = <8>;
  peer-name = <4>;
 };

 sys-pm-vx@c320000 {
  compatible = "qcom,sys-pm-violators", "qcom,sys-pm-kalama";
  reg = <0xc320000 0x0400>;
  mboxes = <&qmp_aop 0>;
  mbox-names = "aop";
 };

 soc-sleep-stats@c3f0000 {
  compatible = "qcom,rpmh-sleep-stats";
  reg = <0xc3f0000 0x400>;
  qcom,drv-max = <0x14>;
  ss-name = "modem", "adsp", "adsp_island",
     "cdsp", "apss";
  mboxes = <&qmp_aop 0>;
  mbox-names = "aop";
  ddr-freq-update;
 };

 cluster-device {
  compatible = "qcom,lpm-cluster-dev";
  power-domains = <&CLUSTER_PD>;
 };

 subsystem-sleep-stats@c3f0000 {
  compatible = "qcom,subsystem-sleep-stats";
  reg = <0xc3f0000 0x400>;
  ddr-freq-update;
 };

 tcsr: syscon@1fc0000 {
       compatible = "syscon";
       reg = <0x1fc0000 0x30000>;
 };

 qcom,mpm2-sleep-counter@c221000 {
  compatible = "qcom,mpm2-sleep-counter";
  reg = <0xc221000 0x1000>;
  clock-frequency = <32768>;
 };

 cache-controller@25000000 {
  compatible = "qcom,kalama-llcc", "qcom,llcc-v41";
  reg = <0x25000000 0x800000> , <0x25800000 0x200000>;
  reg-names = "llcc_base", "llcc_broadcast_base";
  interrupts = <0 266 4>;
  cap-based-alloc-and-pwr-collapse;

  llcc-perfmon {
   compatible = "qcom,llcc-perfmon";
   clocks = <&aoss_qmp 0>;
   clock-names = "qdss_clk";
  };
 };

 qcom,chd {
  compatible = "qcom,core-hang-detect";
  label = "core";
  qcom,chd-percpu-info = <&CPU0 0x17800058 0x17800060>,
     <&CPU1 0x17810058 0x17810060>,
     <&CPU2 0x17820058 0x17820060>,
     <&CPU3 0x17830058 0x17830060>,
     <&CPU4 0x17840058 0x17840060>,
     <&CPU5 0x17850058 0x17850060>,
     <&CPU6 0x17860058 0x17860060>,
     <&CPU7 0x17870058 0x17870060>;
 };

 eud: qcom,msm-eud@88e0000 {
  compatible = "qcom,msm-eud";
  interrupt-names = "eud_irq";
  interrupt-parent = <&pdc>;
  interrupts = <11 4>;
  reg = <0x088E0000 0x2000>,
   <0x088E2000 0x1000>;
  reg-names = "eud_base", "eud_mode_mgr2";
  qcom,secure-eud-en;
  status = "ok";
 };

 ipcc_mproc: qcom,ipcc@408000 {
  compatible = "qcom,ipcc";
  reg = <0x408000 0x1000>;
  interrupts = <0 229 4>;
  interrupt-controller;
  #interrupt-cells = <3>;
  #mbox-cells = <2>;
 };

 qcom,msm-cdsp-loader {
  compatible = "qcom,cdsp-loader";
  qcom,proc-img-to-load = "cdsp";
  qcom,rproc-handle = <&cdsp_pas>;
 };

 qcom,msm-adsprpc-mem {
  compatible = "qcom,msm-adsprpc-mem-region";
  memory-region = <&adsp_mem_heap>;
  restrict-access;
 };

 msm_fastrpc: qcom,msm_fastrpc {
  compatible = "qcom,msm-fastrpc-compute";
  qcom,adsp-remoteheap-vmid = <22 37>;
  qcom,fastrpc-adsp-audio-pdr;
  qcom,fastrpc-adsp-sensors-pdr;
  qcom,rpc-latency-us = <235>;
  qcom,fastrpc-gids = <2908>;
  qcom,qos-cores = <0 1 2>;

  qcom,msm_fastrpc_compute_cb1 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1961 0x0000>,
     <&apps_smmu 0x0C01 0x0020>,
     <&apps_smmu 0x19C1 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb2 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1962 0x0000>,
     <&apps_smmu 0x0C02 0x0020>,
     <&apps_smmu 0x19C2 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb3 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1963 0x0000>,
     <&apps_smmu 0x0C03 0x0020>,
     <&apps_smmu 0x19C3 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb4 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1964 0x0000>,
     <&apps_smmu 0x0C04 0x0020>,
     <&apps_smmu 0x19C4 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb5 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1965 0x0000>,
     <&apps_smmu 0x0C05 0x0020>,
     <&apps_smmu 0x19C5 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb6 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1966 0x0000>,
     <&apps_smmu 0x0C06 0x0020>,
     <&apps_smmu 0x19C6 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb7 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1967 0x0000>,
     <&apps_smmu 0x0C07 0x0020>,
     <&apps_smmu 0x19C7 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb8 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x1968 0x0000>,
     <&apps_smmu 0x0C08 0x0020>,
     <&apps_smmu 0x19C8 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb9 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   qcom,secure-context-bank;
   iommus = <&apps_smmu 0x1969 0x0000>,
     <&apps_smmu 0x0C09 0x0020>,
     <&apps_smmu 0x19C9 0x0010>;
   qcom,iommu-dma-addr-pool = <0x40000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   qcom,iommu-vmid = <0xA>;
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb10 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "adsprpc-smd";
   iommus = <&apps_smmu 0x1003 0x0080>,
     <&apps_smmu 0x1063 0x0000>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb11 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "adsprpc-smd";
   iommus = <&apps_smmu 0x1004 0x0080>,
     <&apps_smmu 0x1064 0x0000>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb12 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "adsprpc-smd";
   iommus = <&apps_smmu 0x1005 0x0080>,
     <&apps_smmu 0x1065 0x0000>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   shared-cb = <8>;
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb13 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "adsprpc-smd";
   iommus = <&apps_smmu 0x1006 0x0080>,
     <&apps_smmu 0x1066 0x0000>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb14 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "adsprpc-smd";
   iommus = <&apps_smmu 0x1007 0x0080>,
     <&apps_smmu 0x1067 0x0000>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb15 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x196C 0x0000>,
     <&apps_smmu 0x0C0C 0x0020>,
     <&apps_smmu 0x19CC 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb16 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x196D 0x0000>,
     <&apps_smmu 0x0C0D 0x0020>,
     <&apps_smmu 0x19CD 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb17 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x196E 0x0000>,
     <&apps_smmu 0x0C0E 0x0020>,
     <&apps_smmu 0x19CE 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };

  qcom,msm_fastrpc_compute_cb18 {
   compatible = "qcom,msm-fastrpc-compute-cb";
   label = "cdsprpc-smd";
   iommus = <&apps_smmu 0x196F 0x0000>,
     <&apps_smmu 0x0C0F 0x0020>,
     <&apps_smmu 0x19CF 0x0010>;
   qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
   qcom,iommu-faults = "stall-disable", "HUPCF";
   dma-coherent;
  };
 };

 adsp_pas: remoteproc-adsp@03000000 {
  compatible = "qcom,kalama-adsp-pas";
  reg = <0x03000000 0x10000>;
  status = "ok";

  cx-supply = <&VDD_LPI_CX_LEVEL>;
  cx-uV-uA = <384 0>;
  mx-supply = <&VDD_LPI_MX_LEVEL>;
  mx-uV-uA = <384 0>;
  reg-names = "cx", "mx";

  clocks = <&rpmhcc 0>;
  clock-names = "xo";

  qcom,signal-aop;
  qcom,qmp = <&aoss_qmp>;

  interconnects = <&lpass_lpicx_noc 41 &mc_virt 512>,
    <&aggre2_noc 39 &mc_virt 512>;
  interconnect-names = "rproc_ddr", "crypto_ddr";

  memory-region = <&adspslpi_mem &q6_adsp_dtb_mem>;


  interrupts-extended = <&pdc 6 1>,
     <&adsp_smp2p_in 0 0>,
     <&adsp_smp2p_in 2 0>,
     <&adsp_smp2p_in 1 0>,
     <&adsp_smp2p_in 3 0>,
     <&adsp_smp2p_in 7 0>;

  interrupt-names = "wdog",
    "fatal",
    "handover",
    "ready",
    "stop-ack",
    "shutdown-ack";


  qcom,smem-states = <&adsp_smp2p_out 0>;
  qcom,smem-state-names = "stop";

  glink_edge: glink-edge {
   qcom,remote-pid = <2>;
   transport = "smem";
   mboxes = <&ipcc_mproc 3
      0>;
   mbox-names = "adsp_smem";
   interrupt-parent = <&ipcc_mproc>;
   interrupts = <3
          0
          1>;

   label = "adsp";
   qcom,glink-label = "lpass";

   qcom,adsp_qrtr {
    qcom,glink-channels = "IPCRTR";
    qcom,intents = <0x800 5
      0x2000 3
      0x4400 2>;
    qcom,no-wake-svc = <0x190>;
   };

   qcom,msm_fastrpc_rpmsg {
    compatible = "qcom,msm-fastrpc-rpmsg";
    qcom,glink-channels = "fastrpcglink-apps-dsp";
    qcom,intents = <0x64 64>;
   };

   qcom,msm_adspsleepmon_rpmsg {
    compatible = "qcom,msm-adspsleepmon-rpmsg";
    qcom,glink-channels = "sleepmonglink-apps-adsp";
    qcom,intents = <0x1000 8>;
   };

   qcom,pmic_glink_rpmsg {
    qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
   };

   qcom,pmic_glink_log_rpmsg {
    qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
    qcom,intents = <0x800 5
      0xc00 3
      0x2000 1>;
   };

  };
 };

 cdsp_pas: remoteproc-cdsp@32300000 {
  compatible = "qcom,kalama-cdsp-pas";
  reg = <0x32300000 0x10000>;
  status = "ok";

  cx-supply = <&VDD_CX_LEVEL>;
  cx-uV-uA = <384 100000>;
  mx-supply = <&VDD_MXC_LEVEL>;
  mx-uV-uA = <384 100000>;
  nsp-supply = <&VDD_NSP_LEVEL>;
  nsp-uV-uA = <384 100000>;
  reg-names = "cx","mx","nsp";

  memory-region = <&cdsp_mem &q6_cdsp_dtb_mem>;

  clocks = <&rpmhcc 0>;
  clock-names = "xo";

  qcom,signal-aop;
  qcom,qmp = <&aoss_qmp>;

  interconnects = <&nsp_noc 42 &mc_virt 512>,
    <&aggre2_noc 39 &mc_virt 512>;
  interconnect-names = "rproc_ddr", "crypto_ddr";


  interrupts-extended = <&intc 0 578 1>,
     <&cdsp_smp2p_in 0 0>,
     <&cdsp_smp2p_in 2 0>,
     <&cdsp_smp2p_in 1 0>,
     <&cdsp_smp2p_in 3 0>,
     <&cdsp_smp2p_in 7 0>;

  interrupt-names = "wdog",
    "fatal",
    "handover",
    "ready",
    "stop-ack",
    "shutdown-ack";


  qcom,smem-states = <&cdsp_smp2p_out 0>;
  qcom,smem-state-names = "stop";

  glink-edge {
   qcom,remote-pid = <5>;
   transport = "smem";
   mboxes = <&ipcc_mproc 6
      0>;
   mbox-names = "cdsp_smem";
   interrupt-parent = <&ipcc_mproc>;
   interrupts = <6
          0
          1>;

   label = "cdsp";
   qcom,glink-label = "cdsp";

   qcom,cdsp_qrtr {
    qcom,glink-channels = "IPCRTR";
    qcom,intents = <0x800 5
      0x2000 3
      0x4400 2>;
   };

   qcom,msm_fastrpc_rpmsg {
    compatible = "qcom,msm-fastrpc-rpmsg";
    qcom,glink-channels = "fastrpcglink-apps-dsp";
    qcom,intents = <0x64 64>;
   };

   qcom,msm_cdsprm_rpmsg {
    compatible = "qcom,msm-cdsprm-rpmsg";
    qcom,glink-channels = "cdsprmglink-apps-dsp";
    qcom,intents = <0x20 12>;

    msm_cdsp_rm: qcom,msm_cdsp_rm {
     compatible = "qcom,msm-cdsp-rm";
     qcom,qos-latency-us = <70>;
     qcom,qos-maxhold-ms = <20>;
    };
   };
  };
 };

 modem_pas: remoteproc-mss@04080000 {
  compatible = "qcom,kalama-modem-pas";
  reg = <0x4080000 0x10000>;
  status = "ok";

  clocks = <&rpmhcc 0>;
  clock-names = "xo";

  cx-supply = <&VDD_CX_LEVEL>;
  cx-uV-uA = <384 100000>;
  mx-supply = <&VDD_MODEM_LEVEL>;
  mx-uV-uA = <320 100000>;
  reg-names = "cx", "mx";

  qcom,signal-aop;
  qcom,qmp = <&aoss_qmp>;

  interconnects = <&mc_virt 3 &mc_virt 512>,
    <&aggre2_noc 39 &mc_virt 512>;
  interconnect-names = "rproc_ddr", "crypto_ddr";

  memory-region = <&mpss_mem &q6_mpss_dtb_mem &system_cma>;
  mpss_dsm_mem_reg = <&mpss_dsm_mem>;


  interrupts-extended = <&intc 0 264 1>,
     <&modem_smp2p_in 0 0>,
     <&modem_smp2p_in 2 0>,
     <&modem_smp2p_in 1 0>,
     <&modem_smp2p_in 3 0>,
     <&modem_smp2p_in 7 0>;

  interrupt-names = "wdog",
    "fatal",
    "handover",
    "ready",
    "stop-ack",
    "shutdown-ack";


  qcom,smem-states = <&modem_smp2p_out 0>;
  qcom,smem-state-names = "stop";

  glink-edge {
   qcom,remote-pid = <1>;
   transport = "smem";
   mboxes = <&ipcc_mproc 2
      0>;
   mbox-names = "mpss_smem";
   interrupt-parent = <&ipcc_mproc>;
   interrupts = <2
          0
          1>;

   label = "modem";
   qcom,glink-label = "mpss";

   qcom,modem_qrtr {
    qcom,glink-channels = "IPCRTR";
    qcom,low-latency;
    qcom,intents = <0x800 5
      0x2000 3
      0x4400 2>;
   };

   qcom,modem_ds {
    qcom,glink-channels = "DS";
    qcom,intents = <0x4000 0x2>;
   };
  };
 };

 qcom,guestvm_loader@f3c00000 {
  compatible = "qcom,guestvm-loader";
  qcom,pas-id = <28>;
  qcom,isolate-cpus;
  qcom,vmid = <45>;
  qcom,firmware-name = "trustedvm";
  qcom,reserved-cpus = <0x5>, <0x6>;
  qcom,unisolate-timeout-ms = <12000>;
  memory-region = <&trust_ui_vm_mem>;
 };

 qcom,guestvm_loader@80a00000 {
  compatible = "qcom,guestvm-loader";
  qcom,pas-id = <35>;
  qcom,vmid = <50>;
  qcom,firmware-name = "cpusys_vm";
  memory-region = <&cpusys_vm_mem>;
 };

 qcom,guestvm_loader@f8400000 {
  compatible = "qcom,guestvm-loader";
  qcom,pas-id = <34>;
  qcom,vmid = <49>;
  qcom,firmware-name = "oemvm";
  memory-region = <&oem_vm_mem>;
 };

 tlmm-vm-mem-access {
  compatible = "qcom,tlmm-vm-mem-access";
  qcom,master;
  tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0
     &tlmm 47 0 &tlmm 24 0 &tlmm 25 0 &tlmm 91 0 &tlmm 56 0
     &tlmm 57 0 &tlmm 58 0 &tlmm 59 0 &tlmm 13 0 &tlmm 48 0>;
 };

 tlmm-vm-test {
  compatible = "qcom,tlmm-vm-test";
  qcom,master;
  tlmm-vm-gpio-list = <&tlmm 86 0 &tlmm 87 0 &tlmm 133 0 &tlmm 137 0 &tlmm 44 0 &tlmm 45 0 &tlmm 46 0
    &tlmm 47 0 &tlmm 24 0 &tlmm 25 0 &tlmm 91 0 &tlmm 56 0
    &tlmm 57 0 &tlmm 58 0 &tlmm 59 0 &tlmm 13 0 &tlmm 48 0>;
 };

 trust_ui_vm: qcom,trust_ui_vm@0xf78f8000 {
  reg = <0xf78f8000 0x108000>;
  vm_name = "trustedvm";
  shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_vblk1_ring &trust_ui_vm_swiotlb>;
 };

 oem_vm: qcom,oem_vm@f7afc000 {
  reg = <0xf7afc000 0x104000>;
  vm_name = "oemvm";
  shared-buffers = <&oem_vm_vblk0_ring &oem_vm_swiotlb>;
 };

 trust_ui_vm_virt_be0: trust_ui_vm_virt_be0@11 {
  qcom,vm = <&trust_ui_vm>;
  qcom,label = <0x11>;
 };

 trust_ui_vm_virt_be1: trust_ui_vm_virt_be1@10 {
  qcom,vm = <&trust_ui_vm>;
  qcom,label = <0x10>;
 };

 gh-secure-vm-loader@0 {
  compatible = "qcom,gh-secure-vm-loader";
  qcom,pas-id = <28>;
  qcom,vmid = <45>;
  qcom,firmware-name = "trustedvm";
  memory-region = <&trust_ui_vm_mem>;
  virtio-backends = <&trust_ui_vm_virt_be0 &trust_ui_vm_virt_be1>;
 };

 oem_vm_virt_be0: oem_vm_virt_be0@13 {
  qcom,vm = <&oem_vm>;
  qcom,label = <0x13>;
 };

 gh-secure-vm-loader@1 {
  compatible = "qcom,gh-secure-vm-loader";
  qcom,pas-id = <34>;
  qcom,vmid = <49>;
  qcom,firmware-name = "oemvm";
  memory-region = <&oem_vm_mem>;
  virtio-backends = <&oem_vm_virt_be0>;
 };

 gh-secure-vm-loader@2 {
  compatible = "qcom,gh-secure-vm-loader";
  qcom,pas-id = <35>;
  qcom,vmid = <50>;
  qcom,firmware-name = "cpusys_vm";
  memory-region = <&cpusys_vm_mem>;
  ext-region = <&chipinfo_mem>;
  ext-label = <0x7>;
 };

 llcc_pmu: llcc-pmu@24095000 {
  compatible = "qcom,llcc-pmu-ver2";
  reg = <0x24095000 0x300>;
  reg-names = "lagg-base";
 };

 qcom_pmu: qcom,pmu {
  compatible = "qcom,pmu";
  qcom,long-counter;
  reg = <0x17d09880 0x380>;
  reg-names = "pmu-base";
  qcom,pmu-events-tbl =
   < 0x0008 0xFF 0x02 0x02 >,
   < 0x0011 0xFF 0x01 0x00 >,
   < 0x0017 0xFF 0xFF 0x04 >,
   < 0x0037 0xFF 0xFF 0x06 >,
   < 0x1000 0xFF 0xFF 0x08 >;
 };

 ddr_freq_table: ddr-freq-table {
  qcom,freq-tbl =
   < 547000 >,
   < 768000 >,
   < 1555000 >,
   < 1708000 >,
   < 2092000 >,
   < 2736000 >,
   < 3187000 >,
   < 3686000 >,
   < 4224000 >;
 };

 llcc_freq_table: llcc-freq-table {
  qcom,freq-tbl =
   < 300000 >,
   < 466000 >,
   < 600000 >,
   < 806000 >,
   < 933000 >,
   < 1066000 >;
 };

 ddrqos_freq_table: ddrqos-freq-table {
  qcom,freq-tbl =
   < 0 >,
   < 1 >;
 };

 qcom_dcvs: qcom,dcvs {
  compatible = "qcom,dcvs";
  #address-cells = <1>;
  #size-cells = <1>;
  ranges;

  qcom_l3_dcvs_hw: l3 {
   compatible = "qcom,dcvs-hw";
   qcom,dcvs-hw-type = <2>;
   qcom,bus-width = <32>;
   reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
   reg-names = "l3-base", "l3tbl-base";

   l3_dcvs_sp: sp {
    compatible = "qcom,dcvs-path";
    qcom,dcvs-path-type = <0>;
    qcom,shared-offset = <0x0090>;
   };
  };

  qcom_ddr_dcvs_hw: ddr {
   compatible = "qcom,dcvs-hw";
   qcom,dcvs-hw-type = <0>;
   qcom,bus-width = <4>;
   qcom,freq-tbl = <&ddr_freq_table>;

   ddr_dcvs_sp: sp {
    compatible = "qcom,dcvs-path";
    qcom,dcvs-path-type = <0>;
    interconnects = <&mc_virt 3
       &mc_virt 512>;
   };

   ddr_dcvs_fp: fp {
    compatible = "qcom,dcvs-path";
    qcom,dcvs-path-type = <1>;
    qcom,fp-voter = <&dcvs_fp>;
   };
  };

  qcom_llcc_dcvs_hw: llcc {
   compatible = "qcom,dcvs-hw";
   qcom,dcvs-hw-type = <1>;
   qcom,bus-width = <16>;
   qcom,freq-tbl = <&llcc_freq_table>;

   llcc_dcvs_sp: sp {
    compatible = "qcom,dcvs-path";
    qcom,dcvs-path-type = <0>;
    interconnects = <&gem_noc 2
       &gem_noc 558>;
   };

   llcc_dcvs_fp: fp {
    compatible = "qcom,dcvs-path";
    qcom,dcvs-path-type = <1>;
    qcom,fp-voter = <&dcvs_fp>;
   };
  };

  qcom_ddrqos_dcvs_hw: ddrqos {
   compatible = "qcom,dcvs-hw";
   qcom,dcvs-hw-type = <3>;
   qcom,bus-width = <1>;
   qcom,freq-tbl = <&ddrqos_freq_table>;

   ddrqos_dcvs_sp: sp {
    compatible = "qcom,dcvs-path";
    qcom,dcvs-path-type = <0>;
    interconnects = <&mc_virt 3
       &mc_virt 512>;
   };
  };
 };

 qcom_memlat: qcom,memlat {
  compatible = "qcom,memlat";

  ddr {
   compatible = "qcom,memlat-grp";
   qcom,target-dev = <&qcom_ddr_dcvs_hw>;
   qcom,sampling-path = <&ddr_dcvs_fp>;
   qcom,miss-ev = <0x1000>;

   silver {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
    qcom,cpufreq-memfreq-tbl =
     < 1113600 547000 >,
     < 1516800 768000 >,
     < 1824000 1555000 >;
    qcom,sampling-enabled;
   };

   gold {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>;
    qcom,cpufreq-memfreq-tbl =
     < 883200 547000 >,
     < 1113600 768000 >,
     < 1344000 1555000 >,
     < 1881600 2092000 >,
     < 2476800 3187000 >,
     < 2707200 4224000 >;
    qcom,sampling-enabled;
   };

   prime {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 883200 547000 >,
     < 1113600 768000 >,
     < 1344000 1555000 >,
     < 1881600 2092000 >,
     < 2476800 3187000 >,
     < 2707200 4224000 >;
    qcom,sampling-enabled;
   };

   gold-compute {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 1881600 547000 >,
     < 2707200 1555000 >;
    qcom,sampling-enabled;
    qcom,compute-mon;
   };

   prime-latfloor {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 2476800 547000 >,
     < 2707200 4224000 >;
    qcom,sampling-enabled;
   };
  };

  llcc {
   compatible = "qcom,memlat-grp";
   qcom,target-dev = <&qcom_llcc_dcvs_hw>;
   qcom,sampling-path = <&llcc_dcvs_fp>;
   qcom,miss-ev = <0x37>;

   silver {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
    qcom,cpufreq-memfreq-tbl =
     < 614400 300000 >,
     < 1516800 466000 >,
     < 1824000 600000 >;
    qcom,sampling-enabled;
   };

   gold {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 652800 300000 >,
     < 1113600 466000 >,
     < 1344000 600000 >,
     < 1881600 806000 >,
     < 2476800 933000 >,
     < 2707200 1066000 >;
    qcom,sampling-enabled;
   };

   gold-compute {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 1881600 300000 >,
     < 2707200 600000 >;
    qcom,sampling-enabled;
    qcom,compute-mon;
   };
  };

  l3 {
   compatible = "qcom,memlat-grp";
   qcom,target-dev = <&qcom_l3_dcvs_hw>;
   qcom,sampling-path = <&l3_dcvs_sp>;
   qcom,miss-ev = <0x17>;

   silver {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU0 &CPU1 &CPU2>;
    qcom,cpufreq-memfreq-tbl =
     < 307200 307200 >,
     < 403200 403200 >,
     < 614400 614400 >,
     < 729400 710400 >,
     < 825600 806400 >,
     < 921600 902400 >,
     < 1113600 998400 >,
     < 1228800 1113600 >,
     < 1324800 1228800 >,
     < 1516800 1420800 >,
     < 1632000 1536000 >,
     < 1824000 1651200 >;
    qcom,sampling-enabled;
   };

   gold {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6>;
    qcom,cpufreq-memfreq-tbl =
     < 307200 307200 >,
     < 537600 614400 >,
     < 883200 710400 >,
     < 1136000 902400 >,
     < 1344000 998400 >,
     < 1555200 1228800 >,
     < 1996800 1420800 >,
     < 2342400 1536000 >,
     < 2707200 1651200 >;
    qcom,sampling-enabled;
   };

   prime {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 307200 307200 >,
     < 537600 614400 >,
     < 883200 710400 >,
     < 1136000 902400 >,
     < 1344000 998400 >,
     < 1555200 1228800 >,
     < 1996800 1420800 >,
     < 2342400 1536000 >,
     < 2707200 1651200 >;
    qcom,sampling-enabled;
   };

   prime-compute {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 1996800 307200 >,
     < 2707200 1651200 >;
    qcom,sampling-enabled;
    qcom,compute-mon;
   };
  };

  ddrqos {
   compatible = "qcom,memlat-grp";
   qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
   qcom,sampling-path = <&ddrqos_dcvs_sp>;
   qcom,miss-ev = <0x1000>;

   ddrqos_gold_lat: gold {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 1881600 0 >,
     < 2707200 1 >;
    qcom,sampling-enabled;
   };

   ddrqos_prime_lat: prime {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 1401600 0 >,
     < 2707200 1 >;
    qcom,sampling-enabled;
   };

   ddrqos_prime_latfloor: prime-latfloor {
    compatible = "qcom,memlat-mon";
    qcom,cpulist = <&CPU7>;
    qcom,cpufreq-memfreq-tbl =
     < 1996800 0 >,
     < 2707200 1 >;
    qcom,sampling-enabled;
   };
  };
 };

 qcom_llcc_l3_vote: qcom,llcc-l3-vote {
  qcom,target-dev = <&qcom_l3_dcvs_hw>;
  qcom,secondary-map =
   < 300000 300000 >,
   < 466000 499200 >,
   < 600000 614400 >,
   < 806000 729600 >,
   < 933000 844800 >,
   < 1066000 940800 >;
 };

 bwmon_llcc: qcom,bwmon-llcc@240B6300 {
  compatible = "qcom,bwmon4";
  reg = <0x240B6400 0x300>, <0x240B6300 0x200>;
  reg-names = "base", "global_base";
  interrupts = <0 581 4>;
  qcom,mport = <0>;
  qcom,hw-timer-hz = <19200000>;
  qcom,count-unit = <0x10000>;
  qcom,target-dev = <&qcom_llcc_dcvs_hw>;
  qcom,second-vote = <&qcom_llcc_l3_vote>;
 };

 bwmon_ddr: qcom,bwmon-ddr@24091000 {
  compatible = "qcom,bwmon5";
  reg = <0x24091000 0x1000>;
  reg-names = "base";
  interrupts = <0 81 4>;
  qcom,hw-timer-hz = <19200000>;
  qcom,count-unit = <0x10000>;
  qcom,target-dev = <&qcom_ddr_dcvs_hw>;
 };

 thermal_zones: thermal-zones {
 };

 qcom_qbt: qcom,qbt_handler {
  compatible = "qcom,qbt-handler";
  qcom,ipc-gpio = <&tlmm 40 0>;
  qcom,finger-detect-gpio = <&tlmm 41 0>;
  qcom,intr2-gpio = <&tlmm 42 0>;
 };

 spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
  compatible = "qcom,spmi-pmic-arb";
  reg = <0xc42d000 0x4000>,
        <0xc400000 0x3000>,
        <0xc500000 0x400000>,
        <0xc440000 0x80000>,
        <0xc4c0000 0x10000>;
  reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
  interrupts-extended = <&pdc 1 4>;
  interrupt-names = "periph_irq";
  interrupt-controller;
  #interrupt-cells = <4>;
  #address-cells = <2>;
  #size-cells = <0>;
  cell-index = <0>;
  qcom,channel = <0>;
  qcom,ee = <0>;
  qcom,bus-id = <0>;
 };

 spmi1_bus: qcom,spmi@c432000 {
  compatible = "qcom,spmi-pmic-arb";
  reg = <0xc432000 0x4000>,
        <0xc400000 0x3000>,
        <0xc500000 0x400000>,
        <0xc440000 0x80000>,
        <0xc4d0000 0x10000>;
  reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
  interrupts-extended = <&pdc 3 4>;
  interrupt-names = "periph_irq";
  interrupt-controller;
  #interrupt-cells = <4>;
  #address-cells = <2>;
  #size-cells = <0>;
  cell-index = <0>;
  qcom,channel = <0>;
  qcom,ee = <0>;
  qcom,bus-id = <1>;
  depends-on-supply = <&spmi0_bus>;
 };

 spmi0_debug_bus: qcom,spmi-debug@10b14000 {
  compatible = "qcom,spmi-pmic-arb-debug";
  reg = <0x10b14000 0x60>, <0x221c8784 0x4>;
  reg-names = "core", "fuse";
  clocks = <&aoss_qmp>;
  clock-names = "core_clk";
  qcom,fuse-enable-bit = <18>;
  #address-cells = <2>;
  #size-cells = <0>;
  depends-on-supply = <&spmi1_bus>;
  depends-on2-supply = <&smb1394_glink_debug>;

  qcom,pmk8550-debug@0 {
   compatible = "qcom,spmi-pmic";
   reg = <0x0 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8550-debug@1 {
   compatible = "qcom,spmi-pmic";
   reg = <0x1 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8550vs-debug@2 {
   compatible = "qcom,spmi-pmic";
   reg = <0x2 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8550vs-debug@3 {
   compatible = "qcom,spmi-pmic";
   reg = <0x3 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8550vs-debug@4 {
   compatible = "qcom,spmi-pmic";
   reg = <0x4 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8550ve-debug@5 {
   compatible = "qcom,spmi-pmic";
   reg = <0x5 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8550vs-debug@6 {
   compatible = "qcom,spmi-pmic";
   reg = <0x6 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8550b-debug@7 {
   compatible = "qcom,spmi-pmic";
   reg = <0x7 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pmr735d-debug@a {
   compatible = "qcom,spmi-pmic";
   reg = <0xa 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pmr735d-debug@b {
   compatible = "qcom,spmi-pmic";
   reg = <0xb 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8010-debug@c {
   compatible = "qcom,spmi-pmic";
   reg = <0xc 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };

  qcom,pm8010-debug@d {
   compatible = "qcom,spmi-pmic";
   reg = <0xd 0>;
   #address-cells = <2>;
   #size-cells = <0>;
   qcom,can-sleep;
  };
 };

 qcom,test-dbl {
  compatible = "qcom,gh-dbl";
  qcom,label = <0x4>;
 };

 qcom,gh-qtimer@17425000 {
  compatible = "qcom,gh-qtmr";
  reg = <0x17425000 0x1000>;
  reg-names = "qtmr-base";
  interrupts = <0 10 4>;
  interrupt-names = "qcom,qtmr-intr";
  qcom,primary;
 };

 qcom,test-msgq {
  compatible = "qcom,gh-msgq-test";
  gunyah-label = <4>;
  qcom,primary;
 };

 qcom,pmic_glink {
  compatible = "qcom,pmic-glink";
  qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
  qcom,subsys-name = "lpass";
  qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
  depends-on-supply = <&ipcc_mproc>;

  battery_charger: qcom,battery_charger {
   compatible = "qcom,battery-charger";
  };

  ucsi: qcom,ucsi {
   compatible = "qcom,ucsi-glink";
  };

  altmode: qcom,altmode {
   compatible = "qcom,altmode-glink";
   #altmode-cells = <1>;
  };
 };

 qcom,pmic_glink_log {
  compatible = "qcom,pmic-glink";
  qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";

  qcom,battery_debug {
   compatible = "qcom,battery-debug";
  };

  qcom,charger_ulog_glink {
   compatible = "qcom,charger-ulog-glink";
  };

  qcom,spmi_glink_debug {
   compatible = "qcom,spmi-glink-debug";
   #address-cells = <1>;
   #size-cells = <0>;
   depends-on-supply = <&spmi1_bus>;


   spmi@0 {
    reg = <0>;
    #address-cells = <2>;
    #size-cells = <0>;

    qcom,pm8550b-debug@7 {
     compatible = "qcom,spmi-pmic";
     reg = <0x7 0>;
     qcom,can-sleep;
    };
   };


   spmi@1 {
    reg = <1>;
    #address-cells = <2>;
    #size-cells = <0>;

    smb1394_glink_debug: qcom,smb1394-debug@9 {
     compatible = "qcom,spmi-pmic";
     reg = <0x9 0>;
     qcom,can-sleep;
    };

    qcom,smb1394-debug@b {
     compatible = "qcom,spmi-pmic";
     reg = <0xb 0>;
     qcom,can-sleep;
    };

    qcom,smb1398-debug@d {
     compatible = "qcom,spmi-pmic";
     reg = <0xd 0>;
     qcom,can-sleep;
    };
   };
  };
 };

 msm_gpu: qcom,kgsl-3d0@3d00000 { };

 google,debug-kinfo {
  compatible = "google,debug-kinfo";
  memory-region = <&kinfo_mem>;
 };
};

&firmware {
 qcom_scm {
  compatible = "qcom,scm";
  qcom,dload-mode = <&tcsr 0x19000>;
 };

 android {
  compatible = "android,firmware";
  vbmeta {
   compatible = "android,vbmeta";
   parts = "vbmeta,boot,system,vendor,dtbo,recovery";
  };

  fstab {
   compatible = "android,fstab";
   vendor {
    compatible = "android,vendor";
    dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
    type = "ext4";
    mnt_flags = "ro,barrier=1,discard";
    fsmgr_flags = "wait,slotselect,avb";
    status = "ok";
   };
  };
 };

 qcom_smcinvoke {
  compatible = "qcom,smcinvoke";
 };

 qtee_shmbridge {
  compatible = "qcom,tee-shared-memory-bridge";
 };
};

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/ipcc-test.dtsi" 1


&soc {
 ipcc_self_ping_apss: ipcc-self-ping-apss {
  compatible = "qcom,ipcc-self-ping";
  interrupts-extended = <&ipcc_mproc 8
   2 4>;
  mboxes = <&ipcc_mproc 8 2>;
 };

 ipcc_self_ping_cdsp: ipcc-self-ping-cdsp {
  compatible = "qcom,ipcc-self-ping";
  interrupts-extended = <&ipcc_mproc 6
    3 4>;
  mboxes = <&ipcc_mproc 6 3>;
 };

 ipcc_self_ping_adsp: ipcc-self-ping-adsp {
  compatible = "qcom,ipcc-self-ping";
  interrupts-extended = <&ipcc_mproc 3
    3 4>;
  mboxes = <&ipcc_mproc 3 3>;
 };

 ipcc_self_ping_slpi: ipcc-self-ping-slpi {
  compatible = "qcom,ipcc-self-ping";
  interrupts-extended = <&ipcc_mproc 4
    3 4>;
  mboxes = <&ipcc_mproc 4 3>;
 };
};
# 3662 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-pinctrl.dtsi" 1
&tlmm {
 qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
  qupv3_se7_2uart_tx_active: qupv3_se7_2uart_tx_active {
   mux {
    pins = "gpio26";
    function = "qup1_se7_l2";
   };

   config {
    pins = "gpio26";
    drive-strength = <2>;
    bias-disable;
   };
  };

  qupv3_se7_2uart_rx_active: qupv3_se7_2uart_rx_active {
   mux {
    pins = "gpio27";
    function = "qup1_se7_l3";
   };

   config {
    pins = "gpio27";
    drive-strength = <2>;
    bias-disable;
   };
  };

  qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
   mux {
    pins = "gpio26", "gpio27";
    function = "gpio";
   };

   config {
    pins = "gpio26", "gpio27";
    drive-strength = <2>;
    bias-pull-down;
   };
  };
 };

 gamepad_gpio_key {
  gpio_key_active: gpio_key_active {
   mux {
    pins = "gpio0", "gpio14", "gpio15", "gpio40",
     "gpio48", "gpio56", "gpio59", "gpio60",
     "gpio62", "gpio63", "gpio73", "gpio75",
     "gpio85", "gpio87", "gpio89", "gpio119",
     "gpio137";
    function = "gpio";
   };

   config {
    pins = "gpio0", "gpio14", "gpio15", "gpio40",
     "gpio48", "gpio56", "gpio59", "gpio60",
     "gpio62", "gpio63", "gpio73", "gpio75",
     "gpio85", "gpio87", "gpio89", "gpio119",
     "gpio137";
    drive-strength = <2>;
    input-enable;
    input;
    bias-pull-up;
   };
  };

  gpio_key_suspend: gpio_key_suspend {
   mux {
    pins = "gpio0", "gpio14", "gpio15", "gpio40",
     "gpio48", "gpio56", "gpio59", "gpio60",
     "gpio62", "gpio63", "gpio73", "gpio75",
     "gpio85", "gpio87", "gpio89", "gpio119",
     "gpio137";
    function = "gpio";
   };

   config {
    pins = "gpio0", "gpio14", "gpio15", "gpio40",
     "gpio48", "gpio56", "gpio59", "gpio60",
     "gpio62", "gpio63", "gpio73", "gpio75",
     "gpio85", "gpio87", "gpio89", "gpio119",
     "gpio137";
    drive-strength = <2>;
    input-enable;
    input;
    bias-pull-up;
   };
  };
 };


 trigout_a: trigout_a {
  mux {
   pins = "gpio10";
   function = "qdss_cti";
  };

  config {
   pins = "gpio10";
   drive-strength = <2>;
   bias-disable;
  };
 };

 qupv3_se14_4uart_pins: qupv3_se14_4uart_pins {
  qupv3_se14_default_cts: qupv3_se14_default_cts {
   mux {
    pins = "gpio76";
    function = "gpio";
   };

   config {
    pins = "gpio76";
    drive-strength = <2>;
    bias-disable;
   };
  };

  qupv3_se14_default_rts: qupv3_se14_default_rts {
   mux {
    pins = "gpio77";
    function = "gpio";
   };

   config {
    pins = "gpio77";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  qupv3_se14_default_tx: qupv3_se14_default_tx {
   mux {
    pins = "gpio78";
    function = "gpio";
   };

   config {
    pins = "gpio78";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se14_default_rx: qupv3_se14_default_rx {
   mux {
    pins = "gpio79";
    function = "gpio";
   };

   config {
    pins = "gpio79";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  qupv3_se14_cts: qupv3_se14_cts {
   mux {
    pins = "gpio76";
    function = "qup2_se6_l0";
   };

   config {
    pins = "gpio76";
    drive-strength = <2>;
    bias-disable;
   };
  };

  qupv3_se14_rts: qupv3_se14_rts {
   mux {
    pins = "gpio77";
    function = "qup2_se6_l1";
   };

   config {
    pins = "gpio77";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  qupv3_se14_tx: qupv3_se14_tx {
   mux {
    pins = "gpio78";
    function = "qup2_se6_l2";
   };

   config {
    pins = "gpio78";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se14_rx: qupv3_se14_rx {
   mux {
    pins = "gpio79";
    function = "qup2_se6_l3";
   };

   config {
    pins = "gpio79";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se0_i3c_pins: qupv3_se0_i3c_pins {
  qupv3_se0_i3c_sda_active: qupv3_se0_i3c_sda_active {
   mux {
    pins = "gpio28";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio28";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se0_i3c_scl_active: qupv3_se0_i3c_scl_active {
   mux {
    pins = "gpio29";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio29";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se0_i3c_sda_sleep: qupv3_se0_i3c_sda_sleep {
   mux {
    pins = "gpio28";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio28";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se0_i3c_scl_sleep: qupv3_se0_i3c_scl_sleep {
   mux {
    pins = "gpio29";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio29";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se0_i3c_disable: qupv3_se0_i3c_disable {
   mux {
    pins = "gpio28", "gpio29";
    function = "gpio";
   };

   config {
    pins = "gpio28", "gpio29";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
  qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
   mux {
    pins = "gpio28";
    function = "qup1_se0_l0";
   };

   config {
    pins = "gpio28";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
   mux {
    pins = "gpio29";
    function = "qup1_se0_l1";
   };

   config {
    pins = "gpio29";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
   mux {
    pins = "gpio28", "gpio29";
    function = "gpio";
   };

   config {
    pins = "gpio28", "gpio29";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se0_spi_pins: qupv3_se0_spi_pins {
  qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active {
   mux {
    pins = "gpio28";
    function = "qup1_se0_l0";
   };

   config {
    pins = "gpio28";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active {
   mux {
    pins = "gpio29";
    function = "qup1_se0_l1";
   };

   config {
    pins = "gpio29";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active {
   mux {
    pins = "gpio30";
    function = "qup1_se0_l2";
   };

   config {
    pins = "gpio30";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
   mux {
    pins = "gpio31";
    function = "qup1_se0_l3";
   };

   config {
    pins = "gpio31";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
   mux {
    pins = "gpio28", "gpio29",
     "gpio30", "gpio31";
    function = "gpio";
   };

   config {
    pins = "gpio28", "gpio29",
     "gpio30", "gpio31";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
  qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active {
   mux {
    pins = "gpio32";
    function = "qup1_se1_l0";
   };

   config {
    pins = "gpio32";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active {
   mux {
    pins = "gpio33";
    function = "qup1_se1_l1";
   };

   config {
    pins = "gpio33";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
   mux {
    pins = "gpio32", "gpio33";
    function = "gpio";
   };

   config {
    pins = "gpio32", "gpio33";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se1_i3c_pins: qupv3_se1_i3c_pins {
  qupv3_se1_i3c_sda_active: qupv3_se1_i3c_sda_active {
   mux {
    pins = "gpio32";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio32";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se1_i3c_scl_active: qupv3_se1_i3c_scl_active {
   mux {
    pins = "gpio33";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio33";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se1_i3c_sda_sleep: qupv3_se1_i3c_sda_sleep {
   mux {
    pins = "gpio32";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio32";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se1_i3c_scl_sleep: qupv3_se1_i3c_scl_sleep {
   mux {
    pins = "gpio33";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio33";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se1_i3c_disable: qupv3_se1_i3c_disable {
   mux {
    pins = "gpio32", "gpio33";
    function = "gpio";
   };

   config {
    pins = "gpio32", "gpio33";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };


 qupv3_se1_spi_pins: qupv3_se1_spi_pins {
  qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
   mux {
    pins = "gpio32";
    function = "qup1_se1_l0";
   };

   config {
    pins = "gpio32";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
   mux {
    pins = "gpio33";
    function = "qup1_se1_l1";
   };

   config {
    pins = "gpio33";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
   mux {
    pins = "gpio34";
    function = "qup1_se1_l2";
   };

   config {
    pins = "gpio34";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
   mux {
    pins = "gpio35";
    function = "qup1_se1_l3";
   };

   config {
    pins = "gpio35";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
   mux {
    pins = "gpio32", "gpio33",
     "gpio34", "gpio35";
    function = "gpio";
   };

   config {
    pins = "gpio32", "gpio33",
     "gpio34", "gpio35";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
  qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
   mux {
    pins = "gpio36";
    function = "qup1_se2_l0";
   };

   config {
    pins = "gpio36";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
   mux {
    pins = "gpio37";
    function = "qup1_se2_l1";
   };

   config {
    pins = "gpio37";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
   mux {
    pins = "gpio36", "gpio37";
    function = "gpio";
   };

   config {
    pins = "gpio36", "gpio37";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se2_spi_pins: qupv3_se2_spi_pins {
  qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
   mux {
    pins = "gpio36";
    function = "qup1_se2_l0";
   };

   config {
    pins = "gpio36";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
   mux {
    pins = "gpio37";
    function = "qup1_se2_l1";
   };

   config {
    pins = "gpio37";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
   mux {
    pins = "gpio38";
    function = "qup1_se2_l2";
   };

   config {
    pins = "gpio38";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
   mux {
    pins = "gpio39";
    function = "qup1_se2_l3";
   };

   config {
    pins = "gpio39";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
   mux {
    pins = "gpio36", "gpio37",
     "gpio38", "gpio39";
    function = "gpio";
   };

   config {
    pins = "gpio36", "gpio37",
     "gpio38", "gpio39";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
  qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active {
   mux {
    pins = "gpio40";
    function = "qup1_se3_l0";
   };

   config {
    pins = "gpio40";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active {
   mux {
    pins = "gpio41";
    function = "qup1_se3_l1";
   };

   config {
    pins = "gpio41";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
   mux {
    pins = "gpio40", "gpio41";
    function = "gpio";
   };

   config {
    pins = "gpio40", "gpio41";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se3_spi_pins: qupv3_se3_spi_pins {
  qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active {
   mux {
    pins = "gpio40";
    function = "qup1_se3_l0";
   };

   config {
    pins = "gpio40";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active {
   mux {
    pins = "gpio41";
    function = "qup1_se3_l1";
   };

   config {
    pins = "gpio41";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active {
   mux {
    pins = "gpio42";
    function = "qup1_se3_l2";
   };

   config {
    pins = "gpio42";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active {
   mux {
    pins = "gpio43";
    function = "qup1_se3_l3";
   };

   config {
    pins = "gpio43";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
   mux {
    pins = "gpio40", "gpio41",
     "gpio42", "gpio43";
    function = "gpio";
   };

   config {
    pins = "gpio40", "gpio41",
     "gpio42", "gpio43";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
  qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active {
   mux {
    pins = "gpio44";
    function = "qup1_se4_l0";
   };

   config {
    pins = "gpio44";
    drive-strength = <2>;
    bias-pull-up;
    qcom,i2c_pull;
   };
  };

  qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active {
   mux {
    pins = "gpio45";
    function = "qup1_se4_l1";
   };

   config {
    pins = "gpio45";
    drive-strength = <2>;
    bias-pull-up;
    qcom,i2c_pull;
   };
  };

  qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
   mux {
    pins = "gpio44", "gpio45";
    function = "gpio";
   };

   config {
    pins = "gpio44", "gpio45";
    drive-strength = <2>;

   };
  };
 };

 qupv3_se4_spi_pins: qupv3_se4_spi_pins {
  qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active {
   mux {
    pins = "gpio44";
    function = "qup1_se4_l0";
   };

   config {
    pins = "gpio44";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active {
   mux {
    pins = "gpio45";
    function = "qup1_se4_l1";
   };

   config {
    pins = "gpio45";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active {
   mux {
    pins = "gpio46";
    function = "qup1_se4_l2";
   };

   config {
    pins = "gpio46";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active {
   mux {
    pins = "gpio47";
    function = "qup1_se4_l3";
   };

   config {
    pins = "gpio47";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
   mux {
    pins = "gpio44", "gpio45",
     "gpio46", "gpio47";
    function = "gpio";
   };

   config {
    pins = "gpio44", "gpio45",
     "gpio46", "gpio47";
    drive-strength = <6>;
    bias-pull-down;
   };
  };
 };
 qupv3_se4_4uart_pins: qupv3_se4_4uart_pins {
  qupv3_se4_default_cts: qupv3_se4_default_cts {
   mux {
    pins = "gpio44";
    function = "gpio";
   };

   config {
    pins = "gpio44";
    drive-strength = <2>;
    bias-disable;
   };
  };

  qupv3_se4_default_rts: qupv3_se4_default_rts {
   mux {
    pins = "gpio45";
    function = "gpio";
   };

   config {
    pins = "gpio45";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  qupv3_se4_default_tx: qupv3_se4_default_tx {
   mux {
    pins = "gpio46";
    function = "gpio";
   };

   config {
    pins = "gpio46";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se4_default_rx: qupv3_se4_default_rx {
   mux {
    pins = "gpio47";
    function = "gpio";
   };

   config {
    pins = "gpio47";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  qupv3_se4_cts: qupv3_se4_cts {
   mux {
    pins = "gpio44";
    function = "qup1_se4_l0";
   };

   config {
    pins = "gpio44";
    drive-strength = <2>;
    bias-disable;
   };
  };

  qupv3_se4_rts: qupv3_se4_rts {
   mux {
    pins = "gpio45";
    function = "qup1_se4_l1";
   };

   config {
    pins = "gpio45";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  qupv3_se4_tx: qupv3_se4_tx {
   mux {
    pins = "gpio46";
    function = "qup1_se4_l2";
   };

   config {
    pins = "gpio46";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se4_rx: qupv3_se4_rx {
   mux {
    pins = "gpio47";
    function = "qup1_se4_l3";
   };

   config {
    pins = "gpio47";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
  qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active {
   mux {
    pins = "gpio52";
    function = "qup1_se5_l0";
   };

   config {
    pins = "gpio52";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active {
   mux {
    pins = "gpio53";
    function = "qup1_se5_l1";
   };

   config {
    pins = "gpio53";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
   mux {
    pins = "gpio52", "gpio53";
    function = "gpio";
   };

   config {
    pins = "gpio52", "gpio53";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se5_spi_pins: qupv3_se5_spi_pins {
  qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active {
   mux {
    pins = "gpio52";
    function = "qup1_se5_l0";
   };

   config {
    pins = "gpio52";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active {
   mux {
    pins = "gpio53";
    function = "qup1_se5_l1";
   };

   config {
    pins = "gpio53";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active {
   mux {
    pins = "gpio54";
    function = "qup1_se5_l2";
   };

   config {
    pins = "gpio54";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active {
   mux {
    pins = "gpio55";
    function = "qup1_se5_l3";
   };

   config {
    pins = "gpio55";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
   mux {
    pins = "gpio52", "gpio53",
     "gpio54", "gpio55";
    function = "gpio";
   };

   config {
    pins = "gpio52", "gpio53",
     "gpio54", "gpio55";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
  qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active {
   mux {
    pins = "gpio48";
    function = "qup1_se6_l0";
   };

   config {
    pins = "gpio48";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active {
   mux {
    pins = "gpio49";
    function = "qup1_se6_l1";
   };

   config {
    pins = "gpio49";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
   mux {
    pins = "gpio48", "gpio49";
    function = "gpio";
   };

   config {
    pins = "gpio48", "gpio49";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se6_spi_pins: qupv3_se6_spi_pins {
  qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active {
   mux {
    pins = "gpio48";
    function = "qup1_se6_l0";
   };

   config {
    pins = "gpio48";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active {
   mux {
    pins = "gpio49";
    function = "qup1_se6_l1";
   };

   config {
    pins = "gpio49";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active {
   mux {
    pins = "gpio50";
    function = "qup1_se6_l2";
   };

   config {
    pins = "gpio50";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active {
   mux {
    pins = "gpio51";
    function = "qup1_se6_l3";
   };

   config {
    pins = "gpio51";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
   mux {
    pins = "gpio48", "gpio49",
     "gpio50", "gpio51";
    function = "gpio";
   };

   config {
    pins = "gpio48", "gpio49",
     "gpio50", "gpio51";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
  qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active {
   mux {
    pins = "gpio56";
    function = "qup2_se0_l0_mira";
   };

   config {
    pins = "gpio56";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active {
   mux {
    pins = "gpio57";
    function = "qup2_se0_l1_mira";
   };

   config {
    pins = "gpio57";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
   mux {
    pins = "gpio56", "gpio57";
    function = "gpio";
   };

   config {
    pins = "gpio56", "gpio57";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se8_i3c_pins: qupv3_se8_i3c_pins {
  qupv3_se8_i3c_sda_active: qupv3_se8_i3c_sda_active {
   mux {
    pins = "gpio56";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio56";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se8_i3c_scl_active: qupv3_se8_i3c_scl_active {
   mux {
    pins = "gpio57";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio57";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se8_i3c_sda_sleep: qupv3_se8_i3c_sda_sleep {
   mux {
    pins = "gpio56";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio56";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se8_i3c_scl_sleep: qupv3_se8_i3c_scl_sleep {
   mux {
    pins = "gpio57";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio57";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se8_i3c_disable: qupv3_se8_i3c_disable {
   mux {
    pins = "gpio56", "gpio57";
    function = "gpio";
   };

   config {
    pins = "gpio56", "gpio57";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };


 qupv3_se8_spi_pins: qupv3_se8_spi_pins {
  qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active {
   mux {
    pins = "gpio56";
    function = "qup2_se0_l0_mira";
   };

   config {
    pins = "gpio56";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active {
   mux {
    pins = "gpio57";
    function = "qup2_se0_l1_mira";
   };

   config {
    pins = "gpio57";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active {
   mux {
    pins = "gpio58";
    function = "qup2_se0_l2_mira";
   };

   config {
    pins = "gpio58";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active {
   mux {
    pins = "gpio59";
    function = "qup2_se0_l3_mira";
   };

   config {
    pins = "gpio59";
    drive-strength = <6>;
    bias-pull-down;
   };
  };

  qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
   mux {
    pins = "gpio56", "gpio57",
     "gpio58", "gpio59";
    function = "gpio";
   };

   config {
    pins = "gpio56", "gpio57",
     "gpio58", "gpio59";
    drive-strength = <2>;
    bias-pull-down;
   };
  };
 };

 qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
  qupv3_se9_i2c_sda_active: qupv3_se9_i2c_sda_active {
   mux {
    pins = "gpio60";
    function = "qup2_se1_l0";
   };

   config {
    pins = "gpio60";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se9_i2c_scl_active: qupv3_se9_i2c_scl_active {
   mux {
    pins = "gpio61";
    function = "qup2_se1_l1";
   };

   config {
    pins = "gpio61";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
   mux {
    pins = "gpio60", "gpio61";
    function = "gpio";
   };

   config {
    pins = "gpio60", "gpio61";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se9_i3c_pins: qupv3_se9_i3c_pins {
  qupv3_se9_i3c_sda_active: qupv3_se9_i3c_sda_active {
   mux {
    pins = "gpio60";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio60";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se9_i3c_scl_active: qupv3_se9_i3c_scl_active {
   mux {
    pins = "gpio61";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio61";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se9_i3c_sda_sleep: qupv3_se9_i3c_sda_sleep {
   mux {
    pins = "gpio60";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio60";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se9_i3c_scl_sleep: qupv3_se9_i3c_scl_sleep {
   mux {
    pins = "gpio61";
    function = "ibi_i3c";
   };

   config {
    pins = "gpio61";
    drive-strength = <16>;
    bias-pull-up;
   };
  };

  qupv3_se9_i3c_disable: qupv3_se9_i3c_disable {
   mux {
    pins = "gpio60", "gpio61";
    function = "gpio";
   };

   config {
    pins = "gpio60", "gpio61";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };


 qupv3_se9_spi_pins: qupv3_se9_spi_pins {
  qupv3_se9_spi_miso_active: qupv3_se9_spi_miso_active {
   mux {
    pins = "gpio60";
    function = "qup2_se1_l0";
   };

   config {
    pins = "gpio60";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se9_spi_mosi_active: qupv3_se9_spi_mosi_active {
   mux {
    pins = "gpio61";
    function = "qup2_se1_l1";
   };

   config {
    pins = "gpio61";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se9_spi_clk_active: qupv3_se9_spi_clk_active {
   mux {
    pins = "gpio62";
    function = "qup2_se1_l2";
   };

   config {
    pins = "gpio62";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se9_spi_cs_active: qupv3_se9_spi_cs_active {
   mux {
    pins = "gpio63";
    function = "qup2_se1_l3";
   };

   config {
    pins = "gpio63";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
   mux {
    pins = "gpio60", "gpio61",
     "gpio62", "gpio63";
    function = "gpio";
   };

   config {
    pins = "gpio60", "gpio61",
     "gpio62", "gpio63";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
  qupv3_se10_i2c_sda_active: qupv3_se10_i2c_sda_active {
   mux {
    pins = "gpio64";
    function = "qup2_se2_l0";
   };

   config {
    pins = "gpio64";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se10_i2c_scl_active: qupv3_se10_i2c_scl_active {
   mux {
    pins = "gpio65";
    function = "qup2_se2_l1";
   };

   config {
    pins = "gpio65";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
   mux {
    pins = "gpio64", "gpio65";
    function = "gpio";
   };

   config {
    pins = "gpio64", "gpio65";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se10_spi_pins: qupv3_se10_spi_pins {
  qupv3_se10_spi_miso_active: qupv3_se10_spi_miso_active {
   mux {
    pins = "gpio64";
    function = "qup2_se2_l0";
   };

   config {
    pins = "gpio64";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se10_spi_mosi_active: qupv3_se10_spi_mosi_active {
   mux {
    pins = "gpio65";
    function = "qup2_se2_l1";
   };

   config {
    pins = "gpio65";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se10_spi_clk_active: qupv3_se10_spi_clk_active {
   mux {
    pins = "gpio66";
    function = "qup2_se2_l2";
   };

   config {
    pins = "gpio66";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se10_spi_cs_active: qupv3_se10_spi_cs_active {
   mux {
    pins = "gpio67";
    function = "qup2_se2_l3";
   };

   config {
    pins = "gpio67";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
   mux {
    pins = "gpio64", "gpio65",
     "gpio66", "gpio67";
    function = "gpio";
   };

   config {
    pins = "gpio64", "gpio65",
     "gpio66", "gpio67";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
  qupv3_se11_i2c_sda_active: qupv3_se11_i2c_sda_active {
   mux {
    pins = "gpio68";
    function = "qup2_se3_l0";
   };

   config {
    pins = "gpio68";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se11_i2c_scl_active: qupv3_se11_i2c_scl_active {
   mux {
    pins = "gpio69";
    function = "qup2_se3_l1";
   };

   config {
    pins = "gpio69";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
   mux {
    pins = "gpio68", "gpio69";
    function = "gpio";
   };

   config {
    pins = "gpio68", "gpio69";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se11_spi_pins: qupv3_se11_spi_pins {
  qupv3_se11_spi_miso_active: qupv3_se11_spi_miso_active {
   mux {
    pins = "gpio68";
    function = "qup2_se3_l0";
   };

   config {
    pins = "gpio68";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se11_spi_mosi_active: qupv3_se11_spi_mosi_active {
   mux {
    pins = "gpio69";
    function = "qup2_se3_l1";
   };

   config {
    pins = "gpio69";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se11_spi_clk_active: qupv3_se11_spi_clk_active {
   mux {
    pins = "gpio70";
    function = "qup2_se3_l2";
   };

   config {
    pins = "gpio70";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se11_spi_cs_active: qupv3_se11_spi_cs_active {
   mux {
    pins = "gpio71";
    function = "qup2_se3_l3";
   };

   config {
    pins = "gpio71";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
   mux {
    pins = "gpio68", "gpio69",
     "gpio70", "gpio71";
    function = "gpio";
   };

   config {
    pins = "gpio68", "gpio69",
     "gpio70", "gpio71";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
  qupv3_se12_i2c_sda_active: qupv3_se12_i2c_sda_active {
   mux {
    pins = "gpio2";
    function = "qup2_se4_l0";
   };

   config {
    pins = "gpio2";
    drive-strength = <2>;
    bias-pull-up;
    qcom,i2c_pull;
   };
  };

  qupv3_se12_i2c_scl_active: qupv3_se12_i2c_scl_active {
   mux {
    pins = "gpio3";
    function = "qup2_se4_l1";
   };

   config {
    pins = "gpio3";
    drive-strength = <2>;
    bias-pull-up;
    qcom,i2c_pull;
   };
  };

  qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
   mux {
    pins = "gpio2", "gpio3";
    function = "gpio";
   };

   config {
    pins = "gpio2", "gpio3";
    drive-strength = <2>;

   };
  };
 };

 qupv3_se12_spi_pins: qupv3_se12_spi_pins {
  qupv3_se12_spi_miso_active: qupv3_se12_spi_miso_active {
   mux {
    pins = "gpio2";
    function = "qup2_se4_l0";
   };

   config {
    pins = "gpio2";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se12_spi_mosi_active: qupv3_se12_spi_mosi_active {
   mux {
    pins = "gpio3";
    function = "qup2_se4_l1";
   };

   config {
    pins = "gpio3";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se12_spi_clk_active: qupv3_se12_spi_clk_active {
   mux {
    pins = "gpio118";
    function = "qup2_se4_l2";
   };

   config {
    pins = "gpio118";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se12_spi_cs_active: qupv3_se12_spi_cs_active {
   mux {
    pins = "gpio119";
    function = "qup2_se4_l3";
   };

   config {
    pins = "gpio119";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
   mux {
    pins = "gpio2", "gpio3",
     "gpio118", "gpio119";
    function = "gpio";
   };

   config {
    pins = "gpio2", "gpio3",
     "gpio118", "gpio119";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
  qupv3_se13_i2c_sda_active: qupv3_se13_i2c_sda_active {
   mux {
    pins = "gpio80";
    function = "qup2_se5_l0";
   };

   config {
    pins = "gpio80";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se13_i2c_scl_active: qupv3_se13_i2c_scl_active {
   mux {
    pins = "gpio81";
    function = "qup2_se5_l1";
   };

   config {
    pins = "gpio81";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
   mux {
    pins = "gpio80", "gpio81";
    function = "gpio";
   };

   config {
    pins = "gpio80", "gpio81";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se13_spi_pins: qupv3_se13_spi_pins {
  qupv3_se13_spi_miso_active: qupv3_se13_spi_miso_active {
   mux {
    pins = "gpio80";
    function = "qup2_se5_l0";
   };

   config {
    pins = "gpio80";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se13_spi_mosi_active: qupv3_se13_spi_mosi_active {
   mux {
    pins = "gpio81";
    function = "qup2_se5_l1";
   };

   config {
    pins = "gpio81";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se13_spi_clk_active: qupv3_se13_spi_clk_active {
   mux {
    pins = "gpio82";
    function = "qup2_se5_l2";
   };

   config {
    pins = "gpio82";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se13_spi_cs_active: qupv3_se13_spi_cs_active {
   mux {
    pins = "gpio83";
    function = "qup2_se5_l3";
   };

   config {
    pins = "gpio83";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
   mux {
    pins = "gpio80", "gpio81",
     "gpio82", "gpio83";
    function = "gpio";
   };

   config {
    pins = "gpio80", "gpio81",
     "gpio82", "gpio83";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
  qupv3_se15_i2c_sda_active: qupv3_se15_i2c_sda_active {
   mux {
    pins = "gpio72";
    function = "qup2_se7_l0";
   };

   config {
    pins = "gpio72";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se15_i2c_scl_active: qupv3_se15_i2c_scl_active {
   mux {
    pins = "gpio106";
    function = "qup2_se7_l1";
   };

   config {
    pins = "gpio106";
    drive-strength = <2>;
    bias-pull-up;

   };
  };

  qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
   mux {
    pins = "gpio72", "gpio106";
    function = "gpio";
   };

   config {
    pins = "gpio72", "gpio106";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 qupv3_se15_spi_pins: qupv3_se15_spi_pins {
  qupv3_se15_spi_miso_active: qupv3_se15_spi_miso_active {
   mux {
    pins = "gpio72";
    function = "qup2_se7_l0";
   };

   config {
    pins = "gpio72";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se15_spi_mosi_active: qupv3_se15_spi_mosi_active {
   mux {
    pins = "gpio106";
    function = "qup2_se7_l1";
   };

   config {
    pins = "gpio106";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se15_spi_clk_active: qupv3_se15_spi_clk_active {
   mux {
    pins = "gpio74";
    function = "qup2_se7_l2";
   };

   config {
    pins = "gpio74";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se15_spi_cs_active: qupv3_se15_spi_cs_active {
   mux {
    pins = "gpio75";
    function = "qup2_se7_l3";
   };

   config {
    pins = "gpio75";
    drive-strength = <6>;
    bias-disable;
   };
  };

  qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
   mux {
    pins = "gpio72", "gpio106",
     "gpio74", "gpio75";
    function = "gpio";
   };

   config {
    pins = "gpio72", "gpio106",
     "gpio74", "gpio75";
    drive-strength = <6>;
    bias-disable;
   };
  };
 };

 qupv3_hub_i2c0_pins: qupv3_hub_i2c0_pins {
  qupv3_hub_i2c0_sda_active: qupv3_hub_i2c0_sda_active {
   mux {
    pins = "gpio16";
    function = "i2chub0_se0_l0";
   };

   config {
    pins = "gpio16";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c0_scl_active: qupv3_hub_i2c0_scl_active {
   mux {
    pins = "gpio17";
    function = "i2chub0_se0_l1";
   };

   config {
    pins = "gpio17";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c0_sleep: qupv3_hub_i2c0_sleep {
   mux {
    pins = "gpio16", "gpio17";
    function = "gpio";
   };

   config {
    pins = "gpio16", "gpio17";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c1_pins: qupv3_hub_i2c1_pins {
  qupv3_hub_i2c1_sda_active: qupv3_hub_i2c1_sda_active {
   mux {
    pins = "gpio18";
    function = "i2chub0_se1_l0";
   };

   config {
    pins = "gpio18";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c1_scl_active: qupv3_hub_i2c1_scl_active {
   mux {
    pins = "gpio19";
    function = "i2chub0_se1_l1";
   };

   config {
    pins = "gpio19";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c1_sleep: qupv3_hub_i2c1_sleep {
   mux {
    pins = "gpio18", "gpio19";
    function = "gpio";
   };

   config {
    pins = "gpio18", "gpio19";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c2_pins: qupv3_hub_i2c2_pins {
  qupv3_hub_i2c2_sda_active: qupv3_hub_i2c2_sda_active {
   mux {
    pins = "gpio20";
    function = "i2chub0_se2_l0";
   };

   config {
    pins = "gpio20";
    drive-strength = <2>;
    bias-pull-up;
    qcom,i2c_pull;
   };
  };

  qupv3_hub_i2c2_scl_active: qupv3_hub_i2c2_scl_active {
   mux {
    pins = "gpio21";
    function = "i2chub0_se2_l1";
   };

   config {
    pins = "gpio21";
    drive-strength = <2>;
    bias-pull-up;
    qcom,i2c_pull;
   };
  };

  qupv3_hub_i2c2_sleep: qupv3_hub_i2c2_sleep {
   mux {
    pins = "gpio20", "gpio21";
    function = "gpio";
   };

   config {
    pins = "gpio20", "gpio21";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c3_pins: qupv3_hub_i2c3_pins {
  qupv3_hub_i2c3_sda_active: qupv3_hub_i2c3_sda_active {
   mux {
    pins = "gpio22";
    function = "i2chub0_se3_l0";
   };

   config {
    pins = "gpio22";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c3_scl_active: qupv3_hub_i2c3_scl_active {
   mux {
    pins = "gpio23";
    function = "i2chub0_se3_l1";
   };

   config {
    pins = "gpio23";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c3_sleep: qupv3_hub_i2c3_sleep {
   mux {
    pins = "gpio22", "gpio23";
    function = "gpio";
   };

   config {
    pins = "gpio22", "gpio23";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c4_pins: qupv3_hub_i2c4_pins {
  qupv3_hub_i2c4_sda_active: qupv3_hub_i2c4_sda_active {
   mux {
    pins = "gpio4";
    function = "i2chub0_se4_l0";
   };

   config {
    pins = "gpio4";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c4_scl_active: qupv3_hub_i2c4_scl_active {
   mux {
    pins = "gpio5";
    function = "i2chub0_se4_l1";
   };

   config {
    pins = "gpio5";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c4_sleep: qupv3_hub_i2c4_sleep {
   mux {
    pins = "gpio4", "gpio5";
    function = "gpio";
   };

   config {
    pins = "gpio4", "gpio5";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c5_pins: qupv3_hub_i2c5_pins {
  qupv3_hub_i2c5_sda_active: qupv3_hub_i2c5_sda_active {
   mux {
    pins = "gpio6";
    function = "i2chub0_se5_l0";
   };

   config {
    pins = "gpio6";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c5_scl_active: qupv3_hub_i2c5_scl_active {
   mux {
    pins = "gpio7";
    function = "i2chub0_se5_l1";
   };

   config {
    pins = "gpio7";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c5_sleep: qupv3_hub_i2c5_sleep {
   mux {
    pins = "gpio6", "gpio7";
    function = "gpio";
   };

   config {
    pins = "gpio6", "gpio7";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c6_pins: qupv3_hub_i2c6_pins {
  qupv3_hub_i2c6_sda_active: qupv3_hub_i2c6_sda_active {
   mux {
    pins = "gpio8";
    function = "i2chub0_se6_l0";
   };

   config {
    pins = "gpio8";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c6_scl_active: qupv3_hub_i2c6_scl_active {
   mux {
    pins = "gpio9";
    function = "i2chub0_se6_l1";
   };

   config {
    pins = "gpio9";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c6_sleep: qupv3_hub_i2c6_sleep {
   mux {
    pins = "gpio8", "gpio9";
    function = "gpio";
   };

   config {
    pins = "gpio8", "gpio9";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c7_pins: qupv3_hub_i2c7_pins {
  qupv3_hub_i2c7_sda_active: qupv3_hub_i2c7_sda_active {
   mux {
    pins = "gpio10";
    function = "i2chub0_se7_l0";
   };

   config {
    pins = "gpio10";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c7_scl_active: qupv3_hub_i2c7_scl_active {
   mux {
    pins = "gpio11";
    function = "i2chub0_se7_l1";
   };

   config {
    pins = "gpio11";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c7_sleep: qupv3_hub_i2c7_sleep {
   mux {
    pins = "gpio10", "gpio11";
    function = "gpio";
   };

   config {
    pins = "gpio10", "gpio11";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c8_pins: qupv3_hub_i2c8_pins {
  qupv3_hub_i2c8_sda_active: qupv3_hub_i2c8_sda_active {
   mux {
    pins = "gpio206";
    function = "i2chub0_se8_l0";
   };

   config {
    pins = "gpio206";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c8_scl_active: qupv3_hub_i2c8_scl_active {
   mux {
    pins = "gpio207";
    function = "i2chub0_se8_l1";
   };

   config {
    pins = "gpio207";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c8_sleep: qupv3_hub_i2c8_sleep {
   mux {
    pins = "gpio206", "gpio207";
    function = "gpio";
   };

   config {
    pins = "gpio206", "gpio207";
    drive-strength = <2>;
   };
  };
 };

 qupv3_hub_i2c9_pins: qupv3_hub_i2c9_pins {
  qupv3_hub_i2c9_sda_active: qupv3_hub_i2c9_sda_active {
   mux {
    pins = "gpio84";
    function = "i2chub0_se9_l0";
   };

   config {
    pins = "gpio84";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c9_scl_active: qupv3_hub_i2c9_scl_active {
   mux {
    pins = "gpio85";
    function = "i2chub0_se9_l1";
   };

   config {
    pins = "gpio85";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  qupv3_hub_i2c9_sleep: qupv3_hub_i2c9_sleep {
   mux {
    pins = "gpio84", "gpio85";
    function = "gpio";
   };

   config {
    pins = "gpio84", "gpio85";
    drive-strength = <2>;
   };
  };
 };

 sdc2_on: sdc2_on {
  clk {
   pins = "sdc2_clk";
   bias-disable;
   drive-strength = <16>;
  };

  cmd {
   pins = "sdc2_cmd";
   bias-pull-up;
   drive-strength = <10>;
  };

  data {
   pins = "sdc2_data";
   bias-pull-up;
   drive-strength = <10>;
  };
 };

 sdc2_off: sdc2_off {
  clk {
   pins = "sdc2_clk";
   bias-disable;
   drive-strength = <2>;
  };

  cmd {
   pins = "sdc2_cmd";
   bias-pull-up;
   drive-strength = <2>;
  };

  data {
   pins = "sdc2_data";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 aux0_pcm_clk {
  aux0_pcm_clk_sleep: aux0_pcm_clk_sleep {
   mux {
    pins = "gpio126";
    function = "gpio";
   };

   config {
    pins = "gpio126";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux0_pcm_clk_active: aux0_pcm_clk_active {
   mux {
    pins = "gpio126";
    function = "i2s0_sck";
   };

   config {
    pins = "gpio126";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 aux0_pcm_ws {
  aux0_pcm_ws_sleep: aux0_pcm_ws_sleep {
   mux {
    pins = "gpio129";
    function = "gpio";
   };

   config {
    pins = "gpio129";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux0_pcm_ws_active: aux0_pcm_ws_active {
   mux {
    pins = "gpio129";
    function = "i2s0_ws";
   };

   config {
    pins = "gpio129";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 aux0_pcm_din {
  aux0_pcm_din_sleep: aux0_pcm_din_sleep {
   mux {
    pins = "gpio127";
    function = "gpio";
   };

   config {
    pins = "gpio127";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux0_pcm_din_active: aux0_pcm_din_active {
   mux {
    pins = "gpio127";
    function = "i2s0_data0";
   };

   config {
    pins = "gpio127";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 aux0_pcm_dout {
  aux0_pcm_dout_sleep: aux0_pcm_dout_sleep {
   mux {
    pins = "gpio128";
    function = "gpio";
   };

   config {
    pins = "gpio128";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux0_pcm_dout_active: aux0_pcm_dout_active {
   mux {
    pins = "gpio128";
    function = "i2s0_data1";
   };

   config {
    pins = "gpio128";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 aux1_pcm_clk {
  aux1_pcm_clk_sleep: aux1_pcm_clk_sleep {
   mux {
    pins = "gpio121";
    function = "gpio";
   };

   config {
    pins = "gpio121";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux1_pcm_clk_active: aux1_pcm_clk_active {
   mux {
    pins = "gpio121";
    function = "i2s1_sck";
   };

   config {
    pins = "gpio121";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 aux1_pcm_ws {
  aux1_pcm_ws_sleep: aux1_pcm_ws_sleep {
   mux {
    pins = "gpio123";
    function = "gpio";
   };

   config {
    pins = "gpio123";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux1_pcm_ws_active: aux1_pcm_ws_active {
   mux {
    pins = "gpio123";
    function = "i2s1_ws";
   };

   config {
    pins = "gpio123";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 aux1_pcm_din {
  aux1_pcm_din_sleep: aux1_pcm_din_sleep {
   mux {
    pins = "gpio122";
    function = "gpio";
   };

   config {
    pins = "gpio122";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux1_pcm_din_active: aux1_pcm_din_active {
   mux {
    pins = "gpio122";
    function = "i2s1_data0";
   };

   config {
    pins = "gpio122";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 aux1_pcm_dout {
  aux1_pcm_dout_sleep: aux1_pcm_dout_sleep {
   mux {
    pins = "gpio124";
    function = "gpio";
   };

   config {
    pins = "gpio124";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  aux1_pcm_dout_active: aux1_pcm_dout_active {
   mux {
    pins = "gpio124";
    function = "i2s1_data1";
   };

   config {
    pins = "gpio124";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 tdm0_clk {
  tdm0_clk_sleep: tdm0_clk_sleep {
   mux {
    pins = "gpio126";
    function = "gpio";
   };

   config {
    pins = "gpio126";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm0_clk_active: tdm0_clk_active {
   mux {
    pins = "gpio126";
    function = "i2s0_sck";
   };

   config {
    pins = "gpio126";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 tdm0_ws {
  tdm0_ws_sleep: tdm0_ws_sleep {
   mux {
    pins = "gpio129";
    function = "gpio";
   };

   config {
    pins = "gpio129";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm0_ws_active: tdm0_ws_active {
   mux {
    pins = "gpio129";
    function = "i2s0_ws";
   };

   config {
    pins = "gpio129";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 tdm0_din {
  tdm0_din_sleep: tdm0_din_sleep {
   mux {
    pins = "gpio127";
    function = "gpio";
   };

   config {
    pins = "gpio127";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm0_din_active: tdm0_din_active {
   mux {
    pins = "gpio127";
    function = "i2s0_data0";
   };

   config {
    pins = "gpio127";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 tdm0_dout {
  tdm0_dout_sleep: tdm0_dout_sleep {
   mux {
    pins = "gpio128";
    function = "gpio";
   };

   config {
    pins = "gpio128";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm0_dout_active: tdm0_dout_active {
   mux {
    pins = "gpio128";
    function = "i2s0_data1";
   };

   config {
    pins = "gpio128";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 tdm1_clk {
  tdm1_clk_sleep: tdm1_clk_sleep {
   mux {
    pins = "gpio121";
    function = "gpio";
   };

   config {
    pins = "gpio121";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm1_clk_active: tdm1_clk_active {
   mux {
    pins = "gpio121";
    function = "i2s1_sck";
   };

   config {
    pins = "gpio121";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 tdm1_ws {
  tdm1_ws_sleep: tdm1_ws_sleep {
   mux {
    pins = "gpio123";
    function = "gpio";
   };

   config {
    pins = "gpio123";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm1_ws_active: tdm1_ws_active {
   mux {
    pins = "gpio123";
    function = "i2s1_ws";
   };

   config {
    pins = "gpio123";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 tdm1_din {
  tdm1_din_sleep: tdm1_din_sleep {
   mux {
    pins = "gpio122";
    function = "gpio";
   };

   config {
    pins = "gpio122";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm1_din_active: tdm1_din_active {
   mux {
    pins = "gpio122";
    function = "i2s1_data0";
   };

   config {
    pins = "gpio122";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 tdm1_dout {
  tdm1_dout_sleep: tdm1_dout_sleep {
   mux {
    pins = "gpio124";
    function = "gpio";
   };

   config {
    pins = "gpio124";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  tdm1_dout_active: tdm1_dout_active {
   mux {
    pins = "gpio124";
    function = "i2s1_data1";
   };

   config {
    pins = "gpio124";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 i2s0_sck {
  i2s0_sck_sleep: i2s0_sck_sleep {
   mux {
    pins = "gpio126";
    function = "gpio";
   };

   config {
    pins = "gpio126";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s0_sck_active: i2s0_sck_active {
   mux {
    pins = "gpio126";
    function = "i2s0_sck";
   };

   config {
    pins = "gpio126";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 i2s0_ws {
  i2s0_ws_sleep: i2s0_ws_sleep {
   mux {
    pins = "gpio129";
    function = "gpio";
   };

   config {
    pins = "gpio129";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s0_ws_active: i2s0_ws_active {
   mux {
    pins = "gpio129";
    function = "i2s0_ws";
   };

   config {
    pins = "gpio129";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 i2s0_sd0 {
  i2s0_sd0_sleep: i2s0_sd0_sleep {
   mux {
    pins = "gpio127";
    function = "gpio";
   };

   config {
    pins = "gpio127";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s0_sd0_active: i2s0_sd0_active {
   mux {
    pins = "gpio127";
    function = "i2s0_data0";
   };

   config {
    pins = "gpio127";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 i2s0_sd1 {
  i2s0_sd1_sleep: i2s0_sd1_sleep {
   mux {
    pins = "gpio128";
    function = "gpio";
   };

   config {
    pins = "gpio128";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s0_sd1_active: i2s0_sd1_active {
   mux {
    pins = "gpio128";
    function = "i2s0_data1";
   };

   config {
    pins = "gpio128";
    drive-strength = <8>;
    bias-disable;
    output-high;
   };
  };
 };

 i2s1_sck {
  i2s1_sck_sleep: i2s1_sck_sleep {
   mux {
    pins = "gpio121";
    function = "gpio";
   };

   config {
    pins = "gpio121";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s1_sck_active: i2s1_sck_active {
   mux {
    pins = "gpio121";
    function = "i2s1_sck";
   };

   config {
    pins = "gpio121";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 i2s1_ws {
  i2s1_ws_sleep: i2s1_ws_sleep {
   mux {
    pins = "gpio123";
    function = "gpio";
   };

   config {
    pins = "gpio123";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s1_ws_active: i2s1_ws_active {
   mux {
    pins = "gpio123";
    function = "i2s1_ws";
   };

   config {
    pins = "gpio123";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 i2s1_sd0 {
  i2s1_sd0_sleep: i2s1_sd0_sleep {
   mux {
    pins = "gpio122";
    function = "gpio";
   };

   config {
    pins = "gpio122";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s1_sd0_active: i2s1_sd0_active {
   mux {
    pins = "gpio122";
    function = "i2s1_data0";
   };

   config {
    pins = "gpio122";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 i2s1_sd1 {
  i2s1_sd1_sleep: i2s1_sd1_sleep {
   mux {
    pins = "gpio124";
    function = "gpio";
   };

   config {
    pins = "gpio124";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };

  i2s1_sd1_active: i2s1_sd1_active {
   mux {
    pins = "gpio124";
    function = "i2s1_data1";
   };

   config {
    pins = "gpio124";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };


 wcd938x_reset_active: wcd938x_reset_active {
  mux {
   pins = "gpio108";
   function = "gpio";
  };

  config {
   pins = "gpio108";
   drive-strength = <16>;
   output-high;
  };
 };

 wcd938x_reset_sleep: wcd938x_reset_sleep {
  mux {
   pins = "gpio108";
   function = "gpio";
  };

  config {
   pins = "gpio108";
   drive-strength = <16>;
   bias-disable;
   output-low;
  };
 };

 pcie0 {
  pcie0_perst_default: pcie0_perst_default {
   mux {
    pins = "gpio94";
    function = "gpio";
   };

   config {
    pins = "gpio94";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  pcie0_clkreq_default: pcie0_clkreq_default {
   mux {
    pins = "gpio95";
    function = "pcie0_clk_req_n";
   };

   config {
    pins = "gpio95";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  pcie0_wake_default: pcie0_wake_default {
   mux {
    pins = "gpio96";
    function = "gpio";
   };

   config {
    pins = "gpio96";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  pcie0_clkreq_sleep: pcie0_clkreq_sleep {
   mux {
    pins = "gpio95";
    function = "gpio";
   };

   config {
    pins = "gpio95";
    drive-strength = <2>;
    bias-pull-up;
   };
  };
 };

 usb_phy_ps: usb_phy_ps {
  usb3phy_portselect_default: usb3phy_portselect_default {
   mux {
    pins = "gpio11";
    function = "usb_phy";
   };

   config {
    pins = "gpio11";
    bias-pull-down;
    drive-strength = <2>;
   };
  };

  usb3phy_portselect_gpio: usb3phy_portselect_gpio {
   mux {
    pins = "gpio11";
    function = "gpio";
   };

   config {
    pins = "gpio11";
    drive-strength = <2>;
    bias-pull-down;
    input-enable;
   };
  };
 };

 pcie1 {
  pcie1_perst_default: pcie1_perst_default {
   mux {
    pins = "gpio97";
    function = "gpio";
   };

   config {
    pins = "gpio97";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  pcie1_clkreq_default: pcie1_clkreq_default {
   mux {
    pins = "gpio98";
    function = "pcie1_clk_req_n";
   };

   config {
    pins = "gpio98";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  pcie1_wake_default: pcie1_wake_default {
   mux {
    pins = "gpio99";
    function = "gpio";
   };

   config {
    pins = "gpio99";
    drive-strength = <2>;
    bias-pull-up;
   };
  };

  pcie1_clkreq_sleep: pcie1_clkreq_sleep {
   mux {
    pins = "gpio98";
    function = "gpio";
   };

   config {
    pins = "gpio98";
    drive-strength = <2>;
    bias-pull-up;
   };
  };
 };

 pcie_ep {
  pcie_ep_clkreq_default: pcie_ep_clkreq_default {
   mux {
       pins = "gpio98";
       function = "pcie1_clk_req_n";
   };

   config {
    pins = "gpio98";
    drive-strength = <2>;
    bias-disable;
   };
  };

  pcie_ep_perst_default: pcie_ep_perst_default {
   mux {
    pins = "gpio97";
    function = "gpio";
   };

   config {
    pins = "gpio97";
    drive-strength = <2>;
    bias-pull-down;
   };
  };

  pcie_ep_wake_default: pcie_ep_wake_default {
   mux {
    pins = "gpio99";
    function = "gpio";
   };

   config {
    pins = "gpio99";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };


 pmx_ts_active {
  ts_active: ts_active {
   mux {
    pins = "gpio24", "gpio25";
    function = "gpio";
   };

   config {
    pins = "gpio24", "gpio25";
    drive-strength = <8>;
    bias-pull-up;
   };
  };
 };

 pmx_ts_reset_suspend {
  ts_reset_suspend: ts_reset_suspend {
   mux {
    pins = "gpio24";
    function = "gpio";
   };

   config {
    pins = "gpio24";
    drive-strength = <2>;
    bias-pull-down;
   };
  };
 };

 pmx_ts_int_suspend {
  ts_int_suspend: ts_int_suspend {
   mux {
    pins = "gpio25";
    function = "gpio";
   };

   config {
    pins = "gpio25";
    drive-strength = <2>;
    bias-pull-down;
   };
  };
 };

 pmx_ts_release {
  ts_release: ts_release {
   mux {
    pins = "gpio24", "gpio25";
    function = "gpio";
   };

   config {
    pins = "gpio24", "gpio25";
    drive-strength = <2>;
    bias-disable;
   };
  };
 };

 ap2mdm {
  ap2mdm_active: ap2mdm_active {
   mux {



    pins = "gpio29", "gpio30";
    function = "gpio";
   };

   config {
    pins = "gpio29", "gpio30";
    drive-strength = <16>;
    bias-disable;
   };
  };

  ap2mdm_sleep: ap2mdm_sleep {
   mux {



    pins = "gpio29", "gpio30";
    function = "gpio";
   };

   config {
    pins = "gpio29", "gpio30";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 mdm2ap {
  mdm2ap_active: mdm2ap_active {
   mux {



    pins = "gpio28", "gpio31";
    function = "gpio";
   };

   config {
    pins = "gpio28", "gpio31";
    drive-strength = <16>;
    bias-disable;
   };
  };

  mdm2ap_sleep: mdm2ap_sleep {
   mux {



    pins = "gpio28", "gpio31";
    function = "gpio";
   };

   config {
    pins = "gpio28", "gpio31";
    drive-strength = <8>;
    bias-disable;
   };
  };
 };

 ch101_rst: ch101_rst {
  mux {
   pins = "gpio127";
   function = "gpio";
  };

  config {
   pins = "gpio127";
   output-high;
   drive-strength = <2>;
  };
 };

 ch101_tmr_rst: ch101_tmr_rst {
  mux {
   pins = "gpio88";
   function = "gpio";
  };

  config {
   pins = "gpio88";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 ch101_0_irq: ch101_0_irq {
  mux {
   pins = "gpio18", "gpio129", "gpio17";
   function = "gpio";
  };

  config {
   pins = "gpio18", "gpio129", "gpio17";
   bias-no-pull;
   drive-strength = <2>;
  };
 };

 ch101_1_irq: ch101_1_irq {
  mux {
   pins = "gpio14", "gpio19", "gpio86";
   function = "gpio";
  };

  config {
   pins = "gpio14", "gpio19", "gpio86";
   bias-no-pull;
   drive-strength = <2>;
  };
 };
};
# 3663 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-kalama.dtsi" 1


&soc {
 kgsl_smmu: kgsl-smmu@3da0000 {
  compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
  reg = <0x3da0000 0x40000>,
   <0x3DE6000 0x40>;
  reg-names = "base", "tcu-base";
  #iommu-cells = <2>;
  qcom,use-3-lvl-tables;
  #global-interrupts = <1>;
  #size-cells = <1>;
  #address-cells = <1>;
  ranges;
  dma-coherent;

  qcom,regulator-names = "vdd";
  vdd-supply = <&gpu_cc_cx_gdsc>;

  clocks = <&gpucc 15>,
    <&gcc 32>,
    <&gcc 33>,
    <&gpucc 0>;
  clock-names =
   "gpu_cc_hlos1_vote_gpu_smmu",
   "gcc_gpu_memnoc_gfx",
   "gcc_gpu_snoc_dvm_gfx",
   "gpu_cc_ahb";

  qcom,actlr =

   <0x000 0x3ff 0x32B>;

  interrupts = <0 673 4>,
    <0 677 4>,
    <0 678 4>,
    <0 679 4>,
    <0 680 4>,
    <0 681 4>,
    <0 682 4>,
    <0 683 4>,
    <0 684 4>,
    <0 685 4>,
    <0 686 4>,
    <0 687 4>,
    <0 422 4>,
    <0 476 4>,
    <0 574 4>,
    <0 575 4>,
    <0 576 4>,
    <0 577 4>,
    <0 659 4>,
    <0 661 4>,
    <0 664 4>,
    <0 665 4>,
    <0 666 4>,
    <0 668 4>,
    <0 669 4>,
    <0 699 4>;

  gpu_qtb: gpu_qtb@3de8000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x3de8000 0x1000>,
    <0x3DEC000 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x0 0x400>;
   qcom,iova-width = <49>;
   interconnects = <&gem_noc 0 &mc_virt 512>;
   qcom,num-qtb-ports = <2>;
  };
 };

 apps_smmu: apps-smmu@15000000 {
  compatible = "qcom,qsmmu-v500";
  reg = <0x15000000 0x100000>,
   <0x151fe000 0x40>;
  reg-names = "base", "tcu-base";
  #iommu-cells = <2>;
  qcom,use-3-lvl-tables;
  qcom,handoff-smrs = <0x1c00 0x2>;
  #global-interrupts = <1>;
  #size-cells = <1>;
  #address-cells = <1>;
  ranges;
  dma-coherent;

  interrupts = <0 65 4>,
    <0 97 4>,
    <0 98 4>,
    <0 99 4>,
    <0 100 4>,
    <0 101 4>,
    <0 102 4>,
    <0 103 4>,
    <0 104 4>,
    <0 105 4>,
    <0 106 4>,
    <0 107 4>,
    <0 108 4>,
    <0 109 4>,
    <0 110 4>,
    <0 111 4>,
    <0 112 4>,
    <0 113 4>,
    <0 114 4>,
    <0 115 4>,
    <0 116 4>,
    <0 117 4>,
    <0 118 4>,
    <0 181 4>,
    <0 182 4>,
    <0 183 4>,
    <0 184 4>,
    <0 185 4>,
    <0 186 4>,
    <0 187 4>,
    <0 188 4>,
    <0 189 4>,
    <0 190 4>,
    <0 191 4>,
    <0 192 4>,
    <0 315 4>,
    <0 316 4>,
    <0 317 4>,
    <0 318 4>,
    <0 319 4>,
    <0 320 4>,
    <0 321 4>,
    <0 322 4>,
    <0 323 4>,
    <0 324 4>,
    <0 325 4>,
    <0 326 4>,
    <0 327 4>,
    <0 328 4>,
    <0 329 4>,
    <0 330 4>,
    <0 331 4>,
    <0 332 4>,
    <0 333 4>,
    <0 334 4>,
    <0 335 4>,
    <0 336 4>,
    <0 337 4>,
    <0 338 4>,
    <0 339 4>,
    <0 340 4>,
    <0 341 4>,
    <0 342 4>,
    <0 343 4>,
    <0 344 4>,
    <0 345 4>,
    <0 395 4>,
    <0 396 4>,
    <0 397 4>,
    <0 398 4>,
    <0 399 4>,
    <0 400 4>,
    <0 401 4>,
    <0 402 4>,
    <0 403 4>,
    <0 404 4>,
    <0 405 4>,
    <0 406 4>,
    <0 407 4>,
    <0 408 4>,
    <0 409 4>,
    <0 418 4>,
    <0 419 4>,
    <0 412 4>,
    <0 421 4>,
    <0 706 4>,
    <0 423 4>,
    <0 424 4>,
    <0 425 4>,
    <0 689 4>,
    <0 690 4>,
    <0 691 4>,
    <0 692 4>,
    <0 693 4>,
    <0 694 4>,
    <0 695 4>,
    <0 696 4>;


  qcom,actlr =

   <0x18a0 0x0000 0x00000103>,
   <0x18e0 0x0000 0x00000103>,


   <0x0800 0x0020 0x00000001>,
   <0x1800 0x00c0 0x00000001>,
   <0x1820 0x0000 0x00000001>,
   <0x1860 0x0000 0x00000001>,


   <0x0c01 0x0020 0x00000303>,
   <0x0c02 0x0020 0x00000303>,
   <0x0c03 0x0020 0x00000303>,
   <0x0c04 0x0020 0x00000303>,
   <0x0c05 0x0020 0x00000303>,
   <0x0c06 0x0020 0x00000303>,
   <0x0c07 0x0020 0x00000303>,
   <0x0c08 0x0020 0x00000303>,
   <0x0c09 0x0020 0x00000303>,
   <0x0c0c 0x0020 0x00000303>,
   <0x0c0d 0x0020 0x00000303>,
   <0x0c0e 0x0020 0x00000303>,
   <0x0c0f 0x0020 0x00000303>,
   <0x1961 0x0000 0x00000303>,
   <0x1962 0x0000 0x00000303>,
   <0x1963 0x0000 0x00000303>,
   <0x1964 0x0000 0x00000303>,
   <0x1965 0x0000 0x00000303>,
   <0x1966 0x0000 0x00000303>,
   <0x1967 0x0000 0x00000303>,
   <0x1968 0x0000 0x00000303>,
   <0x1969 0x0000 0x00000303>,
   <0x196c 0x0000 0x00000303>,
   <0x196d 0x0000 0x00000303>,
   <0x196e 0x0000 0x00000303>,
   <0x196f 0x0000 0x00000303>,
   <0x19c1 0x0010 0x00000303>,
   <0x19c2 0x0010 0x00000303>,
   <0x19c3 0x0010 0x00000303>,
   <0x19c4 0x0010 0x00000303>,
   <0x19c5 0x0010 0x00000303>,
   <0x19c6 0x0010 0x00000303>,
   <0x19c7 0x0010 0x00000303>,
   <0x19c8 0x0010 0x00000303>,
   <0x19c9 0x0010 0x00000303>,
   <0x19cc 0x0010 0x00000303>,
   <0x19cd 0x0010 0x00000303>,
   <0x19ce 0x0010 0x00000303>,
   <0x19cf 0x0010 0x00000303>,


   <0x1c00 0x0002 0x00000001>,
   <0x1c01 0x0000 0x00000001>,


   <0x1920 0x0000 0x00000103>,
   <0x1923 0x0000 0x00000103>,
   <0x1924 0x0000 0x00000103>,


   <0x1940 0x0000 0x00000103>,
   <0x1941 0x0004 0x00000103>,
   <0x1943 0x0000 0x00000103>,
   <0x1944 0x0000 0x00000103>,
   <0x1947 0x0000 0x00000103>;

  anoc_1_qtb: anoc_1_qtb@16f0000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x16f0000 0x1000>,
    <0x16e1100 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x0 0x400>;
   qcom,iova-width = <36>;
   interconnects = <&system_noc 9 &mc_virt 512>;
   qcom,num-qtb-ports = <1>;
  };

  anoc_2_qtb: anoc_2_qtb@171a000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x171a000 0x1000>,
    <0x16e1100 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x400 0x400>;
   qcom,iova-width = <36>;
   interconnects = <&system_noc 10 &mc_virt 512>;
   qcom,num-qtb-ports = <1>;
  };

  cam_hf_qtb: cam_hf_qtb@17d2000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x17d2000 0x1000>,
    <0x1783000 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x800 0x400>;
   qcom,iova-width = <36>;
   interconnects = <&mmss_noc 11 &mc_virt 512>;
   qcom,num-qtb-ports = <2>;
  };

  nsp_qtb: nsp_qtb@523000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x523000 0x1000>,
    <0x532000 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0xc00 0x400>;
   qcom,iova-width = <34>;
   interconnects = <&nsp_noc 42 &mc_virt 512>;
   qcom,num-qtb-ports = <2>;
  };

  lpass_qtb: lpass_qtb@503000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x503000 0x1000>,
    <0x511000 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x1000 0x400>;
   qcom,iova-width = <32>;
   interconnects = <&lpass_lpicx_noc 41 &mc_virt 512>;
   qcom,num-qtb-ports = <1>;
  };

  pcie_qtb: pcie_qtb@16cd000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x16cd000 0x1000>,
    <0x16C3000 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x1400 0x400>;
   qcom,iova-width = <36>;
   interconnects = <&pcie_noc 45 &mc_virt 512>;
   qcom,num-qtb-ports = <1>;
   qcom,opt-out-tbu-halting;
  };

  sf_qtb: sf_qtb@17d1000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x17d1000 0x1000>,
    <0x1783000 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x1800 0x400>;
   qcom,iova-width = <36>;
   interconnects = <&mmss_noc 29 &mc_virt 512>;
   qcom,num-qtb-ports = <2>;
  };

  mdp_hf_qtb: mdp_hf_qtb@17d0000 {
   compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
   reg = <0x17d0000 0x1000>,
    <0x1783000 0x1000>;
   reg-names = "base", "debugchain-base";
   qcom,stream-id-range = <0x1c00 0x400>;
   qcom,iova-width = <32>;
   interconnects = <&mmss_noc 20 &mc_virt 512>;
   qcom,num-qtb-ports = <2>;
  };
 };

 dma_dev {
  compatible = "qcom,iommu-dma";
  memory-region = <&system_cma>;
 };

 iommu_test_device {
  compatible = "qcom,iommu-debug-test";

  usecase0_apps {
   compatible = "qcom,iommu-debug-usecase";
   iommus = <&apps_smmu 0x400 0x0>;
  };

  usecase1_apps_fastmap {
   compatible = "qcom,iommu-debug-usecase";
   iommus = <&apps_smmu 0x400 0x0>;
   qcom,iommu-dma = "fastmap";
  };

  usecase2_apps_atomic {
   compatible = "qcom,iommu-debug-usecase";
   iommus = <&apps_smmu 0x400 0x0>;
   qcom,iommu-dma = "atomic";
  };

  usecase3_apps_dma {
   compatible = "qcom,iommu-debug-usecase";
   iommus = <&apps_smmu 0x400 0x0>;
   dma-coherent;
  };

  usecase4_apps_secure {
   compatible = "qcom,iommu-debug-usecase";
   iommus = <&apps_smmu 0x400 0x0>;
   qcom,iommu-vmid = <0xa>;
  };

  usecase5_kgsl {
   compatible = "qcom,iommu-debug-usecase";
   iommus = <&kgsl_smmu 0x7 0x0>;
  };

  usecase6_kgsl_dma {
   compatible = "qcom,iommu-debug-usecase";
   iommus = <&kgsl_smmu 0x7 0x0>;
   dma-coherent;
  };
 };
};
# 3664 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-coresight.dtsi" 1
&soc {
 audio_etm0 {
  compatible = "qcom,coresight-remote-etm";

  coresight-name = "coresight-audio-etm0";
  qcom,inst-id = <5>;
  atid = <40 41>;

  out-ports {
   port {
    audio_etm0_out_funnel_lpass_lpi: endpoint {
     remote-endpoint =
     <&funnel_lpass_lpi_in_audio_etm0>;
    };
   };
  };
 };

 tpdm_lpass_lpi: tpdm_lpass_lpi {
  compatible = "qcom,coresight-dummy";
  coresight-name = "coresight-tpdm-lpass-lpi";
  qcom,dummy-source;

  atid = <26>;

  out-ports {
   port {
    tpdm_lpass_lpi_1_out_funnel_lpass_lpi: endpoint {
     remote-endpoint =
     <&funnel_lpass_lpi_in_tpdm_lpass_lpi_1>;
    };
   };
  };
 };

 lpass_stm: lpass_stm {
  compatible = "qcom,coresight-dummy";
  coresight-name = "coresight-lpass-stm";
  qcom,dummy-source;

  atid = <25>;

  out-ports {
   port {
    lpass_stm_out_funnel_lpass_lpi_1: endpoint {
     remote-endpoint =
     <&funnel_lpass_lpi_1_in_lpass_stm>;
    };
   };
  };
 };

 tpdm_swao_prio_0: tpdm@10b09000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10b09000 0x1000>;
  reg-names = "tpdm-base";

  atid = <71>;
  coresight-name = "coresight-tpdm-swao-prio-0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_swao_prio_0_out_tpda_aoss_0: endpoint {
     remote-endpoint =
     <&tpda_aoss_0_in_tpdm_swao_prio_0>;
    };
   };
  };
 };

 tpdm_swao_prio_1: tpdm@10b0a000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10b0a000 0x1000>;
  reg-names = "tpdm-base";

  atid = <71>;
  coresight-name = "coresight-tpdm-swao-prio-1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_swao_prio_1_out_tpda_aoss_1: endpoint {
     remote-endpoint =
     <&tpda_aoss_1_in_tpdm_swao_prio_1>;
    };
   };
  };
 };

 tpdm_swao_prio_2: tpdm@10b0b000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10b0b000 0x1000>;
  reg-names = "tpdm-base";

  atid = <71>;
  coresight-name = "coresight-tpdm-swao-prio-2";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_swao_prio_2_out_tpda_aoss_2: endpoint {
     remote-endpoint =
     <&tpda_aoss_2_in_tpdm_swao_prio_2>;
    };
   };
  };
 };

 tpdm_swao_prio_3: tpdm@10b0c000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10b0c000 0x1000>;
  reg-names = "tpdm-base";

  atid = <71>;
  coresight-name = "coresight-tpdm-swao-prio-3";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_swao_prio_3_out_tpda_aoss_3: endpoint {
     remote-endpoint =
     <&tpda_aoss_3_in_tpdm_swao_prio_3>;
    };
   };
  };
 };

 tpdm_lpass: tpdm@10844000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10844000 0x1000>;
  reg-names = "tpdm-base";

  coresight-name = "coresight-tpdm-lpass";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  atid = <78>;
  out-ports {
   port {
    tpdm_lpass_out_funnel_lpass: endpoint {
     remote-endpoint =
     <&funnel_lpass_in_tpdm_lpass>;
    };
   };
  };
 };

 tpdm_ddr_ch02: tpdm@10d20000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d20000 0x1000>;
  reg-names = "tpdm-base";

  coresight-name = "coresight-tpdm-ddr-ch02";

  atid = <78>;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_ddr_ch02_out_funnel_ddr_ch02: endpoint {
     remote-endpoint =
     <&funnel_ddr_ch02_in_tpdm_ddr_ch02>;
    };
   };
  };
 };

 tpdm_ddr_ch13: tpdm@10d30000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d30000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-ddr-ch13";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_ddr_ch13_out_funnel_ddr_ch13: endpoint {
     remote-endpoint =
     <&funnel_ddr_ch13_in_tpdm_ddr_ch13>;
    };
   };
  };
 };

 tpdm_ddr: tpdm@10d00000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d00000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-ddr";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_ddr_dl0_0_out_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_in_tpdm_ddr_dl0_0>;
    };
   };
  };
 };

 tpdm_shrm: tpdm@10d01000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d01000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  status = "disabled";
  coresight-name = "coresight-tpdm-shrm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_ddr_dl0_1_out_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_in_tpdm_ddr_dl0_1>;
    };
   };
  };
 };

 tpdm_video: tpdm@10830000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10830000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-video";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_video_out_funnel_video: endpoint {
     remote-endpoint =
     <&funnel_video_in_tpdm_video>;
    };
   };
  };
 };

 tpdm_mdss: tpdm@10c60000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c60000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-mdss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_mdss_out_funnel_multimedia: endpoint {
     remote-endpoint =
     <&funnel_multimedia_in_tpdm_mdss>;
    };
   };
  };
 };

 tpdm_mm: tpdm@10c08000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c08000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-mm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_dlmm_out_funnel_multimedia: endpoint {
     remote-endpoint =
     <&funnel_multimedia_in_tpdm_dlmm>;
    };
   };
  };
 };

 tpdm_rdpm: tpdm@10c38000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c38000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-rdpm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_dlwt0_out_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_in_tpdm_dlwt0>;
    };
   };
  };
 };

 tpdm_rdpm_mx: tpdm@10c39000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c39000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-rdpm-mx";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_dlwt1_out_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_in_tpdm_dlwt1>;
    };
   };
  };
 };

 tpdm_turing: tpdm@10980000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10980000 0x1000>;
  reg-names = "tpdm-base";

  coresight-name = "coresight-tpdm-turing";

  atid = <78>;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_turing_out_funnel_turing: endpoint {
     remote-endpoint =
     <&funnel_turing_in_tpdm_turing>;
    };
   };
  };
 };

 tpdm_turing_llm: tpdm_turing_llm {
  compatible = "qcom,coresight-dummy";
  coresight-name = "coresight-tpdm-turing-llm";
  qcom,dummy-source;

  atid = <78>;

  out-ports {
   port {
    tpdm_turing_llm_out_funnel_turing: endpoint {
     remote-endpoint =
     <&funnel_turing_in_tpdm_turing_llm>;
    };
   };
  };
 };

 tpdm_gpu: tpdm@10900000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10900000 0x1000>;
  reg-names = "tpdm-base";

  coresight-name = "coresight-tpdm-gpu";
  atid = <78>;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_gpu_out_funnel_gfx_dl: endpoint {
     remote-endpoint =
     <&funnel_gfx_dl_in_tpdm_gpu>;
    };
   };
  };
 };

 tpdm_prng: tpdm@10841000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10841000 0x1000>;
  reg-names = "tpdm-base";

  coresight-name = "coresight-tpdm-prng";

  atid = <78>;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_prng_out_tpda_dl_center_19: endpoint {
     remote-endpoint =
     <&tpda_dl_center_19_in_tpdm_prng>;
    };
   };
  };
 };

 tpdm_qm: tpdm@109d0000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x109d0000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-qm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_qm_out_tpda_dl_center_20: endpoint {
     remote-endpoint =
     <&tpda_dl_center_20_in_tpdm_qm>;
    };
   };
  };
 };

 tpdm_gcc: tpdm@1082c000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x1082c000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-gcc";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_gcc_out_tpda_dl_center_21: endpoint {
     remote-endpoint =
     <&tpda_dl_center_21_in_tpdm_gcc>;
    };
   };
  };
 };

 tpdm_vsense: tpdm@10840000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10840000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-vsense";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_vsense_out_tpda_dl_center_22: endpoint {
     remote-endpoint =
     <&tpda_dl_center_22_in_tpdm_vsense>;
    };
   };
  };
 };

 tpdm_ipa: tpdm@10c22000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c22000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-ipa";
  status = "disabled";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_ipa_out_tpda_dl_center_23: endpoint {
     remote-endpoint =
     <&tpda_dl_center_23_in_tpdm_ipa>;
    };
   };
  };
 };

 tpdm_dlct: tpdm@10c28000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c28000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-dlct";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_dlct_out_tpda_dl_center_26: endpoint {
     remote-endpoint =
     <&tpda_dl_center_26_in_tpdm_dlct>;
    };
   };
  };
 };

 tpdm_ipcc: tpdm@10c29000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c29000 0x1000>;
  reg-names = "tpdm-base";

  atid = <78>;
  coresight-name = "coresight-tpdm-ipcc";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_ipcc_out_tpda_dl_center_27: endpoint {
     remote-endpoint =
     <&tpda_dl_center_27_in_tpdm_ipcc>;
    };
   };
  };
 };

 tpdm_swao_1: tpdm@10b0d000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10b0d000 0x1000>;
  reg-names = "tpdm-base";

  atid = <71>;
  coresight-name = "coresight-tpdm-swao-1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_swao_out_tpda_aoss_4: endpoint {
     remote-endpoint =
     <&tpda_aoss_4_in_tpdm_swao>;
    };
   };
  };
 };

 snoc: snoc {
  compatible = "qcom,coresight-dummy";
  coresight-name = "coresight-snoc";
  qcom,dummy-source;

  atid = <125>;
  out-ports {
   port {
    snoc_out_funnel_in0: endpoint {
     remote-endpoint =
     <&funnel_in0_in_snoc>;
    };
   };
  };
 };

 tpdm_spdm: tpdm@1000f000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x1000f000 0x1000>;
  reg-names = "tpdm-base";

  atid = <65>;
  coresight-name = "coresight-tpdm-spdm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_spdm_out_tpda_qdss_1: endpoint {
     remote-endpoint =
     <&tpda_qdss_1_in_tpdm_spdm>;
    };
   };
  };
 };

 stm: stm@10002000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb962>;
  reg = <0x10002000 0x1000>,
   <0x16280000 0x180000>;
  reg-names = "stm-base", "stm-stimulus-base";

  atid = <16>;
  coresight-name = "coresight-stm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    stm_out_funnel_in0: endpoint {
     remote-endpoint =
     <&funnel_in0_in_stm>;
    };
   };
  };
 };

 tpdm_dcc: tpdm@10003000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10003000 0x1000>;
  reg-names = "tpdm-base";

  atid = <65>;
  coresight-name = "coresight-tpdm-dcc";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
  qcom,hw-enable-check;

  out-ports {
   port {
    tpdm_dcc_out_tpda_qdss_0: endpoint {
     remote-endpoint =
     <&tpda_qdss_0_in_tpdm_dcc>;
    };
   };
  };
 };


 tpdm_ufs: tpdm@10c23000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c23000 0x1000>;
  reg-names = "tpdm-base";

  atid = <75>;
  coresight-name = "coresight-tpdm-ufs";
  status = "disabled";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_ufs_out_tpda_dl_south: endpoint {
     remote-endpoint =
     <&tpda_dl_south_in_tpdm_ufs>;
    };
   };
  };
 };

 turing_etm0: turing_etm0 {
  compatible = "qcom,coresight-remote-etm";

  coresight-name = "coresight-turing-etm0";
  qcom,inst-id = <13>;

  atid = <38 39>;

  out-ports {
   port {
    turing_etm0_out_funnel_turing_dup: endpoint {
     remote-endpoint =
      <&funnel_turing_dup_in_turing_etm0>;
    };
   };
  };
 };

 tpdm_spss: tpdm@10880000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10880000 0x1000>;
  reg-names = "tpdm-base";

  atid = <70>;
  coresight-name = "coresight-tpdm-spss";
  status = "disabled";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_spss_out_tpda_spss: endpoint {
     remote-endpoint =
     <&tpda_spss_in_tpdm_spss>;
    };
   };
  };
 };

 tpda_spss: tpda@10882000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;
  reg = <0x10882000 0x1000>;
  reg-names = "tpda-base";

  coresight-name = "coresight-tpda-spss";
  status = "disabled";

  qcom,tpda-atid = <70>;
  qcom,cmb-elem-size = <0 32>;
  qcom,dsb-elem-size = <0 32>;

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpda_spss_out_funnel_spss: endpoint {
     remote-endpoint =
     <&funnel_spss_in_tpda_spss>;
    };
   };
  };

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    tpda_spss_in_tpdm_spss: endpoint {
     remote-endpoint =
     <&tpdm_spss_out_tpda_spss>;
    };
   };

  };
 };

 tpdm_dl_south: tpdm@109c0000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x109c0000 0x1000>;
  reg-names = "tpdm-base";

  atid = <75>;
  coresight-name = "coresight-tpdm-dl-south";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_dl_south_out_tpda_dl_south_2: endpoint {
     remote-endpoint =
     <&tpda_dl_south_2_in_tpdm_dl_south>;
    };
   };
  };
 };

 tpdm_dl_north: tpdm@10ac0000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10ac0000 0x1000>;
  reg-names = "tpdm-base";

  atid = <97>;
  coresight-name = "coresight-tpdm-dl-north";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_dl_north_out_tpda_dl_north_2: endpoint {
     remote-endpoint =
     <&tpda_dl_north_2_in_tpdm_dl_north>;
    };
   };
  };
 };

 tpdm_llm_silver: tpdm@138a0000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x138a0000 0x1000>;
  reg-names = "tpdm-base";

  atid = <66>;
  coresight-name = "coresight-tpdm-llm-silver";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_llm_silver_out_tpda_apss_0: endpoint {
     remote-endpoint =
     <&tpda_apss_0_in_tpdm_llm_silver>;
    };
   };
  };
 };

 tpdm_llm_gold: tpdm@138b0000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x138b0000 0x1000>;
  reg-names = "tpdm-base";

  atid = <66>;
  coresight-name = "coresight-tpdm-llm-gold";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_llm_gold_out_tpda_apss_1: endpoint {
     remote-endpoint =
     <&tpda_apss_1_in_tpdm_llm_gold>;
    };
   };
  };
 };

 tpdm_apss_llm: tpdm@138c0000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x138c0000 0x1000>;
  reg-names = "tpdm-base";

  atid = <66>;
  coresight-name = "coresight-tpdm-apss-llm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_apss_llm_out_tpda_apss_2: endpoint {
     remote-endpoint =
     <&tpda_apss_2_in_tpdm_apss_llm>;
    };
   };
  };
 };

 tpdm_actpm: tpdm@13860000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x13860000 0x1000>;
  reg-names = "tpdm-base";

  atid = <66>;
  coresight-name = "coresight-tpdm-actpm";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_apss0_out_tpda_apss_3: endpoint {
     remote-endpoint =
     <&tpda_apss_3_in_tpdm_apss0>;
    };
   };
  };
 };

 tpdm_apss: tpdm@13861000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x13861000 0x1000>;
  reg-names = "tpdm-base";

  atid = <66>;
  coresight-name = "coresight-tpdm-apss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_apps1_out_tpda_apss_4: endpoint {
     remote-endpoint =
     <&tpda_apss_4_in_tpdm_apps1>;
    };
   };
  };
 };

 tpdm_modem_0: tpdm@10800000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10800000 0x1000>;
  reg-names = "tpdm-base";

  atid = <67>;
  coresight-name = "coresight-tpdm-modem-0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_modem_0_out_tpda_modem_0: endpoint {
     remote-endpoint =
     <&tpda_modem_0_in_tpdm_modem_0>;
    };
   };
  };
 };

 tpdm_modem_1: tpdm@10801000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10801000 0x1000>;
  reg-names = "tpdm-base";

  status = "disabled";
  atid = <67>;
  coresight-name = "coresight-tpdm-modem-1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_modem_1_out_tpda_modem_1: endpoint {
     remote-endpoint =
     <&tpda_modem_1_in_tpdm_modem_1>;
    };
   };
  };
 };

 modem_etm0 {
  compatible = "qcom,coresight-remote-etm";

  coresight-name = "coresight-modem-etm0";
  qcom,inst-id = <2>;

  atid = <36 37>;
  out-ports {
   port {
    modem_etm0_out_funnel_modem_q6_dup: endpoint {
     remote-endpoint =
      <&funnel_modem_q6_dup_in_modem_etm0>;
    };
   };
  };
 };

 modem2_etm0 {
  compatible = "qcom,coresight-remote-etm";

  coresight-name = "coresight-modem2-etm0";
  qcom,inst-id = <11>;

  atid = <39>;
  out-ports {
   port {
    modem2_etm0_out_funnel_modem: endpoint {
     remote-endpoint =
      <&funnel_modem_in_modem2_etm0>;
    };
   };
  };
 };

 modem_diag: modem_diag {
  compatible = "qcom,coresight-dummy";
  coresight-name = "coresight-modem-diag";
  qcom,dummy-source;

  atid = <50>;
  out-ports {
   port {
    modem_diag_out_funnel_modem_q6: endpoint {
     remote-endpoint =
     <&funnel_modem_q6_in_modem_diag>;
    };
   };
  };
 };

 tpdm_sdcc2: tpdm@10c20000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c20000 0x1000>;
  reg-names = "tpdm-base";

  status = "disabled";
  atid = <97>;
  coresight-name = "coresight-tpdm-sdcc-2";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_sdcc2_out_tpda_dl_north_1: endpoint {
     remote-endpoint =
     <&tpda_dl_north_1_in_tpdm_sdcc2>;
    };
   };
  };
 };

 tpdm_sdcc4: tpdm@10c21000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10c21000 0x1000>;
  reg-names = "tpdm-base";

  status = "disabled";
  atid = <75>;
  coresight-name = "coresight-tpdm-sdcc-4";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_sdcc4_out_tpda_dl_south_1: endpoint {
     remote-endpoint =
     <&tpda_dl_south_1_in_tpdm_sdcc4>;
    };
   };
  };
 };

 tpdm_tmess_prng: tpdm@10cc9000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10cc9000 0x1000>;
  reg-names = "tpdm-base";

  atid = <85>;
  coresight-name = "coresight-tpdm-tmess-prng";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_tmess_prng_out_tpda_tmess_0: endpoint {
     remote-endpoint =
     <&tpda_tmess_0_in_tpdm_tmess_prng>;
    };
   };
  };
 };

 tpdm_tmess_0: tpdm@10cc0000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10cc0000 0x1000>;
  reg-names = "tpdm-base";

  atid = <85>;
  coresight-name = "coresight-tpdm-tmess-0";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_tmess0_out_tpda_tmess: endpoint {
     remote-endpoint =
     <&tpda_tmess_in_tpdm_tmess0>;
    };
   };
  };
 };

 tpdm_tmess_1: tpdm@10cc1000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10cc1000 0x1000>;
  reg-names = "tpdm-base";

  atid = <85>;
  coresight-name = "coresight-tpdm-tmess-1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
  qcom,hw-enable-check;

  out-ports {
   port {
    tpdm_tmess1_out_tpda_tmess: endpoint {
     remote-endpoint =
     <&tpda_tmess_in_tpdm_tmess1>;
    };
   };
  };
 };

 tpdm_lpicc: tpdm_lpicc {
  compatible = "qcom,coresight-dummy";
  coresight-name = "coresight-tpdm-lpicc";
  qcom,dummy-source;

  atid = <27>;

  out-ports {
   port {
    tpdm_lpicc_out_funnel_ddr_lpi: endpoint {
     remote-endpoint =
     <&funnel_ddr_lpi_in_tpdm_lpicc>;
    };
   };
  };
 };

 tpdm_llcc_0: tpdm@10d40000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d40000 0x1000>;
  reg-names = "tpdm-base";

  atid = <99>;
  coresight-name = "coresight-tpdm-llcc-0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_llcc0_out_tpda_ddr_llcc: endpoint {
     remote-endpoint =
     <&tpda_ddr_llcc_in_tpdm_llcc0>;
    };
   };
  };
 };

 tpdm_llcc_1: tpdm@10d41000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d41000 0x1000>;
  reg-names = "tpdm-base";

  atid = <99>;
  coresight-name = "coresight-tpdm-llcc-1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_llcc1_out_tpda_ddr_llcc: endpoint {
     remote-endpoint =
     <&tpda_ddr_llcc_in_tpdm_llcc1>;
    };
   };
  };
 };

 tpdm_llcc_2: tpdm@10d42000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d42000 0x1000>;
  reg-names = "tpdm-base";

  atid = <99>;
  coresight-name = "coresight-tpdm-llcc-2";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_llcc2_out_tpda_ddr_llcc: endpoint {
     remote-endpoint =
     <&tpda_ddr_llcc_in_tpdm_llcc2>;
    };
   };
  };
 };

 tpdm_llcc_3: tpdm@10d43000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb968>;
  reg = <0x10d43000 0x1000>;
  reg-names = "tpdm-base";

  atid = <99>;
  coresight-name = "coresight-tpdm-llcc-3";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    tpdm_llcc3_out_tpda_ddr_llcc: endpoint {
     remote-endpoint =
     <&tpda_ddr_llcc_in_tpdm_llcc3>;
    };
   };
  };
 };

 tpda_ddr_llcc: tpda@10d09000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x10d09000 0x1000>;
  reg-names = "tpda-base";

  qcom,tpda-atid = <99>;

  qcom,cmb-elem-size = <0 32>,
        <1 32>,
        <2 32>,
        <3 32>;

  coresight-name = "coresight-tpda-ddr-llcc";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    tpda_ddr_llcc_in_tpdm_llcc0: endpoint {
     remote-endpoint =
     <&tpdm_llcc0_out_tpda_ddr_llcc>;
    };
   };

   port@1 {
    reg = <1>;
    tpda_ddr_llcc_in_tpdm_llcc1: endpoint {
     remote-endpoint =
     <&tpdm_llcc1_out_tpda_ddr_llcc>;
    };
   };

   port@2 {
    reg = <2>;
    tpda_ddr_llcc_in_tpdm_llcc2: endpoint {
     remote-endpoint =
     <&tpdm_llcc2_out_tpda_ddr_llcc>;
    };
   };

   port@3 {
    reg = <3>;
    tpda_ddr_llcc_in_tpdm_llcc3: endpoint {
     remote-endpoint =
     <&tpdm_llcc3_out_tpda_ddr_llcc>;
    };
   };
  };

  out-ports {
   port {
    tpda_ddr_llcc_out_funnel_ddr_dl1: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl1_in_tpda_ddr_llcc>;
    };
   };
  };
 };

 funnel_ddr_lpi: funnel@10b23000 {
  compatible = "arm,coresight-static-funnel";
  coresight-name = "coresight-funnel-ddr-lpi";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_ddr_lpi_in_tpdm_lpicc: endpoint {
     remote-endpoint =
     <&tpdm_lpicc_out_funnel_ddr_lpi>;
    };
   };
  };

  out-ports {
   port {
    funnel_ddr_lpi_out_funnel_aoss: endpoint {
     remote-endpoint =
     <&funnel_aoss_in_funnel_ddr_lpi>;
    };
   };
  };
 };

 funnel_lpass_lpi_1: funnel@10b50000 {
  compatible = "arm,coresight-static-funnel";
  coresight-name = "coresight-funnel-lpass_lpi_1";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_lpass_lpi_1_in_lpass_stm: endpoint {
     remote-endpoint =
     <&lpass_stm_out_funnel_lpass_lpi_1>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_lpass_lpi_in_tpdm_lpass_lpi_1: endpoint {
     remote-endpoint =
     <&tpdm_lpass_lpi_1_out_funnel_lpass_lpi>;
    };
   };

  };

  out-ports {
   port {
    funnel_lpass_lpi_1_out_funnel_lpass_lpi_0: endpoint {
     remote-endpoint =
     <&funnel_lpass_lpi_0_in_funnel_lpass_lpi_1>;
    };
   };

  };
 };

 funnel_lpass_lpi_0: funnel@10b44000 {
  compatible = "arm,coresight-static-funnel";
  coresight-name = "coresight-funnel-lpass_lpi_0";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_lpass_lpi_in_audio_etm0: endpoint {
     remote-endpoint =
     <&audio_etm0_out_funnel_lpass_lpi>;
    };
   };

   port@7 {
    reg = <7>;
    funnel_lpass_lpi_0_in_funnel_lpass_lpi_1: endpoint {
     remote-endpoint =
     <&funnel_lpass_lpi_1_out_funnel_lpass_lpi_0>;
    };
   };

  };

  out-ports {
   port {
    funnel_lpass_lpi_out_funnel_aoss: endpoint {
     remote-endpoint =
     <&funnel_aoss_in_funnel_lpass_lpi>;
    };
   };

  };
 };

 funnel_gfx: funnel@10963000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10963000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-gfx";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  out-ports {
   port {
    funnel_gfx_out_funnel_gfx_dl: endpoint {
    remote-endpoint =
     <&funnel_gfx_dl_in_funnel_gfx>;
    };
   };
  };
 };

 funnel_gfx_dl: funnel@10902000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10902000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-gfx_dl";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_gfx_dl_in_tpdm_gpu: endpoint {
     remote-endpoint =
     <&tpdm_gpu_out_funnel_gfx_dl>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_gfx_dl_in_funnel_gfx: endpoint {
     remote-endpoint =
     <&funnel_gfx_out_funnel_gfx_dl>;
    };
   };
  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;
   port@0 {
    reg = <0>;
    funnel_gfx_dl_out_tpda_dl_center_17: endpoint {
     remote-endpoint =
     <&tpda_dl_center_17_in_funnel_gfx_dl>;
    source = <&tpdm_gpu>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_gfx_dl_out_funnel_dl_center: endpoint {
     remote-endpoint =
     <&funnel_dl_center_in_funnel_gfx_dl>;
    };
   };
  };
 };

 funnel_video: funnel@10832000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10832000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-video";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    funnel_video_in_tpdm_video: endpoint {
     remote-endpoint =
     <&tpdm_video_out_funnel_video>;
    };
   };

  };

  out-ports {
   port {
    funnel_video_out_funnel_multimedia: endpoint {
     remote-endpoint =
     <&funnel_multimedia_in_funnel_video>;
    };
   };

  };
 };

 funnel_multimedia: funnel@10c0a000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10c0a000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-multimedia";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_multimedia_in_funnel_video: endpoint {
     remote-endpoint =
     <&funnel_video_out_funnel_multimedia>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_multimedia_in_tpdm_mdss: endpoint {
     remote-endpoint =
     <&tpdm_mdss_out_funnel_multimedia>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_multimedia_in_tpdm_dlmm: endpoint {
     remote-endpoint =
     <&tpdm_dlmm_out_funnel_multimedia>;
    };
   };

  };

  out-ports {
   port {
    funnel_multimedia_out_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_in_funnel_multimedia>;
    };
   };

  };
 };

 funnel_lpass: funnel@10846000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10846000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-lpass";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    funnel_lpass_in_tpdm_lpass: endpoint {
     remote-endpoint =
     <&tpdm_lpass_out_funnel_lpass>;
    };
   };

  };

  out-ports {
   port {
    funnel_lpass_out_tpda_dl_center_4: endpoint {
     remote-endpoint =
     <&tpda_dl_center_4_in_funnel_lpass>;
    };
   };

  };
 };

 funnel_ddr_ch02: funnel@10d22000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10d22000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-ddr_ch02";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    funnel_ddr_ch02_in_tpdm_ddr_ch02: endpoint {
     remote-endpoint =
     <&tpdm_ddr_ch02_out_funnel_ddr_ch02>;
    };
   };

  };

  out-ports {
   port {
    funnel_ddr_ch02_out_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_in_funnel_ddr_ch02>;
    };
   };

  };
 };

 funnel_ddr_ch13: funnel@10d32000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10d32000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-ddr_ch13";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    funnel_ddr_ch13_in_tpdm_ddr_ch13: endpoint {
     remote-endpoint =
     <&tpdm_ddr_ch13_out_funnel_ddr_ch13>;
    };
   };

  };

  out-ports {
   port {
    funnel_ddr_ch13_out_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_in_funnel_ddr_ch13>;
    };
   };

  };
 };

 gladiator: gladiator {
  compatible = "qcom,coresight-dummy";
  coresight-name = "coresight-gladiator";
  qcom,dummy-source;

  atid = <96>;

  out-ports {
   port {
    gladiator_out_funnel_ddr_dl1: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl1_in_gladiator>;
    };
   };
  };
 };

 funnel_ddr_dl1: funnel@10d0a000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10d0a000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-ddr_dl1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_ddr_dl1_in_tpda_ddr_llcc: endpoint {
     remote-endpoint =
     <&tpda_ddr_llcc_out_funnel_ddr_dl1>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_ddr_dl1_in_gladiator: endpoint {
     remote-endpoint =
     <&gladiator_out_funnel_ddr_dl1>;
    };
   };
  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_ddr_dl1_out_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_in_funnel_ddr_dl1>;
    };
   };
  };

 };

 funnel_ddr_dl0: funnel@10d03000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10d03000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-ddr_dl0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@1 {
    reg = <1>;
    funnel_ddr_dl0_in_funnel_ddr_ch13: endpoint {
     remote-endpoint =
     <&funnel_ddr_ch13_out_funnel_ddr_dl0>;
    };
   };

   port@0 {
    reg = <0>;
    funnel_ddr_dl0_in_funnel_ddr_ch02: endpoint {
     remote-endpoint =
     <&funnel_ddr_ch02_out_funnel_ddr_dl0>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_ddr_dl0_in_tpdm_ddr_dl0_1: endpoint {
     remote-endpoint =
     <&tpdm_ddr_dl0_1_out_funnel_ddr_dl0>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_ddr_dl0_in_tpdm_ddr_dl0_0: endpoint {
     remote-endpoint =
     <&tpdm_ddr_dl0_0_out_funnel_ddr_dl0>;
    };
   };

   port@4 {
    reg = <4>;
    funnel_ddr_dl0_in_funnel_ddr_dl1: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl1_out_funnel_ddr_dl0>;
    };
   };
  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_ddr_dl0_out_tpda_dl_center_5: endpoint {
     remote-endpoint =
     <&tpda_dl_center_5_in_funnel_ddr_dl0>;
     source = <&tpdm_ddr_ch02>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_ddr_dl0_out_tpda_dl_center_6: endpoint {
     remote-endpoint =
     <&tpda_dl_center_6_in_funnel_ddr_dl0>;
     source = <&tpdm_ddr_ch13>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_ddr_dl0_out_tpda_dl_center_7: endpoint {
     remote-endpoint =
     <&tpda_dl_center_7_in_funnel_ddr_dl0>;
     source = <&tpdm_ddr>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_ddr_dl0_out_tpda_dl_center_8: endpoint {
     remote-endpoint =
     <&tpda_dl_center_8_in_funnel_ddr_dl0>;
     source = <&tpdm_shrm>;
    };
   };

   port@4 {
    reg = <4>;
    funnel_ddr_dl0_out_funnel_dl_center: endpoint {
     remote-endpoint =
     <&funnel_dl_center_in_funnel_ddr_dl0>;
    };
   };
  };
 };

 funnel_turing_dup: funnel@10984000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10984000 0x1000>,
   <0x10983000 0x1000>;
  reg-names = "funnel-base-dummy", "funnel-base-real";

  coresight-name = "coresight-funnel-turing_dup";

  qcom,duplicate-funnel;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;
   port@4 {
    reg = <4>;
    funnel_turing_dup_in_turing_etm0: endpoint {
     remote-endpoint =
     <&turing_etm0_out_funnel_turing_dup>;
    };
   };

  };

  out-ports {
   port {
    funnel_turing_dup_out_funnel_turing: endpoint {
     remote-endpoint =
     <&funnel_turing_in_funnel_turing_dup>;
    };
   };

  };
 };

 funnel_turing: funnel@10983000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10983000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-turing";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_turing_in_tpdm_turing: endpoint {
     remote-endpoint =
     <&tpdm_turing_out_funnel_turing>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_turing_in_tpdm_turing_llm: endpoint {
     remote-endpoint =
     <&tpdm_turing_llm_out_funnel_turing>;
    };
   };

   port@5 {
    reg = <5>;
    funnel_turing_in_funnel_turing_dup: endpoint {
     remote-endpoint =
     <&funnel_turing_dup_out_funnel_turing>;
    };
   };

  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_turing_out_tpda_dl_center_15: endpoint {
     remote-endpoint =
     <&tpda_dl_center_15_in_funnel_turing>;
     source = <&tpdm_turing>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_turing_out_tpda_dl_center_16: endpoint {
     remote-endpoint =
     <&tpda_dl_center_16_in_funnel_turing>;
     source = <&tpdm_turing_llm>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_turing_out_funnel_dl_center: endpoint {
     remote-endpoint =
     <&funnel_dl_center_in_funnel_turing>;
    };
   };

  };
 };

 funnel_spss: funnel@10883000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10883000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-spss";
  status = "disabled";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    funnel_spss_in_tpda_spss: endpoint {
     remote-endpoint =
     <&tpda_spss_out_funnel_spss>;
    };
   };

  };

  out-ports {
   port {
    funnel_spss_out_funnel_dl_north: endpoint {
     remote-endpoint =
     <&funnel_dl_north_in_funnel_spss>;
    };
   };

  };
 };

 funnel_dl_west: funnel@10c3a000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10c3a000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-dl_west";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_dl_west_in_funnel_multimedia: endpoint {
     remote-endpoint =
     <&funnel_multimedia_out_funnel_dl_west>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_dl_west_in_tpdm_dlwt0: endpoint {
     remote-endpoint =
     <&tpdm_dlwt0_out_funnel_dl_west>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_dl_west_in_tpdm_dlwt1: endpoint {
     remote-endpoint =
     <&tpdm_dlwt1_out_funnel_dl_west>;
    };
   };

  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_dl_west_out_tpda_dl_center_9: endpoint {
     remote-endpoint =
     <&tpda_dl_center_9_in_funnel_dl_west>;
     source = <&tpdm_video>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_dl_west_out_tpda_dl_center_10: endpoint {
     remote-endpoint =
     <&tpda_dl_center_10_in_funnel_dl_west>;
     source = <&tpdm_mdss>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_dl_west_out_tpda_dl_center_12: endpoint {
     remote-endpoint =
     <&tpda_dl_center_12_in_funnel_dl_west>;
     source = <&tpdm_mm>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_dl_west_out_tpda_dl_center_13: endpoint {
     remote-endpoint =
     <&tpda_dl_center_13_in_funnel_dl_west>;
     source = <&tpdm_rdpm>;
    };
   };

   port@4 {
    reg = <4>;
    funnel_dl_west_out_tpda_dl_center_14: endpoint {
     remote-endpoint =
     <&tpda_dl_center_14_in_funnel_dl_west>;
     source = <&tpdm_rdpm_mx>;
    };
   };

  };
 };

 tpda_dl_south: tpda@109c1000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x109c1000 0x1000>;
  reg-names = "tpda-base";

  qcom,tpda-atid = <75>;

  qcom,dsb-elem-size = <4 32>;
  qcom,cmb-elem-size = <1 32>,
        <2 32>;

  coresight-name = "coresight-tpda-dl_south";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@1 {
    reg = <1>;
    tpda_dl_south_1_in_tpdm_sdcc4: endpoint {
     remote-endpoint =
     <&tpdm_sdcc4_out_tpda_dl_south_1>;
    };
   };

   port@2 {
    reg = <2>;
    tpda_dl_south_in_tpdm_ufs: endpoint {
     remote-endpoint =
     <&tpdm_ufs_out_tpda_dl_south>;
    };
   };

   port@4 {
    reg = <4>;
    tpda_dl_south_2_in_tpdm_dl_south: endpoint {
     remote-endpoint =
     <&tpdm_dl_south_out_tpda_dl_south_2>;
    };
   };

  };

  out-ports {

   port {
    tpda_dl_south_out_funnel_dl_south: endpoint {
     remote-endpoint =
     <&funnel_dl_south_in_tpda_dl_south>;
    };
   };

  };
 };

 funnel_dl_south: funnel@109c2000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x109c2000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-dl_south";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    funnel_dl_south_in_tpda_dl_south: endpoint {
     remote-endpoint =
     <&tpda_dl_south_out_funnel_dl_south>;
    };
   };

  };

  out-ports {
   port {
    funnel_dl_south_out_funnel_in1: endpoint {
     remote-endpoint =
     <&funnel_in1_in_funnel_dl_south>;
    };
   };

  };
 };

 tpda_tmess: tpda@10cc4000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x10cc4000 0x1000>;
  reg-names = "tpda-base";

  qcom,cmb-elem-size = <0 32>,
        <1 32>,
        <2 32>;

  qcom,tpda-atid = <85>;

  coresight-name = "coresight-tpda-tmess";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@2 {
    reg = <2>;
    tpda_tmess_in_tpdm_tmess1: endpoint {
     remote-endpoint =
     <&tpdm_tmess1_out_tpda_tmess>;
    };
   };

   port@0 {
    reg = <0>;
    tpda_tmess_0_in_tpdm_tmess_prng: endpoint {
     remote-endpoint =
     <&tpdm_tmess_prng_out_tpda_tmess_0>;
    };
   };

   port@1 {
    reg = <1>;
    tpda_tmess_in_tpdm_tmess0: endpoint {
     remote-endpoint =
     <&tpdm_tmess0_out_tpda_tmess>;
    };
   };

  };

  out-ports {

   port {
    tpda_tmess_out_funnel_tmess: endpoint {
     remote-endpoint =
     <&funnel_tmess_in_tpda_tmess>;
    };
   };

  };
 };

 funnel_tmess: funnel@10cc5000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10cc5000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-tmess";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    funnel_tmess_in_tpda_tmess: endpoint {
     remote-endpoint =
     <&tpda_tmess_out_funnel_tmess>;
    };
   };

  };

  out-ports {
   port {
    funnel_tmess_out_funnel_dl_north: endpoint {
     remote-endpoint =
     <&funnel_dl_north_in_funnel_tmess>;
    };
   };

  };
 };

 tpda_dl_north: tpda@10ac1000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x10ac1000 0x1000>;
  reg-names = "tpda-base";

  qcom,tpda-atid = <97>;
  qcom,dsb-elem-size = <2 32>;
  qcom,cmb-elem-size = <1 32>;

  coresight-name = "coresight-tpda-dl_north";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@1 {
    reg = <1>;
    tpda_dl_north_1_in_tpdm_sdcc2: endpoint {
     remote-endpoint =
     <&tpdm_sdcc2_out_tpda_dl_north_1>;
    };
   };

   port@2 {
    reg = <2>;
    tpda_dl_north_2_in_tpdm_dl_north: endpoint {
     remote-endpoint =
     <&tpdm_dl_north_out_tpda_dl_north_2>;
    };
   };

  };

  out-ports {

   port {
    tpda_dl_north_out_funnel_dl_north: endpoint {
     remote-endpoint =
     <&funnel_dl_north_in_tpda_dl_north>;
    };
   };

  };
 };

 funnel_dl_north: funnel@10ac2000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10ac2000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-dl_north";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_dl_north_in_tpda_dl_north: endpoint {
     remote-endpoint =
     <&tpda_dl_north_out_funnel_dl_north>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_dl_north_in_funnel_spss: endpoint {
     remote-endpoint =
     <&funnel_spss_out_funnel_dl_north>;
    };
   };

   port@5 {
    reg = <5>;
    funnel_dl_north_in_funnel_tmess: endpoint {
     remote-endpoint =
     <&funnel_tmess_out_funnel_dl_north>;
    };
   };

  };

  out-ports {
   port {
    funnel_dl_north_out_funnel_in1: endpoint {
     remote-endpoint =
     <&funnel_in1_in_funnel_dl_north>;
    };
   };

  };
 };

 tpda_modem: tpda@10803000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x10803000 0x1000>;
  reg-names = "tpda-base";
  qcom,tpda-atid = <67>;

  qcom,dsb-elem-size = <0 32>;
  qcom,cmb-elem-size = <0 64>;

  coresight-name = "coresight-tpda-modem";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    tpda_modem_0_in_tpdm_modem_0: endpoint {
     remote-endpoint =
     <&tpdm_modem_0_out_tpda_modem_0>;
    };
   };

   port@1 {
    reg = <1>;
    tpda_modem_1_in_tpdm_modem_1: endpoint {
     remote-endpoint =
     <&tpdm_modem_1_out_tpda_modem_1>;
    };
   };

  };

  out-ports {

   port {
    tpda_modem_out_funnel_modem: endpoint {
     remote-endpoint =
     <&funnel_modem_in_tpda_modem>;
    };
   };

  };
 };

 funnel_modem_q6_dup: funnel@1080d000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x1080d000 0x1000>,
   <0x1080c000 0x1000>;
  reg-names = "funnel-base-dummy", "funnel-base-real";

  coresight-name = "coresight-funnel-modem_q6_dup";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
  qcom,duplicate-funnel;

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_modem_q6_dup_in_modem_etm0: endpoint {
     remote-endpoint =
     <&modem_etm0_out_funnel_modem_q6_dup>;
    };
   };

  };

  out-ports {
   port {
    funnel_modem_q6_dup_out_funnel_modem_q6: endpoint {
     remote-endpoint =
     <&funnel_modem_q6_in_funnel_modem_q6_dup>;
    };
   };

  };
 };

 funnel_modem_q6: funnel@1080c000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x1080c000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-modem_q6";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@1 {
    reg = <1>;
    funnel_modem_q6_in_funnel_modem_q6_dup: endpoint {
     remote-endpoint =
     <&funnel_modem_q6_dup_out_funnel_modem_q6>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_modem_q6_in_modem_diag: endpoint {
     remote-endpoint =
     <&modem_diag_out_funnel_modem_q6>;
    };
   };

  };

  out-ports {
   port {
    funnel_modem_q6_out_funnel_modem: endpoint {
     remote-endpoint =
     <&funnel_modem_in_funnel_modem_q6>;
    };
   };

  };
 };

 funnel_modem: funnel@10804000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10804000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-modem";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@1 {
    reg = <1>;
    funnel_modem_in_modem2_etm0: endpoint {
     remote-endpoint =
     <&modem2_etm0_out_funnel_modem>;
    };
   };

   port@0 {
    reg = <0>;
    funnel_modem_in_tpda_modem: endpoint {
     remote-endpoint =
     <&tpda_modem_out_funnel_modem>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_modem_in_funnel_modem_q6: endpoint {
     remote-endpoint =
     <&funnel_modem_q6_out_funnel_modem>;
    };
   };

  };

  out-ports {
   port {
    funnel_modem_out_funnel_in1: endpoint {
     remote-endpoint =
     <&funnel_in1_in_funnel_modem>;
    };
   };

  };
 };

 tpda_apss: tpda@13863000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x13863000 0x1000>;
  reg-names = "tpda-base";

  qcom,tpda-atid = <66>;

  qcom,dsb-elem-size = <2 32>,
        <4 32>;
  qcom,cmb-elem-size = <0 32>,
        <1 32>,
        <3 64>;

  coresight-name = "coresight-tpda-apss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    tpda_apss_0_in_tpdm_llm_silver: endpoint {
     remote-endpoint =
     <&tpdm_llm_silver_out_tpda_apss_0>;
    };
   };

   port@1 {
    reg = <1>;
    tpda_apss_1_in_tpdm_llm_gold: endpoint {
     remote-endpoint =
     <&tpdm_llm_gold_out_tpda_apss_1>;
    };
   };

   port@3 {
    reg = <3>;
    tpda_apss_3_in_tpdm_apss0: endpoint {
     remote-endpoint =
     <&tpdm_apss0_out_tpda_apss_3>;
    };
   };

   port@2 {
    reg = <2>;
    tpda_apss_2_in_tpdm_apss_llm: endpoint {
     remote-endpoint =
     <&tpdm_apss_llm_out_tpda_apss_2>;
    };
   };

   port@4 {
    reg = <4>;
    tpda_apss_4_in_tpdm_apps1: endpoint {
     remote-endpoint =
     <&tpdm_apps1_out_tpda_apss_4>;
    };
   };

  };

  out-ports {

   port {
    tpda_apss_out_funnel_apss: endpoint {
     remote-endpoint =
     <&funnel_apss_in_tpda_apss>;
    };
   };

  };
 };

 funnel_apss: funnel@13810000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x13810000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-apss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_apss_in_funnel_ete: endpoint {
     remote-endpoint =
     <&funnel_ete_out_funnel_apss>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_apss_in_tpda_apss: endpoint {
     remote-endpoint =
     <&tpda_apss_out_funnel_apss>;
    };
   };

  };

  out-ports {
   port {
    funnel_apss_out_funnel_in1: endpoint {
     remote-endpoint =
     <&funnel_in1_in_funnel_apss>;
    };
   };

  };
 };

 tpda_dl_center: tpda@10c2b000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x10c2b000 0x1000>;
  reg-names = "tpda-base";

  qcom,tpda-atid = <78>;

  qcom,dsb-elem-size = <5 32>,
        <6 32>,
        <7 32>,
        <9 32>,
        <10 32>,
        <12 32>,
        <15 32>,
        <17 32>,
        <20 32>,
        <21 32>,
        <25 32>,
        <26 32>;

  qcom,cmb-elem-size = <7 32>,
        <8 32>,
        <10 32>,
        <13 64>,
        <14 64>,
        <16 32>,
        <19 64>,
        <22 32>,
        <23 32>,
        <27 64>;

  coresight-name = "coresight-tpda-dl_center";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@a {
    reg = <10>;
    tpda_dl_center_10_in_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_out_tpda_dl_center_10>;
    };
   };

   port@d {
    reg = <13>;
    tpda_dl_center_13_in_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_out_tpda_dl_center_13>;
    };
   };

   port@c {
    reg = <12>;
    tpda_dl_center_12_in_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_out_tpda_dl_center_12>;
    };
   };

   port@f {
    reg = <15>;
    tpda_dl_center_15_in_funnel_turing: endpoint {
     remote-endpoint =
     <&funnel_turing_out_tpda_dl_center_15>;
    };
   };

   port@e {
    reg = <14>;
    tpda_dl_center_14_in_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_out_tpda_dl_center_14>;
    };
   };

   port@11 {
    reg = <17>;
    tpda_dl_center_17_in_funnel_gfx_dl: endpoint {
     remote-endpoint =
     <&funnel_gfx_dl_out_tpda_dl_center_17>;
    };
   };

   port@10 {
    reg = <16>;
    tpda_dl_center_16_in_funnel_turing: endpoint {
     remote-endpoint =
     <&funnel_turing_out_tpda_dl_center_16>;
    };
   };

   port@13 {
    reg = <19>;
    tpda_dl_center_19_in_tpdm_prng: endpoint {
     remote-endpoint =
     <&tpdm_prng_out_tpda_dl_center_19>;
    };
   };

   port@17 {
    reg = <23>;
    tpda_dl_center_23_in_tpdm_ipa: endpoint {
     remote-endpoint =
     <&tpdm_ipa_out_tpda_dl_center_23>;
    };
   };

   port@16 {
    reg = <22>;
    tpda_dl_center_22_in_tpdm_vsense: endpoint {
     remote-endpoint =
     <&tpdm_vsense_out_tpda_dl_center_22>;
    };
   };

   port@1a {
    reg = <26>;
    tpda_dl_center_26_in_tpdm_dlct: endpoint {
     remote-endpoint =
     <&tpdm_dlct_out_tpda_dl_center_26>;
    };
   };

   port@14 {
    reg = <20>;
    tpda_dl_center_20_in_tpdm_qm: endpoint {
     remote-endpoint =
     <&tpdm_qm_out_tpda_dl_center_20>;
    };
   };

   port@1b {
    reg = <27>;
    tpda_dl_center_27_in_tpdm_ipcc: endpoint {
     remote-endpoint =
     <&tpdm_ipcc_out_tpda_dl_center_27>;
    };
   };

   port@5 {
    reg = <5>;
    tpda_dl_center_5_in_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_out_tpda_dl_center_5>;
    };
   };

   port@4 {
    reg = <4>;
    tpda_dl_center_4_in_funnel_lpass: endpoint {
     remote-endpoint =
     <&funnel_lpass_out_tpda_dl_center_4>;
    };
   };

   port@7 {
    reg = <7>;
    tpda_dl_center_7_in_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_out_tpda_dl_center_7>;
    };
   };

   port@6 {
    reg = <6>;
    tpda_dl_center_6_in_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_out_tpda_dl_center_6>;
    };
   };

   port@9 {
    reg = <9>;
    tpda_dl_center_9_in_funnel_dl_west: endpoint {
     remote-endpoint =
     <&funnel_dl_west_out_tpda_dl_center_9>;
    };
   };

   port@8 {
    reg = <8>;
    tpda_dl_center_8_in_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_out_tpda_dl_center_8>;
    };
   };

   port@15 {
    reg = <21>;
    tpda_dl_center_21_in_tpdm_gcc: endpoint {
     remote-endpoint =
     <&tpdm_gcc_out_tpda_dl_center_21>;
    };
   };

  };

  out-ports {

   port {
    tpda_dl_center_out_funnel_dl_center: endpoint {
     remote-endpoint =
     <&funnel_dl_center_in_tpda_dl_center>;
    };
   };

  };
 };

 funnel_dl_center: funnel@10c2c000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10c2c000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-dl_center";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_dl_center_in_tpda_dl_center: endpoint {
     remote-endpoint =
     <&tpda_dl_center_out_funnel_dl_center>;
    };
   };

   port@4 {
    reg = <4>;
    funnel_dl_center_in_funnel_ddr_dl0: endpoint {
     remote-endpoint =
     <&funnel_ddr_dl0_out_funnel_dl_center>;
    };
   };

   port@6 {
    reg = <6>;
    funnel_dl_center_in_funnel_turing: endpoint {
     remote-endpoint =
     <&funnel_turing_out_funnel_dl_center>;
    };
   };

   port@7 {
    reg = <7>;
     funnel_dl_center_in_funnel_gfx_dl: endpoint {
     remote-endpoint =
     <&funnel_gfx_dl_out_funnel_dl_center>;
    };
   };
  };

  out-ports {
   port {
    funnel_dl_center_out_funnel_in1: endpoint {
     remote-endpoint =
     <&funnel_in1_in_funnel_dl_center>;
    };
   };

  };
 };

 tpda_qdss: tpda@10004000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x10004000 0x1000>;
  reg-names = "tpda-base";

  qcom,tpda-atid = <65>;
  coresight-name = "coresight-tpda-qdss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@1 {
    reg = <1>;
    tpda_qdss_1_in_tpdm_spdm: endpoint {
     remote-endpoint =
     <&tpdm_spdm_out_tpda_qdss_1>;
    };
   };

   port@0 {
    reg = <0>;
    tpda_qdss_0_in_tpdm_dcc: endpoint {
     remote-endpoint =
     <&tpdm_dcc_out_tpda_qdss_0>;
    };
   };

  };

  out-ports {

   port {
    tpda_qdss_out_funnel_in0: endpoint {
     remote-endpoint =
     <&funnel_in0_in_tpda_qdss>;
    };
   };

  };
 };

 funnel_in0: funnel@10041000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10041000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-in0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_in0_in_snoc: endpoint {
     remote-endpoint =
     <&snoc_out_funnel_in0>;
    };
   };

   port@7 {
    reg = <7>;
    funnel_in0_in_stm: endpoint {
     remote-endpoint =
     <&stm_out_funnel_in0>;
    };
   };

   port@6 {
    reg = <6>;
    funnel_in0_in_tpda_qdss: endpoint {
     remote-endpoint =
     <&tpda_qdss_out_funnel_in0>;
    };
   };

  };

  out-ports {
   port {
    funnel_in0_out_funnel_qdss: endpoint {
     remote-endpoint =
     <&funnel_qdss_in_funnel_in0>;
    };
   };

  };
 };

 funnel_in1: funnel@10042000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10042000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-in1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_in1_in_funnel_dl_south: endpoint {
     remote-endpoint =
     <&funnel_dl_south_out_funnel_in1>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_in1_in_funnel_dl_north: endpoint {
     remote-endpoint =
     <&funnel_dl_north_out_funnel_in1>;
    };
   };

   port@4 {
    reg = <4>;
    funnel_in1_in_funnel_apss: endpoint {
     remote-endpoint =
     <&funnel_apss_out_funnel_in1>;
    };
   };

   port@5 {
    reg = <5>;
    funnel_in1_in_funnel_modem: endpoint {
     remote-endpoint =
     <&funnel_modem_out_funnel_in1>;
    };
   };

   port@6 {
    reg = <6>;
    funnel_in1_in_funnel_dl_center: endpoint {
     remote-endpoint =
     <&funnel_dl_center_out_funnel_in1>;
    };
   };

  };

  out-ports {
   port {
    funnel_in1_out_funnel_qdss: endpoint {
     remote-endpoint =
     <&funnel_qdss_in_funnel_in1>;
    };
   };

  };
 };

 funnel_qdss: funnel@10045000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10045000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-qdss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@1 {
    reg = <1>;
    funnel_qdss_in_funnel_in1: endpoint {
     remote-endpoint =
     <&funnel_in1_out_funnel_qdss>;
    };
   };

   port@0 {
    reg = <0>;
    funnel_qdss_in_funnel_in0: endpoint {
     remote-endpoint =
     <&funnel_in0_out_funnel_qdss>;
    };
   };

  };

  out-ports {
   port {
    funnel_qdss_out_funnel_aoss: endpoint {
     remote-endpoint =
     <&funnel_aoss_in_funnel_qdss>;
    };
   };

  };
 };

 tpda_aoss: tpda@10b08000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb969>;

  reg = <0x10b08000 0x1000>;
  reg-names = "tpda-base";

  coresight-name = "coresight-tpda-aoss";

  qcom,tpda-atid = <71>;

  qcom,cmb-elem-size = <0 64>,
        <1 64>,
        <2 64>,
        <3 64>;

  qcom,dsb-elem-size = <4 32>;

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {

   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    tpda_aoss_0_in_tpdm_swao_prio_0: endpoint {
     remote-endpoint =
     <&tpdm_swao_prio_0_out_tpda_aoss_0>;
    };
   };

   port@1 {
    reg = <1>;
    tpda_aoss_1_in_tpdm_swao_prio_1: endpoint {
     remote-endpoint =
     <&tpdm_swao_prio_1_out_tpda_aoss_1>;
    };
   };

   port@2 {
    reg = <2>;
    tpda_aoss_2_in_tpdm_swao_prio_2: endpoint {
     remote-endpoint =
     <&tpdm_swao_prio_2_out_tpda_aoss_2>;
    };
   };

   port@3 {
    reg = <3>;
    tpda_aoss_3_in_tpdm_swao_prio_3: endpoint {
     remote-endpoint =
     <&tpdm_swao_prio_3_out_tpda_aoss_3>;
    };
   };

   port@4 {
    reg = <4>;
    tpda_aoss_4_in_tpdm_swao: endpoint {
     remote-endpoint =
     <&tpdm_swao_out_tpda_aoss_4>;
    };
   };

  };

  out-ports {

   port {
    tpda_aoss_out_funnel_aoss: endpoint {
     remote-endpoint =
     <&funnel_aoss_in_tpda_aoss>;
    };
   };

  };
 };

 funnel_aoss: funnel@10b04000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb908>;

  reg = <0x10b04000 0x1000>;
  reg-names = "funnel-base";

  coresight-name = "coresight-funnel-aoss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@3 {
    reg = <3>;
    funnel_aoss_in_funnel_ddr_lpi: endpoint {
     remote-endpoint =
     <&funnel_ddr_lpi_out_funnel_aoss>;
    };
   };

   port@5 {
    reg = <5>;
    funnel_aoss_in_funnel_lpass_lpi: endpoint {
     remote-endpoint =
     <&funnel_lpass_lpi_out_funnel_aoss>;
    };
   };

   port@7 {
    reg = <7>;
    funnel_aoss_in_funnel_qdss: endpoint {
     remote-endpoint =
     <&funnel_qdss_out_funnel_aoss>;
    };
   };

   port@6 {
    reg = <6>;
    funnel_aoss_in_tpda_aoss: endpoint {
     remote-endpoint =
     <&tpda_aoss_out_funnel_aoss>;
    };
   };

  };

  out-ports {
   port {
    funnel_aoss_out_tmc_etf: endpoint {
     remote-endpoint =
     <&tmc_etf_in_funnel_aoss>;
    };
   };

  };
 };

 dummy_eud: dummy_sink {
  compatible = "qcom,coresight-dummy";

  coresight-name = "coresight-eud";

  qcom,dummy-sink;
  in-ports {
   port {
    eud_in_replicator_swao: endpoint {
     remote-endpoint =
      <&replicator_swao_out_eud>;
    };
   };
  };
 };

 tmc_etf: tmc@10b05000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb961>;
  reg = <0x10b05000 0x1000>;
  reg-names = "tmc-base";

  coresight-name = "coresight-tmc-etf";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    tmc_etf_in_funnel_aoss: endpoint {
     remote-endpoint =
     <&funnel_aoss_out_tmc_etf>;
    };
   };
  };

  out-ports {
   port {
    tmc_etf_out_replicator_swao: endpoint {
     remote-endpoint =
     <&replicator_swao_in_tmc_etf>;
    };
   };
  };
 };

 replicator_swao: replicator@10b06000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb909>;
  reg = <0x10b06000 0x1000>;
  reg-names = "replicator-base";

  coresight-name = "coresight-replicator_swao";

  qcom,replicator-loses-context;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    replicator_swao_in_tmc_etf: endpoint {
     remote-endpoint =
     <&tmc_etf_out_replicator_swao>;
    };
   };
  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    replicator_swao_out_replicator_qdss: endpoint {
     remote-endpoint =
     <&replicator_qdss_in_replicator_swao>;
    };
   };

   port@1 {
    reg = <1>;
    replicator_swao_out_eud: endpoint {
     remote-endpoint =
       <&eud_in_replicator_swao>;
    };
   };
  };
 };

 replicator_qdss: replicator@10046000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb909>;
  reg = <0x10046000 0x1000>;
  reg-names = "replicator-base";

  coresight-name = "coresight-replicator_qdss";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    replicator_qdss_in_replicator_swao: endpoint {
     remote-endpoint =
     <&replicator_swao_out_replicator_qdss>;
    };
   };
  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    replicator_qdss_out_replicator_etr: endpoint {
     remote-endpoint =
     <&replicator_etr_in_replicator_qdss>;
    };
   };
  };
 };

 replicator_etr: replicator@1004e000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb909>;
  reg = <0x1004e000 0x1000>;
  reg-names = "replicator-base";

  coresight-name = "coresight-replicator_etr";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    replicator_etr_in_replicator_qdss: endpoint {
     remote-endpoint =
     <&replicator_qdss_out_replicator_etr>;
    };
   };
  };

  out-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    replicator_etr_out_tmc_etr: endpoint {
     remote-endpoint =
     <&tmc_etr_in_replicator_etr>;
    };
   };

   port@1 {
    reg = <1>;
    replicator_etr_out_tmc_etr1: endpoint {
     remote-endpoint =
     <&tmc_etr1_in_replicator_etr>;
    };
   };
  };
 };

 tmc_etr: tmc@10048000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb961>;
  reg = <0x10048000 0x1000>,
   <0x10064000 0x16000>;
  reg-names = "tmc-base", "bam-base";

  qcom,iommu-dma = "bypass";
  iommus = <&apps_smmu 0x04c0 0x0020>;

  qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;

  qcom,mem_support;
  qcom,sw-usb;
  dma-coherent;
  coresight-name = "coresight-tmc-etr";

  coresight-csr = <&csr>;
  csr-atid-offset = <0xf8>;
  csr-irqctrl-offset = <0x6c>;
  byte-cntr-name = "byte-cntr";
  byte-cntr-class-name = "coresight-tmc-etr-stream";

  interrupts = <0 270 1>;
  interrupt-names = "byte-cntr-irq";

  arm,scatter-gather;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    tmc_etr_in_replicator_etr: endpoint {
     remote-endpoint =
     <&replicator_etr_out_tmc_etr>;
    };
   };
  };
 };

 tmc_etr1: tmc@1004f000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb961>;
  reg = <0x1004f000 0x1000>;
  reg-names = "tmc-base";

  coresight-name = "coresight-tmc-etr1";

  iommus = <&apps_smmu 0x0500 0>;
  qcom,iommu-dma-addr-pool = <0x0 0xffc00000>;
  dma-coherent;

  qcom,mem_support;
  coresight-csr = <&csr>;
  csr-atid-offset = <0x108>;
  csr-irqctrl-offset = <0x70>;
  byte-cntr-name = "byte-cntr1";
  byte-cntr-class-name = "coresight-tmc-etr1-stream";

  interrupts = <0 269 1>;
  interrupt-names = "byte-cntr-irq";

  arm,scatter-gather;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  in-ports {
   port {
    tmc_etr1_in_replicator_etr: endpoint {
     remote-endpoint =
     <&replicator_etr_out_tmc_etr1>;
    };
   };
  };
 };

 csr: csr@10001000 {
  compatible = "qcom,coresight-csr";
  reg = <0x10001000 0x1000>;
  reg-names = "csr-base";

  coresight-name = "coresight-csr";
  qcom,usb-bam-support;
  qcom,hwctrl-set-support;
  qcom,set-byte-cntr-support;

  qcom,blk-size = <1>;
 };

 swao_csr: csr@10b11000 {
  compatible = "qcom,coresight-csr";
  reg = <0x10b11000 0x1000>,
        <0x10b110f8 0x50>;
  reg-names = "csr-base", "msr-base";

  coresight-name = "coresight-swao-csr";
  qcom,timestamp-support;
  qcom,msr-support;

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  qcom,blk-size = <1>;
 };

 qc_cti: cti@10010000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10010000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-qc_cti";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  qcom,cti-gpio-trigout = <16>;
  pinctrl-names = "cti-trigout-pctrl";
  pinctrl-0 = <&trigout_a>;
 };

 cti0: cti@10c2a000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10c2a000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cti0";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 dlmm_cti0: cti@10c09000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10c09000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-dlmm_cti0";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 ddr_dl_0_cti_0: cti@10d02000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10d02000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-ddr_dl_0_cti_0";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 ddr_ch02_dl_cti_0: cti@10d21000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10d21000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-ddr_ch02_dl_cti_0";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 ddr_ch13_dl_cti_0: cti@10d31000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10d31000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-ddr_ch13_dl_cti_0";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 lpass_dl_cti: cti@10845000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10845000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-lpass_dl_cti";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 gpu_isdb_cti: cti@10961000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10961000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-gpu_isdb_cti";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 gpu_cortex_m3: cti@10962000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10962000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-gpu_cortex_m3";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 gpu_dl: cti@10901000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10901000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-gpu_dl";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 iris_dl_cti: cti@10831000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10831000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-iris_dl_cti";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 mdss_dl_cti: cti@10c61000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10c61000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-mdss_dl_cti";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 turing_dl_cti_0: cti@10982000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10982000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-turing_dl_cti_0";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 turing_q6_cti: cti@1098b000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x1098b000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-turing_q6_cti";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 swao_cti: cti@10b00000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10b00000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-swao_cti";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 ddr_dl2_lpi: cti@10b21000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10b21000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-ddr_dl2_lpi";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 ddr_dl_1_cti_0: cti@10d08000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10d08000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-ddr_dl_1_cti_0";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 cortex_m3: cti@10b13000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10b13000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cortex_m3";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 lpass_lpi_cti1: cti@10b41000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10b41000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-lpass_lpi_cti1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 lpass_lpi_cti3: cti@10b51000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10b51000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-lpass_lpi_cti3";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 lpass_q6_cti: cti@10b4b000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10b4b000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-lpass_q6_cti";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 lpass_ssc_sdc_cti: cti@10b42000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10b42000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-lpass_ssc_sdc_cti";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 apss_cti0: cti@138e0000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x138e0000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-apss_cti0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 apss_cti1: cti@138f0000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x138f0000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-apss_cti1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 apss_cti2: cti@13900000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x13900000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-apss_cti2";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 camera_dl: cti@10c15000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10c15000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-camera_dl";

  status = "disabled";
  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 riscv_cti: cti@1382b000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x1382b000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-riscv_cti";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 riscv_sifive_cti: cti@1382e000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x1382e000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-riscv_sifive_cti";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 mss_q6_cti: cti@1080b000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x1080b000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-mss_q6_cti";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 mss_vq6_cti: cti@10813000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10813000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-mss_vq6_cti";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 tmess_cti_0: cti@10cc2000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10cc2000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-tmess_cti_0";

  status = "disabled";
  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 tmess_cti_1: cti@10cc3000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10cc3000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-tmess_cti_1";

  status = "disabled";
  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 tmess_cti_2: cti@10cc4000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10cc4000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-tmess_cti_2";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };


 tmess_cti_3: cti@10cc5000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10cc5000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-tmess_cti_3";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 tmess_cti_4: cti@10cc6000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10cc6000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-tmess_cti_4";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 tmess_cpu: cti@10cd1000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10cd1000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-tmess_cpu";

  status = "disabled";
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 modem_tp_cti: cti@10802000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10802000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-modem_tp_cti";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 apss_atb_cti: cti@13862000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x13862000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-apss_atb_cti";

  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 ddrss_shrm2: cti@10d11000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10d11000 0x1000>;

  status = "disabled";
  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-ddrss_shrm2";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 cpu0: cti@12010000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12010000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU0>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 spss_cti: cti@10881000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x10881000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-spss_cti";

  status = "disabled";
  qcom,extended_cti;
  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 cpu1: cti@12020000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12020000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU1>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 cpu2: cti@12030000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12030000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu2";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU2>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 cpu3: cti@12040000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12040000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu3";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU3>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 cpu4: cti@12050000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12050000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu4";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU4>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 cpu5: cti@112060000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12060000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu5";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU5>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 cpu6: cti@12070000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12070000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu6";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU6>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 cpu7: cti@12080000 {
  compatible = "arm,coresight-cti", "arm,primecell";
  reg = <0x12080000 0x1000>;

  arm,primecell-periphid = <0x000bb922>;
  coresight-name = "coresight-cti-cpu7";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";

  trig-conns {
   cpu = <&CPU7>;
   arm,trig-in-sigs = <0 1 2 3 4 5 6 7 8 9>;
   arm,trig-out-sigs = <0 1 2 3 4 5 6 7 8 9>;
  };
 };

 ipcb_tgu: tgu@10b0e000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb999>;
  reg = <0x10b0e000 0x1000>;
  reg-names = "tgu-base";
  tgu-steps = <3>;
  tgu-conditions = <4>;
  tgu-regs = <4>;
  tgu-timer-counters = <8>;

  coresight-name = "coresight-tgu-ipcb";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 ete0 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU0>;
  phy-cpu = <0>;

  coresight-name = "coresight-ete0";
  qcom,skip-power-up;
  atid = <1>;
  out-ports {
   port {
    ete0_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete0>;
    };
   };
  };
 };

 ete1 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU1>;
  phy-cpu = <1>;

  coresight-name = "coresight-ete1";
  qcom,skip-power-up;
  atid = <2>;
  out-ports {
   port {
    ete1_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete1>;
    };
   };
  };
 };

 ete2 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU2>;
  phy-cpu = <2>;

  coresight-name = "coresight-ete2";
  qcom,skip-power-up;
  atid = <3>;
  out-ports {
   port {
    ete2_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete2>;
    };
   };
  };
 };

 ete3 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU3>;
  phy-cpu = <3>;

  coresight-name = "coresight-ete3";
  qcom,skip-power-up;
  atid = <4>;
  out-ports {
   port {
    ete3_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete3>;
    };
   };
  };
 };

 ete4 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU4>;
  phy-cpu = <4>;

  coresight-name = "coresight-ete4";
  qcom,skip-power-up;
  atid = <5>;
  out-ports {
   port {
    ete4_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete4>;
    };
   };
  };
 };

 ete5 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU5>;
  phy-cpu = <5>;

  coresight-name = "coresight-ete5";
  qcom,skip-power-up;
  atid = <6>;
  out-ports {
   port {
    ete5_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete5>;
    };
   };
  };
 };

 ete6 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU6>;
  phy-cpu = <6>;

  coresight-name = "coresight-ete6";
  qcom,skip-power-up;
  atid = <7>;
  out-ports {
   port {
    ete6_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete6>;
    };
   };
  };
 };

 ete7 {
  compatible = "arm,embedded-trace-extension";
  cpu = <&CPU7>;
  phy-cpu = <7>;

  coresight-name = "coresight-ete7";
  qcom,skip-power-up;
  atid = <8>;
  out-ports {
   port {
    ete7_out_funnel_ete: endpoint {
    remote-endpoint = <&funnel_ete_in_ete7>;
    };
   };
  };
 };

 funnel_ete {
  compatible = "arm,coresight-static-funnel";
  coresight-name = "coresight-funnel-ete";

  out-ports {
   port {
    funnel_ete_out_funnel_apss: endpoint {
     remote-endpoint =
     <&funnel_apss_in_funnel_ete>;
    };
   };
  };

  in-ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    funnel_ete_in_ete0: endpoint {
     remote-endpoint =
     <&ete0_out_funnel_ete>;
    };
   };

   port@1 {
    reg = <1>;
    funnel_ete_in_ete1: endpoint {
    remote-endpoint =
     <&ete1_out_funnel_ete>;
    };
   };

   port@2 {
    reg = <2>;
    funnel_ete_in_ete2: endpoint {
    remote-endpoint =
     <&ete2_out_funnel_ete>;
    };
   };

   port@3 {
    reg = <3>;
    funnel_ete_in_ete3: endpoint {
    remote-endpoint =
     <&ete3_out_funnel_ete>;
    };
   };

   port@4 {
    reg = <4>;
    funnel_ete_in_ete4: endpoint {
    remote-endpoint =
     <&ete4_out_funnel_ete>;
    };
   };

   port@5 {
    reg = <5>;
    funnel_ete_in_ete5: endpoint {
     remote-endpoint =
     <&ete5_out_funnel_ete>;
    };
   };

   port@6 {
    reg = <6>;
    funnel_ete_in_ete6: endpoint {
     remote-endpoint =
     <&ete6_out_funnel_ete>;
    };
   };

   port@7 {
    reg = <7>;
    funnel_ete_in_ete7: endpoint {
     remote-endpoint =
     <&ete7_out_funnel_ete>;
    };
   };
  };
 };

 spmi_tgu0: tgu@10b0f000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb999>;

  reg = <0x10b0f000 0x1000>;
  reg-names = "tgu-base";

  tgu-steps = <3>;
  tgu-conditions = <4>;
  tgu-regs = <9>;
  tgu-timer-counters = <8>;

  coresight-name = "coresight-tgu-spmi0";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };

 spmi_tgu1: tgu@10b10000 {
  compatible = "arm,primecell";
  arm,primecell-periphid = <0x000bb999>;

  reg = <0x10b10000 0x1000>;
  reg-names = "tgu-base";

  tgu-steps = <3>;
  tgu-conditions = <4>;
  tgu-regs = <9>;
  tgu-timer-counters = <8>;

  coresight-name = "coresight-tgu-spmi1";

  clocks = <&aoss_qmp>;
  clock-names = "apb_pclk";
 };
};
# 3665 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-debug.dtsi" 1
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/soc/qcom,dcc_v2.h" 1
# 2 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-debug.dtsi" 2

&reserved_memory {
 #address-cells = <2>;
 #size-cells = <2>;
 ranges;

 dump_mem: mem_dump_region {
  compatible = "shared-dma-pool";
  alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
  reusable;
  alignment = <0x0 0x400000>;
  size = <0 0x3400000>;
 };
};

&soc {
 dcc: dcc_v2@100ff000 {
  compatible = "qcom,dcc-v2";
  reg = <0x100ff000 0x1000>,
        <0x10080000 0x18000>;

  qcom,transaction_timeout = <0>;

  reg-names = "dcc-base", "dcc-ram-base";
  dcc-ram-offset = <0>;

  per-ll-reg-cnt = <9>;
  ll-reg-offsets = <
   0x034 0x03C 0x040 0x044 0x04C 0x050 0x068 0x06C 0x038
   0x0B4 0x0BC 0x0C0 0x0C4 0x0CC 0x0D0 0x0E8 0x0EC 0x0B8
   0x134 0x13C 0x140 0x144 0x14C 0x150 0x168 0x16C 0x138
   0x1B4 0x1BC 0x1C0 0x1C4 0x1CC 0x1D0 0x1E8 0x1EC 0x1B8
   0x234 0x23C 0x240 0x244 0x24C 0x250 0x268 0x26C 0x238
   0x2B4 0x2BC 0x2C0 0x2C4 0x2CC 0x2D0 0x2E8 0x2EC 0x2B8
   0x334 0x33C 0x340 0x344 0x34C 0x350 0x368 0x36C 0x338
   0x3B4 0x3BC 0x3C0 0x3C4 0x3CC 0x3D0 0x3E8 0x3EC 0x3B8>;

  link_list_0 {
   qcom,curr-link-list = <6>;
   qcom,data-sink = "sram";
   qcom,link-list = <0 0x00185000 1 0>,
    <1 0x00185000 1 0>,
    <0 0x00185000 1 0>,
    <0 0x1084c000 1 1>,
    <0 0x10c06000 1 1>,
    <1 0x1084c000 0 1>,
    <1 0x10c06000 0 1>,
    <0 0x1084c000 1 1>,
    <0 0x10c06000 1 1>,
    <0 0x01fc4080 3 0>,
    <0 0x01fc4090 1 0>,
    <0 0x6802028 1 0>,
    <0 0x68b0404 2 0>,
    <0 0x68b0208 3 0>,
    <0 0x68b0228 3 0>,
    <0 0x68b0248 3 0>,
    <0 0x68b0268 3 0>,
    <0 0x7200404 2 0>,
    <0 0x7200208 3 0>,
    <0 0x7200228 3 0>,
    <0 0x7200248 3 0>,
    <0 0x7200268 3 0>,
    <0 0x32302028 1 0>,
    <0 0x323b0404 2 0>,
    <0 0x323b0208 3 0>,
    <0 0x323b0228 3 0>,
    <0 0x323b0248 3 0>,
    <0 0x323b0268 3 0>,
    <0 0x320a4404 2 0>,
    <0 0x320a4208 3 0>,
    <0 0x320a4228 3 0>,
    <0 0x320a4248 3 0>,
    <0 0x320a4268 3 0>,
    <0 0x4082028 1 0>,
    <0 0x4130404 2 0>,
    <0 0x4130208 3 0>,
    <0 0x4130228 3 0>,
    <0 0x4130248 3 0>,
    <0 0x4130268 3 0>,
    <0 0x4200404 2 0>,
    <0 0x4200208 3 0>,
    <0 0x4200228 3 0>,
    <0 0x4200248 3 0>,
    <0 0x4200268 3 0>,
    <0 0x1780005c 1 0>,
    <0 0x1781005c 1 0>,
    <0 0x1782005c 1 0>,
    <0 0x1783005c 1 0>,
    <0 0x1784005c 1 0>,
    <0 0x1785005c 1 0>,
    <0 0x1786005c 1 0>,
    <0 0x1787005c 1 0>,
    <0 0x1740003c 1 0>,
    <0 0x17600238 1 0>,
    <0 0x17600240 11 0>,
    <0 0x17600530 1 0>,
    <0 0x1760051c 1 0>,
    <0 0x17600524 1 0>,
    <0 0x1760052c 1 0>,
    <0 0x17600518 1 0>,
    <0 0x17600520 1 0>,
    <0 0x17600528 1 0>,
    <0 0x17600404 3 0>,
    <0 0x1760041c 3 0>,
    <0 0x17600434 1 0>,
    <0 0x1760043c 1 0>,
    <0 0x17600440 1 0>,
    <0 0x17400438 1 0>,
    <0 0x17600044 1 0>,
    <0 0x17600500 1 0>,
    <0 0x17600504 5 0>,
    <0 0x17900908 1 0>,
    <0 0x17900c18 1 0>,
    <0 0x17901908 1 0>,
    <0 0x17901c18 1 0>,
    <0 0x17b90810 1 0>,
    <0 0x17b90c50 1 0>,
    <0 0x17b90814 1 0>,
    <0 0x17b90c54 1 0>,
    <0 0x17b90818 1 0>,
    <0 0x17b90c58 1 0>,
    <0 0x17b93a04 2 0>,
    <0 0x17ba0810 1 0>,
    <0 0x17ba0c50 1 0>,
    <0 0x17ba0814 1 0>,
    <0 0x17ba0c54 1 0>,
    <0 0x17ba0818 1 0>,
    <0 0x17ba0c58 1 0>,
    <0 0x17ba3a04 2 0>,
    <0 0x17b93000 80 0>,
    <0 0x17ba3000 80 0>,
    <0 0x0c201244 1 0>,
    <0 0x0c202244 1 0>,
    <0 0x17b00000 1 0>,
    <0 0x17a94030 1 0>,
    <0 0x17a9408c 1 0>,
    <1 0x17a9409c 0x78 0>,
    <1 0x17a9409c 0x0 0>,
    <1 0x17a94048 0x1 0>,
    <1 0x17a94090 0x0 0>,
    <1 0x17a94090 0x25 0>,
    <0 0x17a94098 1 0>,
    <1 0x17a94048 0x1d 0>,
    <1 0x17a94090 0x0 0>,
    <1 0x17a94090 0x25 0>,
    <0 0x17a94098 1 0>,
    <0 0x17a90030 1 0>,
    <0 0x17a9008c 1 0>,
    <1 0x17a9009c 0x78 0>,
    <1 0x17a9009c 0x0 0>,
    <1 0x17a90048 0x1 0>,
    <1 0x17a90090 0x0 0>,
    <1 0x17a90090 0x25 0>,
    <0 0x17a90098 1 0>,
    <1 0x17a90048 0x1d 0>,
    <1 0x17a90090 0x0 0>,
    <1 0x17a90090 0x25 0>,
    <0 0x17a90098 1 0>,
    <0 0x17a92030 1 0>,
    <0 0x17a9208c 1 0>,
    <1 0x17a9209c 0x78 0>,
    <1 0x17a9209c 0x0 0>,
    <1 0x17a92048 0x1 0>,
    <1 0x17a92090 0x0 0>,
    <1 0x17a92090 0x25 0>,
    <0 0x17a92098 1 0>,
    <1 0x17a92048 0x1d 0>,
    <1 0x17a92090 0x0 0>,
    <1 0x17a92090 0x25 0>,
    <0 0x17a92098 1 0>,
    <0 0x17a96030 1 0>,
    <0 0x17a9608c 1 0>,
    <1 0x17a9609c 0x78 0>,
    <1 0x17a9609c 0x0 0>,
    <1 0x17a96048 0x1 0>,
    <1 0x17a96090 0x0 0>,
    <1 0x17a96090 0x25 0>,
    <0 0x17a96098 1 0>,
    <1 0x17a96048 0x1d 0>,
    <1 0x17a96090 0x0 0>,
    <1 0x17a96090 0x25 0>,
    <0 0x17a96098 1 0>,
    <0 0x17d98024 1 0>,
    <0 0x13822000 1 1>,
    <0 0x221c20a4 1 0>,
    <0 0x01fc8000 1 0>,
    <0 0x17400038 1 0>,
    <0 0x17d91020 1 0>,
    <0 0x17d92020 1 0>,
    <0 0x17d93020 1 0>,
    <0 0x17d90020 1 0>,
    <0 0x17d9134c 1 0>,
    <0 0x17d9234c 1 0>,
    <0 0x17d9334c 1 0>,
    <0 0x17d9034c 1 0>,
    <0 0x17d91300 1 0>,
    <0 0x17d92300 1 0>,
    <0 0x17d93300 1 0>,
    <0 0x17d90300 1 0>,
    <0 0x24183040 1 0>,
    <0 0x24183048 1 0>,
    <0 0x24102010 1 0>,
    <0 0x24102020 6 0>,
    <0 0x24102410 1 0>,
    <0 0x24102420 6 0>,
    <0 0x24142010 1 0>,
    <0 0x24142020 6 0>,
    <0 0x24142410 1 0>,
    <0 0x24142420 6 0>,
    <0 0x24182010 1 0>,
    <0 0x24182020 6 0>,
    <0 0x24182410 1 0>,
    <0 0x24182420 6 0>,
    <0 0x24100810 1 0>,
    <0 0x24100838 1 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100838 1 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100838 1 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100838 1 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100830 2 0>,
    <0 0x24100808 2 0>,
    <0 0x24100c10 1 0>,
    <0 0x24100c38 1 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c38 1 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c38 1 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c38 1 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c30 2 0>,
    <0 0x24100c08 2 0>,
    <0 0x24140810 1 0>,
    <0 0x24140838 1 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140838 1 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140838 1 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140838 1 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140830 2 0>,
    <0 0x24140808 2 0>,
    <0 0x24140c10 1 0>,
    <0 0x24140c38 1 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c38 1 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c38 1 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c38 1 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c30 2 0>,
    <0 0x24140c08 2 0>,
    <0 0x24180010 1 0>,
    <0 0x24180038 1 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180038 1 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180038 1 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180038 1 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180030 2 0>,
    <0 0x24180008 2 0>,
    <0 0x24180410 1 0>,
    <0 0x24180438 1 0>,
    <0 0x24180430 2 0>,
    <0 0x24180430 2 0>,
    <0 0x24180430 2 0>,
    <0 0x24180430 2 0>,
    <0 0x24180438 1 0>,
    <0 0x24180430 2 0>,
    <0 0x24180430 2 0>,
    <0 0x24180430 2 0>,
    <0 0x24180430 2 0>,
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    <0 0x25225010 1 0>,
    <0 0x25225000 1 0>,
    <0 0x25240064 1 0>,
    <0 0x25240070 1 0>,
    <0 0x25240074 1 0>,
    <0 0x25240078 1 0>,
    <0 0x2524007c 1 0>,
    <0 0x25240080 1 0>,
    <0 0x2524002c 1 0>,
    <0 0x25240030 1 0>,
    <0 0x25240034 1 0>,
    <0 0x25240038 1 0>,
    <0 0x25240048 1 0>,
    <0 0x2524004c 1 0>,
    <0 0x25240050 1 0>,
    <0 0x25240054 1 0>,
    <0 0x25240058 1 0>,
    <0 0x25240060 1 0>,
    <0 0x2567718c 1 0>,
    <0 0x256771b0 1 0>,
    <0 0x25677204 1 0>,
    <0 0x25677208 1 0>,
    <0 0x2567720c 1 0>,
    <0 0x25677210 1 0>,
    <0 0x25677214 1 0>,
    <0 0x25623210 1 0>,
    <0 0x25625010 1 0>,
    <0 0x25625000 1 0>,
    <0 0x25640064 1 0>,
    <0 0x25640070 1 0>,
    <0 0x25640074 1 0>,
    <0 0x25640078 1 0>,
    <0 0x2564007c 1 0>,
    <0 0x25640080 1 0>,
    <0 0x2564002c 1 0>,
    <0 0x25640030 1 0>,
    <0 0x25640034 1 0>,
    <0 0x25640038 1 0>,
    <0 0x25640048 1 0>,
    <0 0x2564004c 1 0>,
    <0 0x25640050 1 0>,
    <0 0x25640054 1 0>,
    <0 0x25640058 1 0>,
    <0 0x25640060 1 0>,
    <0 0x250a9004 1 0>,
    <0 0x250a9010 1 0>,
    <0 0x250a9014 1 0>,
    <0 0x250a9018 1 0>,
    <0 0x250a9020 1 0>,
    <0 0x250a9024 1 0>,
    <0 0x250a9028 1 0>,
    <0 0x250a9030 1 0>,
    <0 0x250a9034 1 0>,
    <0 0x250a9038 1 0>,
    <0 0x250a9040 1 0>,
    <0 0x250a9044 1 0>,
    <0 0x250a9048 1 0>,
    <0 0x250a9050 1 0>,
    <0 0x250a9054 1 0>,
    <0 0x250a9058 1 0>,
    <0 0x250aa004 1 0>,
    <0 0x250aa010 1 0>,
    <0 0x250aa014 1 0>,
    <0 0x250aa018 1 0>,
    <0 0x250aa020 1 0>,
    <0 0x250aa024 1 0>,
    <0 0x250aa028 1 0>,
    <0 0x250aa030 1 0>,
    <0 0x250aa034 1 0>,
    <0 0x250aa038 1 0>,
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    <0 0x250b101c 1 0>,
    <0 0x250b201c 1 0>,
    <0 0x250b301c 1 0>,
    <0 0x250b401c 1 0>,
    <0 0x250b501c 1 0>,
    <0 0x250b601c 1 0>,
    <0 0x250b701c 1 0>,
    <0 0x250b801c 1 0>,
    <0 0x250b901c 1 0>,
    <0 0x250ba01c 1 0>,
    <0 0x250bb01c 1 0>,
    <0 0x250bc01c 1 0>,
    <0 0x250bd01c 1 0>,
    <0 0x250be01c 1 0>,
    <0 0x250bf01c 1 0>,
    <0 0x254a9004 1 0>,
    <0 0x254a9010 1 0>,
    <0 0x254a9014 1 0>,
    <0 0x254a9018 1 0>,
    <0 0x254a9020 1 0>,
    <0 0x254a9024 1 0>,
    <0 0x254a9028 1 0>,
    <0 0x254a9030 1 0>,
    <0 0x254a9034 1 0>,
    <0 0x254a9038 1 0>,
    <0 0x254a9040 1 0>,
    <0 0x254a9044 1 0>,
    <0 0x254a9048 1 0>,
    <0 0x254a9050 1 0>,
    <0 0x254a9054 1 0>,
    <0 0x254a9058 1 0>,
    <0 0x254aa004 1 0>,
    <0 0x254aa010 1 0>,
    <0 0x254aa014 1 0>,
    <0 0x254aa018 1 0>,
    <0 0x254aa020 1 0>,
    <0 0x254aa024 1 0>,
    <0 0x254aa028 1 0>,
    <0 0x254aa030 1 0>,
    <0 0x254aa034 1 0>,
    <0 0x254aa038 1 0>,
    <0 0x254aa040 1 0>,
    <0 0x254aa044 1 0>,
    <0 0x254aa048 1 0>,
    <0 0x254aa050 1 0>,
    <0 0x254aa054 1 0>,
    <0 0x254aa058 1 0>,
    <0 0x254b001c 1 0>,
    <0 0x254b101c 1 0>,
    <0 0x254b201c 1 0>,
    <0 0x254b301c 1 0>,
    <0 0x254b401c 1 0>,
    <0 0x254b501c 1 0>,
    <0 0x254b601c 1 0>,
    <0 0x254b701c 1 0>,
    <0 0x254b801c 1 0>,
    <0 0x254b901c 1 0>,
    <0 0x254ba01c 1 0>,
    <0 0x254bb01c 1 0>,
    <0 0x254bc01c 1 0>,
    <0 0x254bd01c 1 0>,
    <0 0x254be01c 1 0>,
    <0 0x254bf01c 1 0>,
    <0 0x252a9004 1 0>,
    <0 0x252a9010 1 0>,
    <0 0x252a9014 1 0>,
    <0 0x252a9018 1 0>,
    <0 0x252a9020 1 0>,
    <0 0x252a9024 1 0>,
    <0 0x252a9028 1 0>,
    <0 0x252a9030 1 0>,
    <0 0x252a9034 1 0>,
    <0 0x252a9038 1 0>,
    <0 0x252a9040 1 0>,
    <0 0x252a9044 1 0>,
    <0 0x252a9048 1 0>,
    <0 0x252a9050 1 0>,
    <0 0x252a9054 1 0>,
    <0 0x252a9058 1 0>,
    <0 0x252aa004 1 0>,
    <0 0x252aa010 1 0>,
    <0 0x252aa014 1 0>,
    <0 0x252aa018 1 0>,
    <0 0x252aa020 1 0>,
    <0 0x252aa024 1 0>,
    <0 0x252aa028 1 0>,
    <0 0x252aa030 1 0>,
    <0 0x252aa034 1 0>,
    <0 0x252aa038 1 0>,
    <0 0x252aa040 1 0>,
    <0 0x252aa044 1 0>,
    <0 0x252aa048 1 0>,
    <0 0x252aa050 1 0>,
    <0 0x252aa054 1 0>,
    <0 0x252aa058 1 0>,
    <0 0x252b001c 1 0>,
    <0 0x252b101c 1 0>,
    <0 0x252b201c 1 0>,
    <0 0x252b301c 1 0>,
    <0 0x252b401c 1 0>,
    <0 0x252b501c 1 0>,
    <0 0x252b601c 1 0>,
    <0 0x252b701c 1 0>,
    <0 0x252b801c 1 0>,
    <0 0x252b901c 1 0>,
    <0 0x252ba01c 1 0>,
    <0 0x252bb01c 1 0>,
    <0 0x252bc01c 1 0>,
    <0 0x252bd01c 1 0>,
    <0 0x252be01c 1 0>,
    <0 0x252bf01c 1 0>,
    <0 0x256a9004 1 0>,
    <0 0x256a9010 1 0>,
    <0 0x256a9014 1 0>,
    <0 0x256a9018 1 0>,
    <0 0x256a9020 1 0>,
    <0 0x256a9024 1 0>,
    <0 0x256a9028 1 0>,
    <0 0x256a9030 1 0>,
    <0 0x256a9034 1 0>,
    <0 0x256a9038 1 0>,
    <0 0x256a9040 1 0>,
    <0 0x256a9044 1 0>,
    <0 0x256a9048 1 0>,
    <0 0x256a9050 1 0>,
    <0 0x256a9054 1 0>,
    <0 0x256a9058 1 0>,
    <0 0x256aa004 1 0>,
    <0 0x256aa010 1 0>,
    <0 0x256aa014 1 0>,
    <0 0x256aa018 1 0>,
    <0 0x256aa020 1 0>,
    <0 0x256aa024 1 0>,
    <0 0x256aa028 1 0>,
    <0 0x256aa030 1 0>,
    <0 0x256aa034 1 0>,
    <0 0x256aa038 1 0>,
    <0 0x256aa040 1 0>,
    <0 0x256aa044 1 0>,
    <0 0x256aa048 1 0>,
    <0 0x256aa050 1 0>,
    <0 0x256aa054 1 0>,
    <0 0x256aa058 1 0>,
    <0 0x256b001c 1 0>,
    <0 0x256b101c 1 0>,
    <0 0x256b201c 1 0>,
    <0 0x256b301c 1 0>,
    <0 0x256b401c 1 0>,
    <0 0x256b501c 1 0>,
    <0 0x256b601c 1 0>,
    <0 0x256b701c 1 0>,
    <0 0x256b801c 1 0>,
    <0 0x256b901c 1 0>,
    <0 0x256ba01c 1 0>,
    <0 0x256bb01c 1 0>,
    <0 0x256bc01c 1 0>,
    <0 0x256bd01c 1 0>,
    <0 0x256be01c 1 0>,
    <0 0x256bf01c 1 0>,
    <0 0x32302028 1 0>,
    <0 0x320a4404 1 0>,
    <0 0x320a4408 1 0>,
    <0 0x323b0404 1 0>,
    <0 0x323b0408 1 0>;

  };

  link_list_1 {
   qcom,curr-link-list = <4>;
   qcom,data-sink = "sram";
   qcom,link-list = <0 0x240e0010 1 0>,
    <0 0x240e0020 8 0>,
    <0 0x240e0248 1 0>,
    <0 0x245f0010 1 0>,
    <0 0x245f0020 8 0>,
    <0 0x245f0248 1 0>,
    <0 0x247f0010 1 0>,
    <0 0x247f0020 8 0>,
    <0 0x247f0248 1 0>,
    <0 0x24330010 1 0>,
    <0 0x24330020 8 0>,
    <0 0x24330248 1 0>,
    <0 0x240e1018 1 0>,
    <0 0x240e1008 1 0>,
    <2 0x9 0 0>,
    <0 0x240e1010 2 0>,
    <2 0x1 0 0>,
    <0 0x245f2018 1 0>,
    <0 0x245f2008 1 0>,
    <2 0x3 0 0>,
    <0 0x245f2010 2 0>,
    <2 0x1 0 0>,
    <0 0x247f2018 1 0>,
    <0 0x247f2008 1 0>,
    <2 0x3 0 0>,
    <0 0x247f2010 2 0>,
    <2 0x1 0 0>,
    <0 0x24331018 1 0>,
    <0 0x24331008 1 0>,
    <2 0x8 0 0>,
    <0 0x24331010 2 0>,
    <2 0x1 0 0>,
    <0 0x6802028 1 0>,
    <0 0x68b0408 1 0>,
    <0 0x68b0404 1 0>,
    <0 0x7200408 1 0>,
    <0 0x7200404 1 0>,
    <0 0x01780010 1 0>,
    <0 0x01780020 8 0>,
    <0 0x01780248 1 0>,
    <0 0x01782018 1 0>,
    <0 0x01782008 1 0>,
    <2 0xc 0 0>,
    <0 0x01782010 2 0>,
    <2 0x1 0 0>,
    <0 0x01783018 1 0>,
    <0 0x01783008 1 0>,
    <2 0x11 0 0>,
    <0 0x01783010 2 0>,
    <2 0x1 0 0>,
    <0 0x01680010 1 0>,
    <0 0x01680020 8 0>,
    <0 0x01681048 1 0>,
    <0 0x01682018 1 0>,
    <0 0x01682008 1 0>,
    <2 0x6 0 0>,
    <0 0x01682010 2 0>,
    <2 0x1 0 0>,
    <0 0x016e0010 1 0>,
    <0 0x016e0020 8 0>,
    <0 0x016e0248 1 0>,
    <0 0x016e1018 1 0>,
    <0 0x016e1008 1 0>,
    <2 0x4 0 0>,
    <0 0x016e1010 2 0>,
    <2 0x1 0 0>,
    <0 0x016e1098 1 0>,
    <0 0x016e1088 1 0>,
    <2 0x3 0 0>,
    <0 0x016e1090 2 0>,
    <2 0x1 0 0>,
    <0 0x016e1118 1 0>,
    <0 0x016e1108 1 0>,
    <2 0x7 0 0>,
    <0 0x016e1110 2 0>,
    <2 0x1 0 0>,
    <0 0x01700010 1 0>,
    <0 0x01700020 8 0>,
    <0 0x01700248 1 0>,
    <0 0x01701018 1 0>,
    <0 0x01701008 1 0>,
    <2 0x4 0 0>,
    <0 0x01701010 2 0>,
    <2 0x1 0 0>,
    <0 0x01701098 1 0>,
    <0 0x01701088 1 0>,
    <2 0x2 0 0>,
    <0 0x01701090 2 0>,
    <2 0x1 0 0>,
    <0 0x01701118 1 0>,
    <0 0x01701108 1 0>,
    <2 0x3 0 0>,
    <0 0x01701110 2 0>,
    <2 0x1 0 0>,
    <0 0x01600010 1 0>,
    <0 0x01600020 8 0>,
    <0 0x01600248 2 0>,
    <0 0x01600258 1 0>,
    <0 0x01602018 1 0>,
    <0 0x01602008 1 0>,
    <2 0x7 0 0>,
    <0 0x01602010 2 0>,
    <2 0x1 0 0>,
    <0 0x01602098 1 0>,
    <0 0x01602088 1 0>,
    <2 0x2 0 0>,
    <0 0x01602090 2 0>,
    <2 0x1 0 0>,
    <0 0x01602118 1 0>,
    <0 0x01602108 1 0>,
    <2 0x3 0 0>,
    <0 0x01602110 2 0>,
    <2 0x1 0 0>,
    <0 0x01602198 1 0>,
    <0 0x01602188 1 0>,
    <2 0x3 0 0>,
    <0 0x01602190 2 0>,
    <2 0x1 0 0>,
    <0 0x01602218 1 0>,
    <0 0x01602208 1 0>,
    <2 0x2 0 0>,
    <0 0x01602210 2 0>,
    <2 0x1 0 0>,
    <0 0x01602298 1 0>,
    <0 0x01602288 1 0>,
    <2 0x2 0 0>,
    <0 0x01602290 2 0>,
    <2 0x1 0 0>,
    <0 0x01500010 1 0>,
    <0 0x01500020 8 0>,
    <0 0x01500248 1 0>,
    <0 0x01500448 1 0>,
    <0 0x01502018 1 0>,
    <0 0x01502008 1 0>,
    <2 0x7 0 0>,
    <0 0x01502010 2 0>,
    <2 0x1 0 0>,
    <0 0x01502098 1 0>,
    <0 0x01502088 1 0>,
    <2 0x7 0 0>,
    <0 0x01502090 2 0>,
    <2 0x1 0 0>,
    <0 0x17100104 29 0>,
    <0 0x17100204 29 0>,
    <0 0x17100384 29 0>,
    <0 0x178a0250 1 0>,
    <0 0x178a0254 1 0>,
    <0 0x178a025c 1 0>,
    <0 0xb281024 1 0>,
    <0 0xbde1034 1 0>,
    <0 0xb201020 2 0>,
    <0 0xb211020 2 0>,
    <0 0xb221020 2 0>,
    <0 0xb231020 2 0>,
    <0 0xb204520 1 0>,
    <0 0x17a00010 1 0>,
    <0 0x17a10010 1 0>,
    <0 0x17a20010 1 0>,
    <0 0x17a30010 1 0>,
    <0 0x17a00030 1 0>,
    <0 0x17a10030 1 0>,
    <0 0x17a20030 1 0>,
    <0 0x17a30030 1 0>,
    <0 0x17a00038 1 0>,
    <0 0x17a10038 1 0>,
    <0 0x17a20038 1 0>,
    <0 0x17a30038 1 0>,
    <0 0x17a00040 1 0>,
    <0 0x17a10040 1 0>,
    <0 0x17a20040 1 0>,
    <0 0x17a30040 1 0>,
    <0 0x17a00048 1 0>,
    <0 0x17a00400 3 0>,
    <0 0x17a10400 3 0>,
    <0 0x17a20400 3 0>,
    <0 0x17a30400 3 0>,
    <0 0xc230000 6 0>,
    <0 0x17d10200 256 0>,
    <0 0x17120000 1 0>,
    <0 0x17120008 1 0>,
    <0 0x17120010 1 0>,
    <0 0x17120018 1 0>,
    <0 0x17120020 1 0>,
    <0 0x17120028 1 0>,
    <0 0x17120040 1 0>,
    <0 0x17120048 1 0>,
    <0 0x17120050 1 0>,
    <0 0x17120058 1 0>,
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    <0 0x17120080 1 0>,
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    <0 0x17120090 1 0>,
    <0 0x17120098 1 0>,
    <0 0x171200a0 1 0>,
    <0 0x171200a8 1 0>,
    <0 0x171200c0 1 0>,
    <0 0x171200c8 1 0>,
    <0 0x171200d0 1 0>,
    <0 0x171200d8 1 0>,
    <0 0x171200e0 1 0>,
    <0 0x171200e8 1 0>,
    <0 0x17120100 1 0>,
    <0 0x17120108 1 0>,
    <0 0x17120110 1 0>,
    <0 0x17120118 1 0>,
    <0 0x17120120 1 0>,
    <0 0x17120128 1 0>,
    <0 0x17120140 1 0>,
    <0 0x17120148 1 0>,
    <0 0x17120150 1 0>,
    <0 0x17120158 1 0>,
    <0 0x17120160 1 0>,
    <0 0x17120168 1 0>,
    <0 0x17120180 1 0>,
    <0 0x17120188 1 0>,
    <0 0x17120190 1 0>,
    <0 0x17120198 1 0>,
    <0 0x171201a0 1 0>,
    <0 0x171201a8 1 0>,
    <0 0x171201c0 1 0>,
    <0 0x171201c8 1 0>,
    <0 0x171201d0 1 0>,
    <0 0x171201d8 1 0>,
    <0 0x171201e0 1 0>,
    <0 0x171201e8 1 0>,
    <0 0x17120200 1 0>,
    <0 0x17120208 1 0>,
    <0 0x17120210 1 0>,
    <0 0x17120218 1 0>,
    <0 0x17120220 1 0>,
    <0 0x17120228 1 0>,
    <0 0x17120240 1 0>,
    <0 0x17120248 1 0>,
    <0 0x17120250 1 0>,
    <0 0x17120258 1 0>,
    <0 0x17120260 1 0>,
    <0 0x17120268 1 0>,
    <0 0x17120280 1 0>,
    <0 0x17120288 1 0>,
    <0 0x17120290 1 0>,
    <0 0x17120298 1 0>,
    <0 0x171202a0 1 0>,
    <0 0x171202a8 1 0>,
    <0 0x171202c0 1 0>,
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    <0 0x171202d0 1 0>,
    <0 0x171202d8 1 0>,
    <0 0x171202e0 1 0>,
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    <0 0x17120300 1 0>,
    <0 0x17120308 1 0>,
    <0 0x17120310 1 0>,
    <0 0x17120318 1 0>,
    <0 0x17120320 1 0>,
    <0 0x17120328 1 0>,
    <0 0x17120340 1 0>,
    <0 0x17120348 1 0>,
    <0 0x17120350 1 0>,
    <0 0x17120358 1 0>,
    <0 0x17120360 1 0>,
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    <0 0x17120380 1 0>,
    <0 0x17120388 1 0>,
    <0 0x17120390 1 0>,
    <0 0x17120398 1 0>,
    <0 0x171203a0 1 0>,
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    <0 0x171203d0 1 0>,
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    <0 0x171203e0 1 0>,
    <0 0x171203e8 1 0>,
    <0 0x17120400 1 0>,
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    <0 0x17120410 1 0>,
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    <0 0x17120440 1 0>,
    <0 0x17120448 1 0>,
    <0 0x17120450 1 0>,
    <0 0x17120458 1 0>,
    <0 0x17120460 1 0>,
    <0 0x17120468 1 0>,
    <0 0x17120480 1 0>,
    <0 0x17120488 1 0>,
    <0 0x17120490 1 0>,
    <0 0x17120498 1 0>,
    <0 0x171204a0 1 0>,
    <0 0x171204a8 1 0>,
    <0 0x171204c0 1 0>,
    <0 0x171204c8 1 0>,
    <0 0x171204d0 1 0>,
    <0 0x171204d8 1 0>,
    <0 0x171204e0 1 0>,
    <0 0x171204e8 1 0>,
    <0 0x17120500 1 0>,
    <0 0x17120508 1 0>,
    <0 0x17120510 1 0>,
    <0 0x17120518 1 0>,
    <0 0x17120520 1 0>,
    <0 0x17120528 1 0>,
    <0 0x17120540 1 0>,
    <0 0x17120548 1 0>,
    <0 0x17120550 1 0>,
    <0 0x17120558 1 0>,
    <0 0x17120560 1 0>,
    <0 0x17120568 1 0>,
    <0 0x17120580 1 0>,
    <0 0x17120588 1 0>,
    <0 0x17120590 1 0>,
    <0 0x17120598 1 0>,
    <0 0x171205a0 1 0>,
    <0 0x171205a8 1 0>,
    <0 0x171205c0 1 0>,
    <0 0x171205c8 1 0>,
    <0 0x171205d0 1 0>,
    <0 0x171205d8 1 0>,
    <0 0x171205e0 1 0>,
    <0 0x171205e8 1 0>,
    <0 0x17120600 1 0>,
    <0 0x17120608 1 0>,
    <0 0x17120610 1 0>,
    <0 0x17120618 1 0>,
    <0 0x17120620 1 0>,
    <0 0x17120628 1 0>,
    <0 0x17120640 1 0>,
    <0 0x17120648 1 0>,
    <0 0x17120650 1 0>,
    <0 0x17120658 1 0>,
    <0 0x17120660 1 0>,
    <0 0x17120668 1 0>,
    <0 0x17120680 1 0>,
    <0 0x17120688 1 0>,
    <0 0x17120690 1 0>,
    <0 0x17120698 1 0>,
    <0 0x171206a0 1 0>,
    <0 0x171206a8 1 0>,
    <0 0x171206c0 1 0>,
    <0 0x171206c8 1 0>,
    <0 0x171206d0 1 0>,
    <0 0x171206d8 1 0>,
    <0 0x171206e0 1 0>,
    <0 0x171206e8 1 0>,
    <0 0x1712e000 1 0>,
    <0 0x110004 1 0>,
    <0 0x110008 1 0>,
    <0 0x11003c 1 0>,
    <0 0x110040 1 0>,
    <0 0x110044 1 0>,
    <0 0x11015c 1 0>,
    <0 0x110160 1 0>,
    <0 0x110464 1 0>,
    <0 0x110468 1 0>,
    <0 0x176040 1 0>;
  };
 };

 mem_dump {
  compatible = "qcom,mem-dump";
  memory-region = <&dump_mem>;

  c0_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x0>;
  };

  c100_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x1>;
  };

  c200_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x2>;
  };

  c300_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x3>;
  };

  c400_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x4>;
  };

  c500_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x5>;
  };

  c600_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x6>;
  };

  c700_context {
   qcom,dump-size = <0x800>;
   qcom,dump-id = <0x7>;
  };

  l1_icache0 {
   qcom,dump-size = <0x11100>;
   qcom,dump-id = <0x60>;
  };

  l1_icache100 {
   qcom,dump-size = <0x11100>;
   qcom,dump-id = <0x61>;
  };

  l1_icache200 {
   qcom,dump-size = <0x11100>;
   qcom,dump-id = <0x62>;
  };

  l1_icache300 {
   qcom,dump-size = <0x11100>;
   qcom,dump-id = <0x63>;
  };

  l1_icache400 {
   qcom,dump-size = <0x11100>;
   qcom,dump-id = <0x64>;
  };

  l1_icache500 {
   qcom,dump-size = <0x11100>;
   qcom,dump-id = <0x65>;
  };

  l1_icache600 {
   qcom,dump-size = <0x11100>;
   qcom,dump-id = <0x66>;
  };

  l1_icache700 {
   qcom,dump-size = <0x22100>;
   qcom,dump-id = <0x67>;
  };

  l1_dcache0 {
   qcom,dump-size = <0x9100>;
   qcom,dump-id = <0x80>;
  };

  l1_dcache100 {
   qcom,dump-size = <0x9100>;
   qcom,dump-id = <0x81>;
  };

  l1_dcache200 {
   qcom,dump-size = <0x9100>;
   qcom,dump-id = <0x82>;
  };

  l1_dcache300 {
   qcom,dump-size = <0xd100>;
   qcom,dump-id = <0x83>;
  };

  l1_dcache400 {
   qcom,dump-size = <0xd100>;
   qcom,dump-id = <0x84>;
  };

  l1_dcache500 {
   qcom,dump-size = <0xd100>;
   qcom,dump-id = <0x85>;
  };

  l1_dcache600 {
   qcom,dump-size = <0xd100>;
   qcom,dump-id = <0x86>;
  };

  l1_dcache700 {
   qcom,dump-size = <0x1a100>;
   qcom,dump-id = <0x87>;
  };

  l1_itlb500 {
   qcom,dump-size = <0x600>;
   qcom,dump-id = <0x25>;
  };

  l1_itlb600 {
   qcom,dump-size = <0x600>;
   qcom,dump-id = <0x26>;
  };

  l1_itlb700 {
   qcom,dump-size = <0x600>;
   qcom,dump-id = <0x27>;
  };

  l1_dtlb500 {
   qcom,dump-size = <0x600>;
   qcom,dump-id = <0x45>;
  };

  l1_dtlb600 {
   qcom,dump-size = <0x600>;
   qcom,dump-id = <0x46>;
  };

  l1_dtlb700 {
   qcom,dump-size = <0x600>;
   qcom,dump-id = <0x47>;
  };

  l2_cache0 {
   qcom,dump-size = <0x24100>;
   qcom,dump-id = <0xc0>;
  };

  l2_cache100 {
   qcom,dump-size = <0x24100>;
   qcom,dump-id = <0xc1>;
  };

  l2_cache200 {
   qcom,dump-size = <0x24100>;
   qcom,dump-id = <0xc2>;
  };

  l2_cache300 {
   qcom,dump-size = <0xd0100>;
   qcom,dump-id = <0xc3>;
  };

  l2_cache400 {
   qcom,dump-size = <0xd0100>;
   qcom,dump-id = <0xc4>;
  };

  l2_cache500 {
   qcom,dump-size = <0x68100>;
   qcom,dump-id = <0xc5>;
  };

  l2_cache600 {
   qcom,dump-size = <0x68100>;
   qcom,dump-id = <0xc6>;
  };

  l2_cache700 {
   qcom,dump-size = <0x1a0100>;
   qcom,dump-id = <0xc7>;
  };

  l2_tlb0 {
   qcom,dump-size = <0xf700>;
   qcom,dump-id = <0x120>;
  };

  l2_tlb100 {
   qcom,dump-size = <0xf700>;
   qcom,dump-id = <0x121>;
  };

  l2_tlb200 {
   qcom,dump-size = <0xf700>;
   qcom,dump-id = <0x122>;
  };

  l2_tlb500 {
   qcom,dump-size = <0x7900>;
   qcom,dump-id = <0x125>;
  };

  l2_tlb600 {
   qcom,dump-size = <0x7900>;
   qcom,dump-id = <0x126>;
  };

  l2_tlb700 {
   qcom,dump-size = <0xa900>;
   qcom,dump-id = <0x127>;
  };

  l1dcdirty0 {
   qcom,dump-size = <0x1100>;
   qcom,dump-id = <0x170>;
  };

  l1dcdirty100 {
   qcom,dump-size = <0x1100>;
   qcom,dump-id = <0x171>;
  };

  l1dcdirty200 {
   qcom,dump-size = <0x1100>;
   qcom,dump-id = <0x172>;
  };

  l1dcmte0 {
   qcom,dump-size = <0x1100>;
   qcom,dump-id = <0x180>;
  };

  l1dcmte100 {
   qcom,dump-size = <0x1100>;
   qcom,dump-id = <0x181>;
  };

  l1dcmte200 {
   qcom,dump-size = <0x1100>;
   qcom,dump-id = <0x182>;
  };

  l2dcmte0 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x190>;
  };

  l2dcmte100 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x191>;
  };

  l2dcmte200 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x192>;
  };

  l0mopca500 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x1a5>;
  };

  l0mopca600 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x1a6>;
  };

  l0mopca700 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x1a7>;
  };

  l1btb500 {
   qcom,dump-size = <0x10100>;
   qcom,dump-id = <0x1b5>;
  };

  l1btb600 {
   qcom,dump-size = <0x10100>;
   qcom,dump-id = <0x1b6>;
  };

  l1ghb500 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x1c5>;
  };

  l1ghb600 {
   qcom,dump-size = <0x4100>;
   qcom,dump-id = <0x1c6>;
  };

  l1bim500 {
   qcom,dump-size = <0x2100>;
   qcom,dump-id = <0x1d5>;
  };

  l1bim600 {
   qcom,dump-size = <0x2100>;
   qcom,dump-id = <0x1d6>;
  };

  l2victim500 {
   qcom,dump-size = <0x2100>;
   qcom,dump-id = <0x1e5>;
  };

  l2victim600 {
   qcom,dump-size = <0x2100>;
   qcom,dump-id = <0x1e6>;
  };

  l2victim700 {
   qcom,dump-size = <0x2100>;
   qcom,dump-id = <0x1e7>;
  };

  l2tldtcsp300 {
   qcom,dump-size = <0x7900>;
   qcom,dump-id = <0x203>;
  };

  l2tldtcsp400 {
   qcom,dump-size = <0x7900>;
   qcom,dump-id = <0x204>;
  };

  l2tldtcmp300 {
   qcom,dump-size = <0x1300>;
   qcom,dump-id = <0x213>;
  };

  l2tldtcmp400 {
   qcom,dump-size = <0x1300>;
   qcom,dump-id = <0x214>;
  };

  cpuss_reg {
   qcom,dump-size = <0x30000>;
   qcom,dump-id = <0xef>;
  };

  gemnoc {
   qcom,dump-size = <0x100000>;
   qcom,dump-id = <0x162>;
  };

  rpmh {
   qcom,dump-size = <0x2000000>;
   qcom,dump-id = <0xec>;
  };

  rpm_sw {
   qcom,dump-size = <0x28000>;
   qcom,dump-id = <0xea>;
  };

  pmic {
   qcom,dump-size = <0x200000>;
   qcom,dump-id = <0xe4>;
  };

  fcm {
   qcom,dump-size = <0x8400>;
   qcom,dump-id = <0xee>;
  };

  etf_swao {
   qcom,dump-size = <0x10000>;
   qcom,dump-id = <0xf1>;
  };

  etr_reg {
   qcom,dump-size = <0x1000>;
   qcom,dump-id = <0x100>;
  };

  etfswao_reg {
   qcom,dump-size = <0x1000>;
   qcom,dump-id = <0x102>;
  };

  etr1_reg {
   qcom,dump-size = <0x1000>;
   qcom,dump-id = <0x105>;
  };

  misc_data {
   qcom,dump-size = <0x1000>;
   qcom,dump-id = <0xe8>;
  };

  etf_slpi {
   qcom,dump-size = <0x4000>;
   qcom,dump-id = <0xf3>;
  };

  etfslpi_reg {
   qcom,dump-size = <0x1000>;
   qcom,dump-id = <0x103>;
  };

  etf_lpass {
   qcom,dump-size = <0x4000>;
   qcom,dump-id = <0xf4>;
  };

  etflpass_reg {
   qcom,dump-size = <0x1000>;
   qcom,dump-id = <0x104>;
  };

  llcc1dc {
   qcom,dump-size = <0x171000>;
   qcom,dump-id = <0x140>;
  };

  llcc2dc {
   qcom,dump-size = <0x171000>;
   qcom,dump-id = <0x141>;
  };

  llcc3dc {
   qcom,dump-size = <0x171000>;
   qcom,dump-id = <0x142>;
  };

  llcc4dc {
   qcom,dump-size = <0x171000>;
   qcom,dump-id = <0x143>;
  };

  osm_reg {
   qcom,dump-size = <0x400>;
   qcom,dump-id = <0x163>;
  };

  pcu_reg {
   qcom,dump-size = <0x400>;
   qcom,dump-id = <0x164>;
  };

  fsm_data {
   qcom,dump-size = <0x400>;
   qcom,dump-id = <0x165>;
  };

  spr_cpu0 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f0>;
  };

  spr_cpu1 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f1>;
  };

  spr_cpu2 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f2>;
  };

  spr_cpu3 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f3>;
  };

  spr_cpu4 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f4>;
  };

  spr_cpu5 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f5>;
  };

  spr_cpu6 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f6>;
  };

  spr_cpu7 {
   qcom,dump-size = <0x2000>;
   qcom,dump-id = <0x1f7>;
  };
 };
};
# 3666 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-dma-heaps.dtsi" 1
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h" 1
# 2 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-dma-heaps.dtsi" 2

&soc {
 qcom,dma-heaps {
  compatible = "qcom,dma-heaps";

  qcom,qseecom {
   qcom,dma-heap-name = "qcom,qseecom";
   qcom,dma-heap-type = <2>;
   memory-region = <&qseecom_mem>;
  };

  qcom,qseecom_ta {
   qcom,dma-heap-name = "qcom,qseecom-ta";
   qcom,dma-heap-type = <2>;
   memory-region = <&qseecom_ta_mem>;
  };

  qcom,display {
   qcom,dma-heap-name = "qcom,display";
   qcom,dma-heap-type = <2>;
   qcom,max-align = <9>;
   memory-region = <&non_secure_display_memory>;
  };

  qcom,demura {
   qcom,dma-heap-name = "qcom,demura";
   qcom,dma-heap-type = <2>;
   qcom,max-align = <9>;
   memory-region = <&demura_heap_memory>;
  };

  qcom,secure_cdsp {
   qcom,dma-heap-name = "qcom,cma-secure-cdsp";
   qcom,dma-heap-type = <2>;
   memory-region = <&cdsp_secure_heap>;
  };

  qcom,user_contig {
   qcom,dma-heap-name = "qcom,user-contig";
   qcom,dma-heap-type = <2>;
   memory-region = <&user_contig_mem>;
  };

  qcom,sp_hlos {
   qcom,dma-heap-name = "qcom,sp-hlos";
   qcom,dma-heap-type = <2>;
   memory-region = <&sp_mem>;
  };

  qcom,secure_sp_modem {
   qcom,dma-heap-name = "qcom,secure-sp-modem";
   qcom,dma-heap-type = <0>;
   memory-region = <&spu_modem_shared_mem>;
   qcom,token = <0x10800000>;
  };

  qcom,secure_sp_tz {
   qcom,dma-heap-name = "qcom,secure-sp-tz";
   qcom,dma-heap-type = <0>;
   memory-region = <&spu_tz_shared_mem>;
   qcom,token = <0x01000000>;
  };

  qcom,audio_ml {
   qcom,dma-heap-name = "qcom,audio-ml";
   qcom,dma-heap-type = <2>;
   memory-region = <&audio_cma_mem>;
  };

  qcom,adsp {
   qcom,dma-heap-name = "qcom,adsp";
   qcom,dma-heap-type = <2>;
   memory-region = <&sdsp_mem>;
  };
 };
};
# 3667 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-regulators.dtsi" 1


&apps_rsc_drv2 {
 rpmh-regulator-lcxlvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "lcx.lvl";

  VDD_LPI_CX_LEVEL: S4D_LEVEL:
  pm_v6d_s4_level: regulator-pm-v6d-s4-level {
   regulator-name = "pm_v6d_s4_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };
 };

 rpmh-regulator-gfxlvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "gfx.lvl";

  VDD_GFX_LEVEL: S5D_LEVEL:
  pm_v6d_s5_level: regulator-pm-v6d-s5-level {
   regulator-name = "pm_v6d_s5_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };
 };

 rpmh-regulator-lmxlvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "lmx.lvl";

  VDD_LPI_MX_LEVEL: L2D_LEVEL:
  pm_v6d_l2_level: regulator-pm-v6d-l2-level {
   regulator-name = "pm_v6d_l2_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };
 };

 rpmh-regulator-cxlvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "cx.lvl";
  proxy-supply = <&VDD_CX_LEVEL>;

  VDD_CX_LEVEL: S6E_LEVEL:
  pm_v6e_s6_level: regulator-pm-v6e-s6-level {
   regulator-name = "pm_v6e_s6_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <384>;
   qcom,proxy-consumer-enable;
   qcom,proxy-consumer-voltage =
    <384
     65535>;
  };

  VDD_CX_LEVEL_AO: S6E_LEVEL_AO:
  pm_v6e_s6_level_ao: regulator-pm-v6e-s6-level-ao {
   regulator-name = "pm_v6e_s6_level_ao";
   qcom,set = <1>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };

  VDD_CX_MMCX_SUPPLY_LEVEL: regulator-pm-v6e-s6-mmcx-sup-level {
   regulator-name = "pm_v6e_s6_mmcx_sup_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <48>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <48>;
  };
 };

 rpmh-regulator-mmcxlvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "mmcx.lvl";
  proxy-supply = <&VDD_MMCX_LEVEL>;

  VDD_MMCX_LEVEL: VDD_MM_LEVEL: S1E_LEVEL:
  pm_v6e_s1_level: regulator-pm-v6e-s1-level {
   regulator-name = "pm_v6e_s1_level";
   qcom,set = <3>;
   pm_v6e_s1_level-parent-supply =
    <&VDD_CX_MMCX_SUPPLY_LEVEL>;
   regulator-min-microvolt =
    <64>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <384>;
   qcom,proxy-consumer-enable;
   qcom,proxy-consumer-voltage =
    <384
     65535>;
  };

  VDD_MMCX_LEVEL_AO: VDD_MM_LEVEL_AO: S1E_LEVEL_AO:
  pm_v6e_s1_level_ao: regulator-pm-v6e-s1-level-ao {
   regulator-name = "pm_v6e_s1_level_ao";
   qcom,set = <1>;
   regulator-min-microvolt =
    <64>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <64>;
  };

  regulator-pm-v6e-s1-level-so {
   regulator-name = "pm_v6e_s1_level_so";
   qcom,set = <2>;
   regulator-min-microvolt =
    <64>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <64>;
  };
 };

 rpmh-regulator-mxlvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "mx.lvl";
  proxy-supply = <&VDD_MXA_LEVEL>;

  VDD_MXA_LEVEL: S3E_LEVEL:
  pm_v6e_s3_level: regulator-pm-v6e-s3-level {
   regulator-name = "pm_v6e_s3_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <384>;
   qcom,proxy-consumer-enable;
   qcom,proxy-consumer-voltage =
    <384
     65535>;
  };

  VDD_MXA_LEVEL_AO: S3E_LEVEL_AO:
  pm_v6e_s3_level_ao: regulator-pm-v6e-s3-level-ao {
   regulator-name = "pm_v6e_s3_level_ao";
   qcom,set = <1>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };
 };

 rpmh-regulator-nsplvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "nsp.lvl";

  VDD_NSP_LEVEL: S1F_LEVEL:
  pm_v8_s1_level: regulator-pm-v8-s1-level {
   regulator-name = "pm_v8_s1_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };
 };

 rpmh-regulator-ebilvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "ebi.lvl";

  VDD_EBI_LEVEL: S3F_LEVEL:
  pm_v8_s3_level: regulator-pm-v8-s3-level {
   regulator-name = "pm_v8_s3_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };
 };

 rpmh-regulator-mxclvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "mxc.lvl";
  proxy-supply = <&VDD_MXC_LEVEL>;

  VDD_MXC_LEVEL: S5F_LEVEL:
  pm_v8_s5_level: regulator-pm-v8-s5-level {
   regulator-name = "pm_v8_s5_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <384>;
   qcom,proxy-consumer-enable;
   qcom,proxy-consumer-voltage =
    <384
     65535>;
  };

  VDD_MXC_LEVEL_AO: S5F_LEVEL_AO:
  pm_v8_s5_level_ao: regulator-pm-v8-s5-level-ao {
   regulator-name = "pm_v8_s5_level_ao";
   qcom,set = <1>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };

  VDD_MXC_MMCX_VOTER_LEVEL: VDD_MXC_MM_VOTER_LEVEL:
  VDD_MM_MXC_VOTER_LEVEL:
  regulator-pm-v8-s5-mmcx-voter-level {
   regulator-name = "pm_v8_s5_mmcx_voter_level";
   pm_v8_s5_mmcx_voter_level-parent-supply =
    <&VDD_MMCX_LEVEL>;
   qcom,set = <3>;
   regulator-min-microvolt =
    <48>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <48>;
  };

  VDD_MXC_GFX_VOTER_LEVEL: VDD_GFX_MXC_VOTER_LEVEL:
  regulator-pm-v8-s5-gfx-voter-level {
   regulator-name = "pm_v8_s5_gfx_voter_level";
   pm_v8_s5_gfx_voter_level-parent-supply =
    <&VDD_GFX_LEVEL>;
   qcom,set = <3>;
   regulator-min-microvolt =
    <48>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <48>;
  };
 };

 rpmh-regulator-msslvl {
  compatible = "qcom,rpmh-arc-regulator";
  qcom,resource-name = "mss.lvl";

  VDD_MODEM_LEVEL: S7F_LEVEL:
  pm_v8_s7_level: regulator-pm-v8-s7-level {
   regulator-name = "pm_v8_s7_level";
   qcom,set = <3>;
   regulator-min-microvolt =
    <16>;
   regulator-max-microvolt =
    <65535>;
   qcom,init-voltage-level =
    <16>;
  };
 };

 rpmh-regulator-ldob1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1B: pm_humu_l1: regulator-pm-humu-l1 {
   regulator-name = "pm_humu_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <1800000>;
   qcom,init-voltage = <1800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob2";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L2B: pm_humu_l2: regulator-pm-humu-l2 {
   regulator-name = "pm_humu_l2";
   qcom,set = <3>;
   regulator-min-microvolt = <3008000>;
   regulator-max-microvolt = <3008000>;
   qcom,init-voltage = <3008000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob5 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob5";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L5B: pm_humu_l5: regulator-pm-humu-l5 {
   regulator-name = "pm_humu_l5";
   qcom,set = <3>;
   regulator-min-microvolt = <3104000>;
   regulator-max-microvolt = <3104000>;
   qcom,init-voltage = <3104000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob6 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob6";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L6B: pm_humu_l6: regulator-pm-humu-l6 {
   regulator-name = "pm_humu_l6";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <3008000>;
   qcom,init-voltage = <1800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob7 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob7";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L7B: pm_humu_l7: regulator-pm-humu-l7 {
   regulator-name = "pm_humu_l7";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <3008000>;
   qcom,init-voltage = <1800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob8 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob8";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L8B: pm_humu_l8: regulator-pm-humu-l8 {
   regulator-name = "pm_humu_l8";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <3008000>;
   qcom,init-voltage = <1800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob9 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob9";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L9B: pm_humu_l9: regulator-pm-humu-l9 {
   regulator-name = "pm_humu_l9";
   qcom,set = <3>;
   regulator-min-microvolt = <2960000>;
   regulator-max-microvolt = <3008000>;
   qcom,init-voltage = <2960000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob10 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob10";
  qcom,regulator-type = "pmic5-ldo";

  L10B: pm_humu_l10: regulator-pm-humu-l10 {
   regulator-name = "pm_humu_l10";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <1800000>;
   qcom,init-voltage = <1800000>;
  };
 };

 rpmh-regulator-ldob11 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob11";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;
  proxy-supply = <&L11B>;

  L11B: pm_humu_l11: regulator-pm-humu-l11 {
   regulator-name = "pm_humu_l11";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1504000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
   qcom,proxy-consumer-enable;
  };
 };

 rpmh-regulator-ldob12 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob12";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;
  proxy-supply = <&L12B>;

  L12B: pm_humu_l12: regulator-pm-humu-l12 {
   regulator-name = "pm_humu_l12";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <1800000>;
   qcom,init-voltage = <1800000>;
   qcom,init-mode = <4>;
   qcom,proxy-consumer-enable;
  };
 };

 rpmh-regulator-ldob13 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob13";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;
  proxy-supply = <&L13B>;

  L13B: pm_humu_l13: regulator-pm-humu-l13 {
   regulator-name = "pm_humu_l13";
   qcom,set = <3>;
   regulator-min-microvolt = <3000000>;
   regulator-max-microvolt = <3000000>;
   qcom,init-voltage = <3000000>;
   qcom,init-mode = <4>;
   qcom,proxy-consumer-enable;
  };
 };

 rpmh-regulator-ldob14 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob14";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L14B: pm_humu_l14: regulator-pm-humu-l14 {
   regulator-name = "pm_humu_l14";
   qcom,set = <3>;
   regulator-min-microvolt = <3200000>;
   regulator-max-microvolt = <3200000>;
   qcom,init-voltage = <3200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob15 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob15";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L15B: pm_humu_l15: regulator-pm-humu-l15 {
   regulator-name = "pm_humu_l15";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <1800000>;
   qcom,init-voltage = <1800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob16 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob16";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L16B: pm_humu_l16: regulator-pm-humu-l16 {
   regulator-name = "pm_humu_l16";
   qcom,set = <3>;
   regulator-min-microvolt = <2800000>;
   regulator-max-microvolt = <2800000>;
   qcom,init-voltage = <2800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldob17 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldob17";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 10000>;

  L17B: pm_humu_l17: regulator-pm-humu-l17 {
   regulator-name = "pm_humu_l17";
   qcom,set = <3>;
   regulator-min-microvolt = <2504000>;
   regulator-max-microvolt = <2504000>;
   qcom,init-voltage = <2504000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-bobb1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "bobb1";

  BOB1: pm_humu_bob1: regulator-pm-humu-bob1 {
   regulator-name = "pm_humu_bob1";
   qcom,set = <3>;
   regulator-min-microvolt = <3008000>;
   regulator-max-microvolt = <3960000>;
   qcom,init-voltage = <3296000>;
  };
 };

 rpmh-regulator-bobb2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "bobb2";

  BOB2: pm_humu_bob2: regulator-pm-humu-bob2 {
   regulator-name = "pm_humu_bob2";
   qcom,set = <3>;
   regulator-min-microvolt = <2704000>;
   regulator-max-microvolt = <3008000>;
   qcom,init-voltage = <2720000>;
  };
 };

 rpmh-regulator-ldoc1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldoc1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1C: pm_v6c_l1: regulator-pm-v6c-l1 {
   regulator-name = "pm_v6c_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldoc3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldoc3";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L3C: pm_v6c_l3: regulator-pm-v6c-l3 {
   regulator-name = "pm_v6c_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <912000>;
   qcom,init-voltage = <912000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldod1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldod1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1D: pm_v6d_l1: regulator-pm-v6d-l1 {
   regulator-name = "pm_v6d_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <920000>;
   qcom,init-voltage = <880000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-smpe4 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpe4";

  S4E: pm_v6e_s4: regulator-pm-v6e-s4 {
   regulator-name = "pm_v6e_s4";
   qcom,set = <3>;
   regulator-min-microvolt = <904000>;
   regulator-max-microvolt = <984000>;
   qcom,init-voltage = <952000>;
  };
 };

 rpmh-regulator-smpe5 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpe5";

  S5E: pm_v6e_s5: regulator-pm-v6e-s5 {
   regulator-name = "pm_v6e_s5";
   qcom,set = <3>;
   regulator-min-microvolt = <1010000>;
   regulator-max-microvolt = <1120000>;
   qcom,init-voltage = <1080000>;
  };
 };

 rpmh-regulator-ldoe1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldoe1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;
  proxy-supply = <&L1E>;

  L1E: pm_v6e_l1: regulator-pm-v6e-l1 {
   regulator-name = "pm_v6e_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <912000>;
   qcom,init-voltage = <880000>;
   qcom,init-mode = <4>;
   qcom,proxy-consumer-enable;
  };

  L1E_AO: pm_v6e_l1_ao: regulator-pm-v6e-l1-ao {
   regulator-name = "pm_v6e_l1_ao";
   qcom,set = <1>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <880000>;
   qcom,init-voltage = <880000>;
   qcom,init-mode = <2>;
  };

  regulator-pm-v6e-l1-so {
   regulator-name = "pm_v6e_l1_so";
   qcom,set = <2>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <880000>;
   qcom,init-voltage = <880000>;
   qcom,init-mode = <2>;
   qcom,init-enable = <0>;
  };
 };

 rpmh-regulator-ldoe2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldoe2";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L2E: pm_v6e_l2: regulator-pm-v6e-l2 {
   regulator-name = "pm_v6e_l2";
   qcom,set = <3>;
   regulator-min-microvolt = <870000>;
   regulator-max-microvolt = <970000>;
   qcom,init-voltage = <904000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldoe3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldoe3";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;
  proxy-supply = <&L3E>;

  L3E: pm_v6e_l3: regulator-pm-v6e-l3 {
   regulator-name = "pm_v6e_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
   qcom,proxy-consumer-enable;
  };

  L3E_AO: pm_v6e_l3_ao: regulator-pm-v6e-l3-ao {
   regulator-name = "pm_v6e_l3_ao";
   qcom,set = <1>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <2>;
  };

  regulator-pm-v6e-l3-so {
   regulator-name = "pm_v6e_l3_so";
   qcom,set = <2>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <2>;
   qcom,init-enable = <0>;
  };
 };

 rpmh-regulator-smpf4 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpf4";

  S4F: pm_v8_s4: regulator-pm-v8-s4 {
   regulator-name = "pm_v8_s4";
   qcom,set = <3>;
   regulator-min-microvolt = <300000>;
   regulator-max-microvolt = <700000>;
   qcom,init-voltage = <500000>;
  };
 };

 rpmh-regulator-ldof1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldof1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1F: pm_v8_l1: regulator-pm-v8-l1 {
   regulator-name = "pm_v8_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <912000>;
   qcom,init-voltage = <912000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldof2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldof2";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L2F: pm_v8_l2: regulator-pm-v8-l2 {
   regulator-name = "pm_v8_l2";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <912000>;
   qcom,init-voltage = <880000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldof3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldof3";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L3F: pm_v8_l3: regulator-pm-v8-l3 {
   regulator-name = "pm_v8_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <912000>;
   qcom,init-voltage = <912000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-smpg1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpg1";

  S1G: pm_v6g_s1: regulator-pm-v6g-s1 {
   regulator-name = "pm_v6g_s1";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1300000>;
   qcom,init-voltage = <1256000>;
  };
 };

 rpmh-regulator-smpg2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpg2";

  S2G: pm_v6g_s2: regulator-pm-v6g-s2 {
   regulator-name = "pm_v6g_s2";
   qcom,set = <3>;
   regulator-min-microvolt = <500000>;
   regulator-max-microvolt = <1036000>;
   qcom,init-voltage = <852000>;
  };
 };

 rpmh-regulator-smpg3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpg3";

  S3G: pm_v6g_s3: regulator-pm-v6g-s3 {
   regulator-name = "pm_v6g_s3";
   qcom,set = <3>;
   regulator-min-microvolt = <300000>;
   regulator-max-microvolt = <1004000>;
   qcom,init-voltage = <752000>;
  };
 };

 rpmh-regulator-smpg4 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpg4";
  qcom,regulator-type = "pmic5-ftsmps";
  qcom,supported-modes =
   <1
   4>;
  qcom,mode-threshold-currents = <0 200000>;

  S4G: pm_v6g_s4: regulator-pm-v6g-s4 {
   regulator-name = "pm_v6g_s4";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1352000>;
   qcom,init-voltage = <1304000>;
   qcom,init-mode = <1>;
  };
 };

 rpmh-regulator-smpg5 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpg5";

  S5G: pm_v6g_s5: regulator-pm-v6g-s5 {
   regulator-name = "pm_v6g_s5";
   qcom,set = <3>;
   regulator-min-microvolt = <500000>;
   regulator-max-microvolt = <1004000>;
   qcom,init-voltage = <852000>;
  };
 };

 rpmh-regulator-smpg6 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "smpg6";

  S6G: pm_v6g_s6: regulator-pm-v6g-s6 {
   regulator-name = "pm_v6g_s6";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <2000000>;
   qcom,init-voltage = <1856000>;
  };
 };

 rpmh-regulator-ldog1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldog1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1G: pm_v6g_l1: regulator-pm-v6g-l1 {
   regulator-name = "pm_v6g_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <1144000>;
   regulator-max-microvolt = <1256000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldog2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldog2";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L2G: pm_v6g_l2: regulator-pm-v6g-l2 {
   regulator-name = "pm_v6g_l2";
   qcom,set = <3>;
   regulator-min-microvolt = <1100000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldog3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldog3";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L3G: pm_v6g_l3: regulator-pm-v6g-l3 {
   regulator-name = "pm_v6g_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldok1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldok1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1K: pmr_nalojrk_l1: regulator-pmr-nalojrk-l1 {
   regulator-name = "pmr_nalojrk_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <400000>;
   regulator-max-microvolt = <900000>;
   qcom,init-voltage = <800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldok2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldok2";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L2K: pmr_nalojrk_l2: regulator-pmr-nalojrk-l2 {
   regulator-name = "pmr_nalojrk_l2";
   qcom,set = <3>;
   regulator-min-microvolt = <500000>;
   regulator-max-microvolt = <900000>;
   qcom,init-voltage = <800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldok3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldok3";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L3K: pmr_nalojrk_l3: regulator-pmr-nalojrk-l3 {
   regulator-name = "pmr_nalojrk_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <912000>;
   qcom,init-voltage = <880000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldok4 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldok4";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L4K: pmr_nalojrk_l4: regulator-pmr-nalojrk-l4 {
   regulator-name = "pmr_nalojrk_l4";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldok5 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldok5";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L5K: pmr_nalojrk_l5: regulator-pmr-nalojrk-l5 {
   regulator-name = "pmr_nalojrk_l5";
   qcom,set = <3>;
   regulator-min-microvolt = <800000>;
   regulator-max-microvolt = <800000>;
   qcom,init-voltage = <800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldok6 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldok6";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L6K: pmr_nalojrk_l6: regulator-pmr-nalojrk-l6 {
   regulator-name = "pmr_nalojrk_l6";
   qcom,set = <3>;
   regulator-min-microvolt = <1776000>;
   regulator-max-microvolt = <1900000>;
   qcom,init-voltage = <1776000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldok7 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldok7";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L7K: pmr_nalojrk_l7: regulator-pmr-nalojrk-l7 {
   regulator-name = "pmr_nalojrk_l7";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldol3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldol3";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L3L: pmr_nalojrl_l3: regulator-pmr-nalojrl-l3 {
   regulator-name = "pmr_nalojrl_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <880000>;
   regulator-max-microvolt = <912000>;
   qcom,init-voltage = <912000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldol4 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldol4";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L4L: pmr_nalojrl_l4: regulator-pmr-nalojrl-l4 {
   regulator-name = "pmr_nalojrl_l4";
   qcom,set = <3>;
   regulator-min-microvolt = <1200000>;
   regulator-max-microvolt = <1200000>;
   qcom,init-voltage = <1200000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldol5 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldol5";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L5L: pmr_nalojrl_l5: regulator-pmr-nalojrl-l5 {
   regulator-name = "pmr_nalojrl_l5";
   qcom,set = <3>;
   regulator-min-microvolt = <800000>;
   regulator-max-microvolt = <800000>;
   qcom,init-voltage = <800000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldol6 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldol6";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L6L: pmr_nalojrl_l6: regulator-pmr-nalojrl-l6 {
   regulator-name = "pmr_nalojrl_l6";
   qcom,set = <3>;
   regulator-min-microvolt = <1776000>;
   regulator-max-microvolt = <1776000>;
   qcom,init-voltage = <1776000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldol7 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldol7";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L7L: pmr_nalojrl_l7: regulator-pmr-nalojrl-l7 {
   regulator-name = "pmr_nalojrl_l7";
   qcom,set = <3>;
   regulator-min-microvolt = <500000>;
   regulator-max-microvolt = <900000>;
   qcom,init-voltage = <752000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldom1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldom1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1M: pm8010m_l1: regulator-pm8010m-l1 {
   regulator-name = "pm8010m_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <1056000>;
   regulator-max-microvolt = <1056000>;
   qcom,init-voltage = <1056000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldom2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldom2";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L2M: pm8010m_l2: regulator-pm8010m-l2 {
   regulator-name = "pm8010m_l2";
   qcom,set = <3>;
   regulator-min-microvolt = <1056000>;
   regulator-max-microvolt = <1056000>;
   qcom,init-voltage = <1056000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldom3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldom3";

  L3M: pm8010m_l3: regulator-pm8010m-l3 {
   regulator-name = "pm8010m_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <2800000>;
   regulator-max-microvolt = <2800000>;
   qcom,init-voltage = <2800000>;
  };
 };

 rpmh-regulator-ldom4 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldom4";

  L4M: pm8010m_l4: regulator-pm8010m-l4 {
   regulator-name = "pm8010m_l4";
   qcom,set = <3>;
   regulator-min-microvolt = <2800000>;
   regulator-max-microvolt = <2800000>;
   qcom,init-voltage = <2800000>;
  };
 };

 rpmh-regulator-ldom5 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldom5";

  L5M: pm8010m_l5: regulator-pm8010m-l5 {
   regulator-name = "pm8010m_l5";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <1800000>;
   qcom,init-voltage = <1800000>;
  };
 };

 rpmh-regulator-ldom6 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldom6";

  L6M: pm8010m_l6: regulator-pm8010m-l6 {
   regulator-name = "pm8010m_l6";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <1800000>;
   qcom,init-voltage = <1800000>;
  };
 };

 rpmh-regulator-ldom7 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldom7";

  L7M: pm8010m_l7: regulator-pm8010m-l7 {
   regulator-name = "pm8010m_l7";
   qcom,set = <3>;
   regulator-min-microvolt = <2800000>;
   regulator-max-microvolt = <2904000>;
   qcom,init-voltage = <2800000>;
  };
 };

 rpmh-regulator-ldon1 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldon1";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L1N: pm8010n_l1: regulator-pm8010n-l1 {
   regulator-name = "pm8010n_l1";
   qcom,set = <3>;
   regulator-min-microvolt = <1104000>;
   regulator-max-microvolt = <1104000>;
   qcom,init-voltage = <1104000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldon2 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldon2";
  qcom,regulator-type = "pmic5-ldo";
  qcom,supported-modes =
   <2
    4>;
  qcom,mode-threshold-currents = <0 30000>;

  L2N: pm8010n_l2: regulator-pm8010n-l2 {
   regulator-name = "pm8010n_l2";
   qcom,set = <3>;
   regulator-min-microvolt = <1104000>;
   regulator-max-microvolt = <1104000>;
   qcom,init-voltage = <1104000>;
   qcom,init-mode = <4>;
  };
 };

 rpmh-regulator-ldon3 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldon3";

  L3N: pm8010n_l3: regulator-pm8010n-l3 {
   regulator-name = "pm8010n_l3";
   qcom,set = <3>;
   regulator-min-microvolt = <2800000>;
   regulator-max-microvolt = <2800000>;
   qcom,init-voltage = <2800000>;
  };
 };

 rpmh-regulator-ldon4 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldon4";

  L4N: pm8010n_l4: regulator-pm8010n-l4 {
   regulator-name = "pm8010n_l4";
   qcom,set = <3>;
   regulator-min-microvolt = <2800000>;
   regulator-max-microvolt = <2800000>;
   qcom,init-voltage = <2800000>;
  };
 };

 rpmh-regulator-ldon5 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldon5";

  L5N: pm8010n_l5: regulator-pm8010n-l5 {
   regulator-name = "pm8010n_l5";
   qcom,set = <3>;
   regulator-min-microvolt = <1800000>;
   regulator-max-microvolt = <1800000>;
   qcom,init-voltage = <1800000>;
  };
 };

 rpmh-regulator-ldon6 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldon6";

  L6N: pm8010n_l6: regulator-pm8010n-l6 {
   regulator-name = "pm8010n_l6";
   qcom,set = <3>;
   regulator-min-microvolt = <3304000>;
   regulator-max-microvolt = <3304000>;
   qcom,init-voltage = <3304000>;
  };
 };

 rpmh-regulator-ldon7 {
  compatible = "qcom,rpmh-vrm-regulator";
  qcom,resource-name = "ldon7";

  L7N: pm8010n_l7: regulator-pm8010n-l7 {
   regulator-name = "pm8010n_l7";
   qcom,set = <3>;
   regulator-min-microvolt = <2960000>;
   regulator-max-microvolt = <2960000>;
   qcom,init-voltage = <2960000>;
  };
 };
};
# 3668 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-qupv3.dtsi" 1
&soc {
# 22 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-qupv3.dtsi"
 gpi_dma1: qcom,gpi-dma@a00000 {
  compatible = "qcom,gpi-dma";
  #dma-cells = <5>;
  reg = <0xa00000 0x60000>;
  reg-names = "gpi-top";
  iommus = <&apps_smmu 0xb6 0x0>;
  qcom,max-num-gpii = <12>;
  interrupts = <0 279 4>,
   <0 280 4>,
   <0 281 4>,
   <0 282 4>,
   <0 283 4>,
   <0 284 4>,
   <0 293 4>,
   <0 294 4>,
   <0 295 4>,
   <0 296 4>,
   <0 297 4>,
   <0 298 4>;
  qcom,static-gpii-mask = <0x1>;
  qcom,gpii-mask = <0x1e>;
  qcom,ev-factor = <2>;
  qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
  qcom,gpi-ee-offset = <0x10000>;
  dma-coherent;
  status = "ok";
 };


 qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
  compatible = "qcom,geni-se-qup";
  reg = <0xac0000 0x2000>;
  #address-cells = <1>;
  #size-cells = <1>;
  clock-names = "m-ahb", "s-ahb";
  clocks = <&gcc 127>,
   <&gcc 128>;
  iommus = <&apps_smmu 0xa3 0x0>;
  qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
  qcom,iommu-geometry = <0x40000000 0x10000000>;
  qcom,iommu-dma = "fastmap";
  dma-coherent;
  ranges;
  status = "ok";


  qupv3_se7_2uart: qcom,qup_uart@a9c000 {
   compatible = "qcom,geni-debug-uart";
   reg = <0xa9c000 0x4000>;
   reg-names = "se_phys";
   interrupts = <0 579 4>;
   clock-names = "se";
   clocks = <&gcc 107>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se7_2uart_tx_active>, <&qupv3_se7_2uart_rx_active>;
   pinctrl-1 = <&qupv3_se7_2uart_sleep>;
   status = "disabled";
  };

  qupv3_se0_i2c: i2c@a80000 {
   compatible = "qcom,i2c-geni";
   reg = <0xa80000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 353 4>;
   clock-names = "se-clk";
   clocks = <&gcc 93>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se0_i2c_sleep>;
   dmas = <&gpi_dma1 0 0 3 64 0>,
    <&gpi_dma1 1 0 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };


  i3c1: i3c-master@a80000 {
   compatible = "qcom,geni-i3c";
   reg = <0xa80000 0x4000>,
    <0xec90000 0x10000>;
   clock-names = "se-clk";
   clocks = <&gcc 93>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep", "disable";
   pinctrl-0 = <&qupv3_se0_i3c_sda_active>, <&qupv3_se0_i3c_scl_active>;
   pinctrl-1 = <&qupv3_se0_i3c_sda_sleep>, <&qupv3_se0_i3c_scl_sleep>;
   pinctrl-2 = <&qupv3_se0_i3c_disable>;
   interrupts-extended = <&intc 0 353 4>,
    <&pdc 31 4>,
    <&pdc 30 4>;
   #address-cells = <3>;
   #size-cells = <0>;
   qcom,ibi-ctrl-id = <8>;
   status = "disabled";
  };

  qupv3_se0_spi: spi@a80000 {
   compatible = "qcom,spi-geni";
   reg = <0xa80000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 353 4>;
   clock-names = "se-clk";
   clocks = <&gcc 93>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
    <&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
   pinctrl-1 = <&qupv3_se0_spi_sleep>;
   dmas = <&gpi_dma1 0 0 1 64 0>,
    <&gpi_dma1 1 0 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se1_i2c: i2c@a84000 {
   compatible = "qcom,i2c-geni";
   reg = <0xa84000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 354 4>;
   clock-names = "se-clk";
   clocks = <&gcc 95>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se1_i2c_sleep>;
   dmas = <&gpi_dma1 0 1 3 64 0>,
    <&gpi_dma1 1 1 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };


  i3c2: i3c-master@a84000 {
   compatible = "qcom,geni-i3c";
   reg = <0xa84000 0x4000>,
    <0xeca0000 0x10000>;
   clock-names = "se-clk";
   clocks = <&gcc 95>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep", "disable";
   pinctrl-0 = <&qupv3_se1_i3c_sda_active>, <&qupv3_se1_i3c_scl_active>;
   pinctrl-1 = <&qupv3_se1_i3c_sda_sleep>, <&qupv3_se1_i3c_scl_sleep>;
   pinctrl-2 = <&qupv3_se1_i3c_disable>;
   interrupts-extended = <&intc 0 354 4>,
    <&pdc 33 4>,
    <&pdc 32 4>;
   #address-cells = <3>;
   #size-cells = <0>;
   qcom,ibi-ctrl-id = <9>;
   status = "disabled";
  };

  qupv3_se1_spi: spi@a84000 {
   compatible = "qcom,spi-geni";
   reg = <0xa84000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 354 4>;
   clock-names = "se-clk";
   clocks = <&gcc 95>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
    <&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
   pinctrl-1 = <&qupv3_se1_spi_sleep>;
   dmas = <&gpi_dma1 0 1 1 64 0>,
    <&gpi_dma1 1 1 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se2_i2c: i2c@a88000 {
   compatible = "qcom,i2c-geni";
   reg = <0xa88000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 355 4>;
   clock-names = "se-clk";
   clocks = <&gcc 97>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se2_i2c_sleep>;
   dmas = <&gpi_dma1 0 2 3 64 0>,
    <&gpi_dma1 1 2 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se2_spi: spi@a88000 {
   compatible = "qcom,spi-geni";
   reg = <0xa88000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 355 4>;
   clock-names = "se-clk";
   clocks = <&gcc 97>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
    <&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
   pinctrl-1 = <&qupv3_se2_spi_sleep>;
   dmas = <&gpi_dma1 0 2 1 64 0>,
    <&gpi_dma1 1 2 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se3_i2c: i2c@a8c000 {
   compatible = "qcom,i2c-geni";
   reg = <0xa8c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 356 4>;
   clock-names = "se-clk";
   clocks = <&gcc 99>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se3_i2c_sda_active>, <&qupv3_se3_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se3_i2c_sleep>;
   dmas = <&gpi_dma1 0 3 3 64 0>,
    <&gpi_dma1 1 3 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se3_spi: spi@a8c000 {
   compatible = "qcom,spi-geni";
   reg = <0xa8c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 356 4>;
   clock-names = "se-clk";
   clocks = <&gcc 99>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se3_spi_mosi_active>, <&qupv3_se3_spi_miso_active>,
    <&qupv3_se3_spi_clk_active>, <&qupv3_se3_spi_cs_active>;
   pinctrl-1 = <&qupv3_se3_spi_sleep>;
   dmas = <&gpi_dma1 0 3 1 64 0>,
    <&gpi_dma1 1 3 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se4_i2c: i2c@a90000 {
   compatible = "qcom,i2c-geni";
   reg = <0xa90000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 357 4>;
   clock-names = "se-clk";
   clocks = <&gcc 101>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se4_i2c_sda_active>, <&qupv3_se4_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se4_i2c_sleep>;
   dmas = <&gpi_dma1 0 4 3 64 2>,
    <&gpi_dma1 1 4 3 64 2>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se4_spi: spi@a90000 {
   compatible = "qcom,spi-geni";
   reg = <0xa90000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 357 4>;
   clock-names = "se-clk";
   clocks = <&gcc 101>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se4_spi_mosi_active>, <&qupv3_se4_spi_miso_active>,
    <&qupv3_se4_spi_clk_active>, <&qupv3_se4_spi_cs_active>;
   pinctrl-1 = <&qupv3_se4_spi_sleep>;
   dmas = <&gpi_dma1 0 4 1 64 2>,
    <&gpi_dma1 1 4 1 64 2>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };
  qupv3_se4_4uart: uart@a90000 {
   compatible = "qcom,msm-geni-serial-hs";
   reg = <0xa90000 0x4000>;
   reg-names = "se_phys";
   interrupts-extended = <&intc 0 357 4>;
   clock-names = "se-clk";
   clocks = <&gcc 101>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "active", "sleep", "shutdown";
   pinctrl-0 = <&qupv3_se4_default_cts>, <&qupv3_se4_default_rts>,
   <&qupv3_se4_default_tx>, <&qupv3_se4_default_rx>;
   pinctrl-1 = <&qupv3_se4_cts>, <&qupv3_se4_rts>,
   <&qupv3_se4_tx>, <&qupv3_se4_rx>;
   pinctrl-2 = <&qupv3_se4_cts>, <&qupv3_se4_rts>,
   <&qupv3_se4_tx>, <&qupv3_se4_rx>;
   pinctrl-3 = <&qupv3_se4_default_cts>, <&qupv3_se4_default_rts>,
   <&qupv3_se4_default_tx>, <&qupv3_se4_default_rx>;
   status = "disabled";
  };

  qupv3_se5_i2c: i2c@a94000 {
   compatible = "qcom,i2c-geni";
   reg = <0xa94000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 358 4>;
   clock-names = "se-clk";
   clocks = <&gcc 103>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se5_i2c_sleep>;
   dmas = <&gpi_dma1 0 5 3 64 0>,
    <&gpi_dma1 1 5 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se5_spi: spi@a94000 {
   compatible = "qcom,spi-geni";
   reg = <0xa94000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 358 4>;
   clock-names = "se-clk";
   clocks = <&gcc 103>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
    <&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
   pinctrl-1 = <&qupv3_se5_spi_sleep>;
   dmas = <&gpi_dma1 0 5 1 64 0>,
    <&gpi_dma1 1 5 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se6_i2c: i2c@a98000 {
   compatible = "qcom,i2c-geni";
   reg = <0xa98000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 363 4>;
   clock-names = "se-clk";
   clocks = <&gcc 105>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se6_i2c_sda_active>, <&qupv3_se6_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se6_i2c_sleep>;
   dmas = <&gpi_dma1 0 6 3 64 0>,
    <&gpi_dma1 1 6 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se6_spi: spi@a98000 {
   compatible = "qcom,spi-geni";
   reg = <0xa98000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 363 4>;
   clock-names = "se-clk";
   clocks = <&gcc 105>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 37 &clk_virt 574>,
   <&gem_noc 2 &config_noc 541>,
   <&aggre1_noc 7 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se6_spi_mosi_active>, <&qupv3_se6_spi_miso_active>,
    <&qupv3_se6_spi_clk_active>, <&qupv3_se6_spi_cs_active>;
   pinctrl-1 = <&qupv3_se6_spi_sleep>;
   dmas = <&gpi_dma1 0 6 1 64 0>,
    <&gpi_dma1 1 6 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };
 };


 gpi_dma2: qcom,gpi-dma@800000 {
  compatible = "qcom,gpi-dma";
  #dma-cells = <5>;
  reg = <0x800000 0x60000>;
  reg-names = "gpi-top";
  iommus = <&apps_smmu 0x436 0x0>;
  qcom,max-num-gpii = <12>;
  interrupts = <0 588 4>,
   <0 589 4>,
   <0 590 4>,
   <0 591 4>,
   <0 592 4>,
   <0 593 4>,
   <0 594 4>,
   <0 595 4>,
   <0 596 4>,
   <0 597 4>,
   <0 598 4>,
   <0 599 4>;
  qcom,static-gpii-mask = <0x1>;
  qcom,gpii-mask = <0x3e>;
  qcom,ev-factor = <2>;
  qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
  qcom,gpi-ee-offset = <0x10000>;
  dma-coherent;
  status = "ok";
 };


 qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
  compatible = "qcom,geni-se-qup";
  reg = <0x8c0000 0x2000>;
  #address-cells = <1>;
  #size-cells = <1>;
  clock-names = "m-ahb", "s-ahb";
  clocks = <&gcc 129>,
   <&gcc 130>;
  iommus = <&apps_smmu 0x423 0x0>;
  qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
  qcom,iommu-geometry = <0x40000000 0x10000000>;
  qcom,iommu-dma = "fastmap";
  dma-coherent;
  ranges;
  status = "ok";

  qupv3_se8_i2c: i2c@880000 {
   compatible = "qcom,i2c-geni";
   reg = <0x880000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 373 4>;
   clock-names = "se-clk";
   clocks = <&gcc 111>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se8_i2c_sda_active>, <&qupv3_se8_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se8_i2c_sleep>;
   dmas = <&gpi_dma2 0 0 3 64 2>,
    <&gpi_dma2 1 0 3 64 2>;
   dma-names = "tx", "rx";
   status = "disabled";
  };


  i3c3: i3c-master@880000 {
   compatible = "qcom,geni-i3c";
   reg = <0x880000 0x4000>,
    <0xecb000 0x10000>;
   clock-names = "se-clk";
   clocks = <&gcc 111>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep", "disable";
   pinctrl-0 = <&qupv3_se8_i3c_sda_active>, <&qupv3_se8_i3c_scl_active>;
   pinctrl-1 = <&qupv3_se8_i3c_sda_sleep>, <&qupv3_se8_i3c_scl_sleep>;
   pinctrl-2 = <&qupv3_se8_i3c_disable>;
   interrupts-extended = <&intc 0 373 4>,
    <&pdc 35 4>,
    <&pdc 34 4>;
   #address-cells = <3>;
   #size-cells = <0>;
   qcom,ibi-ctrl-id = <16>;
   status = "disabled";
  };

  qupv3_se8_spi: spi@880000 {
   compatible = "qcom,spi-geni";
   reg = <0x880000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 373 4>;
   clock-names = "se-clk";
   clocks = <&gcc 111>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se8_spi_mosi_active>, <&qupv3_se8_spi_miso_active>,
    <&qupv3_se8_spi_clk_active>, <&qupv3_se8_spi_cs_active>;
   pinctrl-1 = <&qupv3_se8_spi_sleep>;
   dmas = <&gpi_dma2 0 0 1 64 2>,
    <&gpi_dma2 1 0 1 64 2>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se9_i2c: i2c@884000 {
   compatible = "qcom,i2c-geni";
   reg = <0x884000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 583 4>;
   clock-names = "se-clk";
   clocks = <&gcc 113>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se9_i2c_sda_active>, <&qupv3_se9_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se9_i2c_sleep>;
   dmas = <&gpi_dma2 0 1 3 64 0>,
    <&gpi_dma2 1 1 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };


  i3c0: i3c-master@884000 {
   compatible = "qcom,geni-i3c";
   reg = <0x884000 0x4000>,
    <0xecc0000 0x10000>;
   clock-names = "se-clk";
   clocks = <&gcc 113>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep", "disable";
   pinctrl-0 = <&qupv3_se9_i3c_sda_active>, <&qupv3_se9_i3c_scl_active>;
   pinctrl-1 = <&qupv3_se9_i3c_sda_sleep>, <&qupv3_se9_i3c_scl_sleep>;
   pinctrl-2 = <&qupv3_se9_i3c_disable>;
   interrupts-extended = <&intc 0 583 4>,
    <&pdc 37 4>,
    <&pdc 36 4>;
   #address-cells = <3>;
   #size-cells = <0>;
   qcom,ibi-ctrl-id = <15>;
   status = "disabled";
  };

  qupv3_se9_spi: spi@884000 {
   compatible = "qcom,spi-geni";
   reg = <0x884000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 583 4>;
   clock-names = "se-clk";
   clocks = <&gcc 113>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se9_spi_mosi_active>, <&qupv3_se9_spi_miso_active>,
    <&qupv3_se9_spi_clk_active>, <&qupv3_se9_spi_cs_active>;
   pinctrl-1 = <&qupv3_se9_spi_sleep>;
   dmas = <&gpi_dma2 0 1 1 64 0>,
    <&gpi_dma2 1 1 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se10_i2c: i2c@888000 {
   compatible = "qcom,i2c-geni";
   reg = <0x888000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 584 4>;
   clock-names = "se-clk";
   clocks = <&gcc 115>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se10_i2c_sda_active>, <&qupv3_se10_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se10_i2c_sleep>;
   dmas = <&gpi_dma2 0 2 3 64 0>,
    <&gpi_dma2 1 2 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se10_spi: spi@888000 {
   compatible = "qcom,spi-geni";
   reg = <0x888000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 584 4>;
   clock-names = "se-clk";
   clocks = <&gcc 115>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se10_spi_mosi_active>, <&qupv3_se10_spi_miso_active>,
    <&qupv3_se10_spi_clk_active>, <&qupv3_se10_spi_cs_active>;
   pinctrl-1 = <&qupv3_se10_spi_sleep>;
   dmas = <&gpi_dma2 0 2 1 64 0>,
    <&gpi_dma2 1 2 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se11_i2c: i2c@88c000 {
   compatible = "qcom,i2c-geni";
   reg = <0x88c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 585 4>;
   clock-names = "se-clk";
   clocks = <&gcc 117>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se11_i2c_sda_active>, <&qupv3_se11_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se11_i2c_sleep>;
   dmas = <&gpi_dma2 0 3 3 64 0>,
    <&gpi_dma2 1 3 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se11_spi: spi@88c000 {
   compatible = "qcom,spi-geni";
   reg = <0x88c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 585 4>;
   clock-names = "se-clk";
   clocks = <&gcc 117>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se11_spi_mosi_active>, <&qupv3_se11_spi_miso_active>,
    <&qupv3_se11_spi_clk_active>, <&qupv3_se11_spi_cs_active>;
   pinctrl-1 = <&qupv3_se11_spi_sleep>;
   dmas = <&gpi_dma2 0 3 1 64 0>,
    <&gpi_dma2 1 3 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se12_i2c: i2c@890000 {
   compatible = "qcom,i2c-geni";
   reg = <0x890000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 586 4>;
   clock-names = "se-clk";
   clocks = <&gcc 119>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se12_i2c_sda_active>, <&qupv3_se12_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se12_i2c_sleep>;
   dmas = <&gpi_dma2 0 4 3 64 0>,
    <&gpi_dma2 1 4 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se12_spi: spi@890000 {
   compatible = "qcom,spi-geni";
   reg = <0x890000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 586 4>;
   clock-names = "se-clk";
   clocks = <&gcc 119>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se12_spi_mosi_active>, <&qupv3_se12_spi_miso_active>,
    <&qupv3_se12_spi_clk_active>, <&qupv3_se12_spi_cs_active>;
   pinctrl-1 = <&qupv3_se12_spi_sleep>;
   dmas = <&gpi_dma2 0 4 1 64 0>,
    <&gpi_dma2 1 4 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };

  qupv3_se13_i2c: i2c@894000 {
   compatible = "qcom,i2c-geni";
   reg = <0x894000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 587 4>;
   clock-names = "se-clk";
   clocks = <&gcc 121>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se13_i2c_sda_active>, <&qupv3_se13_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se13_i2c_sleep>;
   dmas = <&gpi_dma2 0 5 3 64 0>,
    <&gpi_dma2 1 5 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se13_spi: spi@894000 {
   compatible = "qcom,spi-geni";
   reg = <0x894000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 587 4>;
   clock-names = "se-clk";
   clocks = <&gcc 121>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se13_spi_mosi_active>, <&qupv3_se13_spi_miso_active>,
    <&qupv3_se13_spi_clk_active>, <&qupv3_se13_spi_cs_active>;
   pinctrl-1 = <&qupv3_se13_spi_sleep>;
   dmas = <&gpi_dma2 0 5 1 64 0>,
    <&gpi_dma2 1 5 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };


  qupv3_se14_4uart: qcom,qup_uart@898000 {
   compatible = "qcom,msm-geni-serial-hs";
   reg = <0x898000 0x4000>;
   reg-names = "se_phys";
   interrupts-extended = <&intc 0 461 4>,
     <&tlmm 79 4>;
   clock-names = "se-clk";
   clocks = <&gcc 123>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "active", "sleep", "shutdown";
   pinctrl-0 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
   <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
   pinctrl-1 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
   <&qupv3_se14_tx>, <&qupv3_se14_rx>;
   pinctrl-2 = <&qupv3_se14_cts>, <&qupv3_se14_rts>,
   <&qupv3_se14_tx>, <&qupv3_se14_default_rx>;
   pinctrl-3 = <&qupv3_se14_default_cts>, <&qupv3_se14_default_rts>,
   <&qupv3_se14_default_tx>, <&qupv3_se14_default_rx>;
   qcom,wakeup-byte = <0xFD>;
   status = "disabled";
  };

  qupv3_se15_i2c: i2c@89c000 {
   compatible = "qcom,i2c-geni";
   reg = <0x89c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 462 4>;
   clock-names = "se-clk";
   clocks = <&gcc 125>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se15_i2c_sda_active>, <&qupv3_se15_i2c_scl_active>;
   pinctrl-1 = <&qupv3_se15_i2c_sleep>;
   dmas = <&gpi_dma2 0 7 3 64 0>,
    <&gpi_dma2 1 7 3 64 0>;
   dma-names = "tx", "rx";
   status = "disabled";
  };

  qupv3_se15_spi: spi@89c000 {
   compatible = "qcom,spi-geni";
   reg = <0x89c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   reg-names = "se_phys";
   interrupts = <0 462 4>;
   clock-names = "se-clk";
   clocks = <&gcc 125>;
   interconnect-names = "qup-core", "qup-config", "qup-memory";
   interconnects =
   <&clk_virt 38 &clk_virt 575>,
   <&gem_noc 2 &config_noc 542>,
   <&aggre2_noc 8 &mc_virt 512>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_se15_spi_mosi_active>, <&qupv3_se15_spi_miso_active>,
    <&qupv3_se15_spi_clk_active>, <&qupv3_se15_spi_cs_active>;
   pinctrl-1 = <&qupv3_se15_spi_sleep>;
   dmas = <&gpi_dma2 0 7 1 64 0>,
    <&gpi_dma2 1 7 1 64 0>;
   dma-names = "tx", "rx";
   spi-max-frequency = <50000000>;
   status = "disabled";
  };
 };


 qupv3_0_i2c_hub: qcom,qupv3_i2c_geni_se@9c0000 {
  compatible = "qcom,geni-se-qup";
  reg = <0x9c0000 0x2000>;
  #address-cells = <1>;
  #size-cells = <1>;




  clock-names = "m-ahb", "s-ahb";
  clocks = <&gcc 90>,
   <&gcc 90>;
  ranges;
  status = "ok";

  qupv3_hub_i2c0: i2c@980000 {
   compatible = "qcom,i2c-geni";
   reg = <0x980000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 464 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 70>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c0_sda_active>, <&qupv3_hub_i2c0_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c0_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c1: i2c@984000 {
   compatible = "qcom,i2c-geni";
   reg = <0x984000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 465 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 72>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c1_sda_active>, <&qupv3_hub_i2c1_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c1_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c2: i2c@988000 {
   compatible = "qcom,i2c-geni";
   reg = <0x988000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 466 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 74>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c2_sda_active>, <&qupv3_hub_i2c2_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c2_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c3: i2c@98c000 {
   compatible = "qcom,i2c-geni";
   reg = <0x98c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 467 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 76>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c3_sda_active>, <&qupv3_hub_i2c3_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c3_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c4: i2c@990000 {
   compatible = "qcom,i2c-geni";
   reg = <0x990000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 468 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 78>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c4_sda_active>, <&qupv3_hub_i2c4_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c4_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c5: i2c@994000 {
   compatible = "qcom,i2c-geni";
   reg = <0x994000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 469 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 80>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c5_sda_active>, <&qupv3_hub_i2c5_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c5_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c6: i2c@998000 {
   compatible = "qcom,i2c-geni";
   reg = <0x998000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 470 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 82>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c6_sda_active>, <&qupv3_hub_i2c6_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c6_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c7: i2c@99c000 {
   compatible = "qcom,i2c-geni";
   reg = <0x99c000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 471 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 84>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c7_sda_active>, <&qupv3_hub_i2c7_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c7_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c8: i2c@9a0000 {
   compatible = "qcom,i2c-geni";
   reg = <0x9a0000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 472 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 86>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c8_sda_active>, <&qupv3_hub_i2c8_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c8_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };

  qupv3_hub_i2c9: i2c@9a4000 {
   compatible = "qcom,i2c-geni";
   reg = <0x9a4000 0x4000>;
   #address-cells = <1>;
   #size-cells = <0>;
   interrupts = <0 473 4>;
   clock-names = "se-clk", "core-clk";
   clocks = <&gcc 88>,
    <&gcc 69>;
   interconnect-names = "qup-core", "qup-config";
   interconnects =
   <&clk_virt 36 &clk_virt 573>,
   <&gem_noc 2 &config_noc 528>;
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&qupv3_hub_i2c9_sda_active>, <&qupv3_hub_i2c9_scl_active>;
   pinctrl-1 = <&qupv3_hub_i2c9_sleep>;
   qcom,i2c-hub;
   status = "disabled";
  };
 };
};
# 3669 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-usb.dtsi" 1

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h" 1
# 3 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-usb.dtsi" 2

&soc {
 usb0: ssusb@a600000 {
  compatible = "qcom,dwc-usb3-msm";
  reg = <0xa600000 0x100000>,
   <0x1fc6000 0x4>;
  reg-names = "core_base",
   "tcsr_dyn_en_dis";

  #address-cells = <1>;
  #size-cells = <1>;
  ranges;

  USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
  clocks = <&gcc 156>,
   <&gcc 11>,
   <&gcc 3>,
   <&gcc 158>,
   <&gcc 161>;
  clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
     "utmi_clk", "sleep_clk";

  resets = <&gcc 25>;
  reset-names = "core_reset";

  interrupts-extended = <&intc 0 130 4>,
   <&pdc 14 1>,
   <&pdc 15 1>,
   <&pdc 17 4>;
  interrupt-names = "pwr_event_irq", "dp_hs_phy_irq",
    "dm_hs_phy_irq", "ss_phy_irq";
  qcom,use-pdc-interrupts;
  qcom,use-eusb2-phy;
  extcon = <&eud>;

  qcom,dis-sending-cm-l1-quirk;
  qcom,core-clk-rate = <200000000>;
  qcom,core-clk-rate-hs = <66666667>;
  qcom,core-clk-rate-disconnected = <133333333>;
  qcom,pm-qos-latency = <2>;
  qcom,num-gsi-evt-buffs = <0x3>;
  qcom,gsi-reg-offset =
   <0x0fc
   0x110
   0x120
   0x130
   0x144
   0x1a4>;

  interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
  interconnects = <&aggre1_noc 52 &mc_virt 512>,
    <&aggre1_noc 52 &config_noc 530>,
    <&gem_noc 2 &config_noc 550>;
  dwc3@a600000 {
   compatible = "snps,dwc3";
   reg = <0xa600000 0xd93c>;

   iommus = <&apps_smmu 0x40 0x0>;
   qcom,iommu-dma = "atomic";
   qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
   dma-coherent;

   interrupts = <0 133 4>;
   usb-phy = <&eusb2_phy0>, <&usb_qmp_dp_phy>;
   snps,disable-clk-gating;
   snps,has-lpm-erratum;
   snps,hird-threshold = /bits/ 8 <0x0>;
   snps,is-utmi-l1-suspend;
   snps,dis-u1-entry-quirk;
   snps,dis-u2-entry-quirk;
   snps,dis_u2_susphy_quirk;
   snps,ssp-u3-u0-quirk;
   tx-fifo-resize;
   dr_mode = "otg";
   maximum-speed = "super-speed-plus";
   usb-role-switch;
  };

  qcom,usbbam@a704000 {
   compatible = "qcom,usb-bam-msm";
   reg = <0xa704000 0x18000>;
   interrupts = <0 132 4>;

   qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
   qcom,usb-bam-num-pipes = <4>;
   qcom,disable-clk-gating;
   qcom,usb-bam-override-threshold = <0x4001>;
   qcom,usb-bam-max-mbps-highspeed = <400>;
   qcom,usb-bam-max-mbps-superspeed = <3600>;
   qcom,reset-bam-on-connect;

   qcom,pipe0 {
    label = "ssusb-qdss-in-0";
    qcom,usb-bam-mem-type = <2>;
    qcom,dir = <1>;
    qcom,pipe-num = <0>;
    qcom,peer-bam = <0>;
    qcom,peer-bam-physical-address = <0x10064000>;
    qcom,src-bam-pipe-index = <0>;
    qcom,dst-bam-pipe-index = <0>;
    qcom,data-fifo-offset = <0x0>;
    qcom,data-fifo-size = <0x1800>;
    qcom,descriptor-fifo-offset = <0x1800>;
    qcom,descriptor-fifo-size = <0x800>;
   };
  };
 };


 eusb2_phy0: hsphy@88e3000 {
  compatible = "qcom,usb-snps-eusb2-phy";
  reg = <0x88e3000 0x154>,
   <0x088e2000 0x4>,
   <0x0C276000 0x4>;
  reg-names = "eusb2_phy_base",
   "eud_enable_reg",
   "eud_detect_reg";

  vdd-supply = <&pm_v6e_l1>;
  qcom,vdd-voltage-level = <0 880000 880000>;
  vdda12-supply = <&pm_v6e_l3>;

  clocks = <&rpmhcc 27>,
   <&tcsrcc 4>;
  clock-names = "ref_clk_src", "ref_clk";

  resets = <&gcc 20>;
  reset-names = "phy_reset";
 };


 usb_qmp_dp_phy: ssphy@88e8000 {
  compatible = "qcom,usb-ssphy-qmp-dp-combo";
  reg = <0x88e8000 0x3000>;
  reg-names = "qmp_phy_base";

  vdd-supply = <&pm_v8_l3>;
  qcom,vdd-voltage-level = <0 912000 912000>;
  qcom,vdd-max-load-uA = <47000>;
  core-supply = <&pm_v6e_l3>;

  usb3_dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
  clocks = <&gcc 162>,
   <&gcc 165>,
   <&gcc 166>,
   <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
   <&rpmhcc 27>,
   <&tcsrcc 5>,
   <&gcc 164>;
  clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
   "pipe_clk_ext_src", "ref_clk_src",
   "ref_clk", "com_aux_clk";

  resets = <&gcc 26>,
   <&gcc 28>;
  reset-names = "global_phy_reset", "phy_reset";

  pinctrl-names = "default";
  pinctrl-0 = <&usb3phy_portselect_default>;
  qcom,qmp-phy-reg-offset =
   <0x1C14
    0x1F08
    0x1F14
    0x1C40
    0x1C00
    0x1C44
    0xffff
    0x0008
    0x0004
    0x001C
    0x0000
    0x0010
    0x1E00>;

  qcom,qmp-phy-init-seq =

         <0x1000 0xC0
   0x1004 0x01
   0x1010 0x02
   0x1014 0x16
   0x1018 0x36
   0x101C 0x04
   0x1020 0x16
   0x1024 0x41
   0x1028 0x41
   0x102C 0x00
   0x1030 0x55
   0x1034 0x75
   0x1038 0x01
   0x103C 0x01
   0x1048 0x25
   0x104C 0x02
   0x1050 0x5C
   0x1054 0x0F
   0x1058 0x5C
   0x105C 0x0F
   0x1060 0xC0
   0x1064 0x01
   0x1070 0x02
   0x1074 0x16
   0x1078 0x36
   0x1080 0x08
   0x1084 0x1A
   0x1088 0x41
   0x108C 0x00
   0x1090 0x55
   0x1094 0x75
   0x1098 0x01
   0x10A8 0x25
   0x10AC 0x02
   0x10BC 0x0A
   0x10C0 0x01
   0x10CC 0x62
   0x10D0 0x02
   0x10E8 0x0C
   0x1110 0x1A
   0x1124 0x14
   0x1140 0x04
   0x1170 0x20
   0x1174 0x16
   0x11A4 0xB6
   0x11A8 0x4B
   0x11AC 0x37
   0x11B4 0x0C
   0x1234 0x00
   0x1238 0x00
   0x123C 0x1F
   0x1240 0x09
   0x1284 0xF5
   0x128C 0x3F
   0x1290 0x3F
   0x1294 0x5F
   0x12A4 0x12
   0x12E4 0x21
   0x1408 0x0A
   0x1414 0x06
   0x1430 0x2F
   0x1434 0x7F
   0x143C 0xFF
   0x1440 0x0F
   0x1444 0x99
   0x144C 0x08
   0x1450 0x08
   0x1454 0x00
   0x1458 0x0A
   0x1460 0xA0
   0x14D4 0x54
   0x14D8 0x0F
   0x14DC 0x13
   0x14EC 0x0F
   0x14F0 0x4A
   0x14F4 0x0A
   0x14F8 0x07
   0x14FC 0x00
   0x1510 0x47
   0x151C 0x04
   0x1524 0x0E
   0x155C 0x3F
   0x1560 0xBF
   0x1564 0xFF
   0x1568 0xDF
   0x156C 0xED
   0x1570 0xDC
   0x1574 0x5C
   0x1578 0x9C
   0x157C 0x1D
   0x1580 0x0C
   0x15A0 0x04
   0x15A4 0x38
   0x15A8 0x0C
   0x15B0 0x10
   0x15E4 0x14
   0x15F8 0x08
   0x1634 0x00
   0x1638 0x00
   0x163C 0x1F
   0x1640 0x09
   0x1684 0xF5
   0x168C 0x3F
   0x1690 0x3F
   0x1694 0x5F
   0x16A4 0x12
   0x16E4 0x05
   0x1808 0x0A
   0x1814 0x06
   0x1830 0x2F
   0x1834 0x7F
   0x183C 0xFF
   0x1840 0x0F
   0x1844 0x99
   0x184C 0x08
   0x1850 0x08
   0x1854 0x00
   0x1858 0x0A
   0x1860 0xA0
   0x18D4 0x54
   0x18D8 0x0F
   0x18DC 0x13
   0x18EC 0x0F
   0x18F0 0x4A
   0x18F4 0x0A
   0x18F8 0x07
   0x18FC 0x00
   0x1910 0x47
   0x191C 0x04
   0x1924 0x0E
   0x195C 0xBF
   0x1960 0xBF
   0x1964 0xBF
   0x1968 0xDF
   0x196C 0xFD
   0x1970 0xDC
   0x1974 0x5C
   0x1978 0x9C
   0x197C 0x1D
   0x1980 0x0C
   0x19A0 0x04
   0x19A4 0x38
   0x19A8 0x0C
   0x19B0 0x10
   0x19E4 0x14
   0x19F8 0x08
   0x1CC4 0xC4
   0x1CC8 0x89
   0x1CCC 0x20
   0x1CD8 0x13
   0x1CDC 0x21
   0x1D88 0x99
   0x1D90 0xE7
   0x1D94 0x03
   0x1DB0 0x0A
   0x1DC0 0x88
   0x1DC4 0x13
   0x1DD0 0x0C
   0x1DDC 0x4B
   0x1DEC 0x10
   0x1F00 0x68
   0x1F18 0xF8
   0x1F3C 0x07
   0x1F40 0x40
   0x1F44 0x00>;
 };

 usb_audio_qmi_dev {
  compatible = "qcom,usb-audio-qmi-dev";
  iommus = <&apps_smmu 0x100b 0x0>;
  qcom,iommu-dma = "disabled";
  qcom,usb-audio-stream-id = <0xb>;
  qcom,usb-audio-intr-num = <2>;
 };
};
# 3670 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-eva.dtsi" 1





&soc {
 msm_cvp: qcom,cvp@ab00000 {
  compatible = "qcom,msm-cvp", "qcom,kalama-cvp";
  status = "ok";
  reg = <0xab00000 0x100000>;
  interrupts = <0 234 4>,<0 235 4>;


  cache-slice-names = "cvp";


  cvp-supply = <&video_cc_mvs1c_gdsc>;
  cvp-core-supply = <&video_cc_mvs1_gdsc>;


  clock-names = "gcc_video_axi1", "cvp_clk", "core_clk",
    "video_cc_mvs1_clk_src";
  clock-ids = <169 10
   7 8>;
  clocks = <&gcc 169>,
   <&videocc 10>,
   <&videocc 7>,
   <&videocc 8>;
  qcom,proxy-clock-names = "gcc_video_axi1",
   "cvp_clk", "core_clk", "video_cc_mvs1_clk_src";

  qcom,clock-configs = <0x0 0x0 0x0 0x1>;
  qcom,allowed-clock-rates = <350000000 450000000 500000000 550000000>;

  resets = <&gcc 34>,
   <&videocc 5>;
  reset-names = "cvp_axi_reset", "cvp_core_reset";
  reset-power-status = <0x2 0x2>;

  qcom,reg-presets = <0xB0088 0x0>;
  qcom,ipcc-reg = <0x400000 0x100000>;
  qcom,gcc-reg = <0x110000 0x40000>;

  pas-id = <26>;
  memory-region = <&cvp_mem>;


  cvp,firmware-name = "evass";


  cvp_cnoc {
   compatible = "qcom,msm-cvp,bus";
   label = "cvp-cnoc";
   qcom,bus-master = <2>;
   qcom,bus-slave = <551>;
   qcom,bus-governor = "performance";
   qcom,bus-range-kbps = <1000 1000>;
  };

  cvp_bus_ddr {
   compatible = "qcom,msm-cvp,bus";
   label = "cvp-ddr";
   qcom,bus-master = <31>;
   qcom,bus-slave = <512>;
   qcom,bus-governor = "performance";
   qcom,bus-range-kbps = <1000 6533000>;
  };


  cvp_non_secure_cb {
   compatible = "qcom,msm-cvp,context-bank";
   label = "cvp_hlos";
   iommus =
    <&apps_smmu 0x1920 0x0000>;
   buffer-types = <0xfff>;
   dma-coherent;
   qcom,iommu-faults = "non-fatal";
   qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
  };


  cvp_secure_nonpixel_cb {
   compatible = "qcom,msm-cvp,context-bank";
   label = "cvp_sec_nonpixel";
   iommus =
    <&apps_smmu 0x1924 0x0000>;
   buffer-types = <0x741>;
   qcom,iommu-faults = "non-fatal";
   qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
   qcom,iommu-vmid = <0xB>;
  };

  cvp_secure_pixel_cb {
   compatible = "qcom,msm-cvp,context-bank";
   label = "cvp_sec_pixel";
   iommus =
    <&apps_smmu 0x1923 0x0000>;
   buffer-types = <0x106>;
   qcom,iommu-faults = "non-fatal";
   qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
   qcom,iommu-vmid = <0xA>;
  };


  qcom,msm-cvp,mem_cdsp {
   compatible = "qcom,msm-cvp,mem-cdsp";
   memory-region = <&cdsp_eva_mem>;
  };
 };
};
# 3671 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-pcie.dtsi" 1

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 3 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-pcie.dtsi" 2

&soc {
 pcie0: qcom,pcie@1c00000 {
  compatible = "qcom,pci-msm";
  device_type = "pci";

  reg = <0x01c00000 0x3000>,
   <0x01c06000 0x2000>,
   <0x60000000 0xf1d>,
   <0x60000f20 0xa8>,
   <0x60001000 0x1000>,
   <0x60100000 0x100000>;
  reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";

  cell-index = <0>;
  linux,pci-domain = <0>;

  #address-cells = <3>;
  #size-cells = <2>;
  ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
   <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;

  interrupts = <0 140 4
    0 149 4
    0 150 4
    0 151 4
    0 152 4>;

  interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
    "int_d";

  msi-map = <0x0 &gic_its 0x1400 0x1>,
   <0x100 &gic_its 0x1401 0x1>;

  perst-gpio = <&tlmm 94 0>;
  wake-gpio = <&tlmm 96 0>;
  pinctrl-names = "default", "sleep";
  pinctrl-0 = <&pcie0_perst_default
    &pcie0_clkreq_default
    &pcie0_wake_default>;
  pinctrl-1 = <&pcie0_perst_default
    &pcie0_clkreq_sleep
    &pcie0_wake_default>;

  gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
  gdsc-phy-vdd-supply = <&gcc_pcie_0_phy_gdsc>;
  vreg-1p2-supply = <&pm_v6e_l3>;
  vreg-0p9-supply = <&pm_v6e_l1>;
  vreg-cx-supply = <&VDD_CX_LEVEL>;
  vreg-mx-supply = <&VDD_MXA_LEVEL>;
  qcom,vreg-1p2-voltage-level = <1200000 1200000 18200>;
  qcom,vreg-0p9-voltage-level = <880000 880000 80900>;
  qcom,vreg-cx-voltage-level = <65535
      256 0>;
  qcom,vreg-mx-voltage-level = <65535
      256 0>;
  qcom,bw-scale =
    <64
    64
    19200000

    64
    64
    19200000

    256
    256
    100000000>;

  interconnect-names = "icc_path";
  interconnects = <&pcie_noc 45 &mc_virt 512>;

  clocks = <&gcc 40>,
   <&rpmhcc 0>,
   <&gcc 34>,
   <&gcc 36>,
   <&gcc 37>,
   <&gcc 42>,
   <&tcsrcc 0>,
   <&gcc 43>,
   <&gcc 38>,
   <&gcc 14>,
   <&gcc 0>,
   <&gcc 41>,
   <&pcie_0_pipe_clk>;
  clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
    "pcie_aux_clk", "pcie_cfg_ahb_clk",
    "pcie_mstr_axi_clk", "pcie_slv_axi_clk",
    "pcie_clkref_en", "pcie_slv_q2a_axi_clk",
    "pcie_rate_change_clk",
    "gcc_ddrss_pcie_sf_qtb_clk",
    "pcie_aggre_noc_axi_clk", "pcie_pipe_clk_mux",
    "pcie_pipe_clk_ext_src";
  clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>,
    <100000000>, <0>, <0>, <0>, <0>;
  clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
    <0>, <0>, <0>, <0>, <0>;

  resets = <&gcc 3>,
   <&gcc 6>;
  reset-names = "pcie_0_core_reset",
    "pcie_0_phy_reset";

  dma-coherent;
  qcom,smmu-sid-base = <0x1400>;
  iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
   <0x100 &apps_smmu 0x1401 0x1>;

  qcom,boot-option = <0x1>;
  qcom,aux-clk-freq = <20>;
  qcom,drv-name = "lpass";
  qcom,drv-l1ss-timeout-us = <5000>;
  qcom,l1-2-th-scale = <2>;
  qcom,l1-2-th-value = <150>;
  qcom,slv-addr-space-size = <0x4000000>;
  qcom,ep-latency = <10>;
  qcom,num-parf-testbus-sel = <0xb9>;
  qcom,config-recovery;

  qcom,pcie-phy-ver = <101>;
  qcom,phy-status-offset = <0x214>;
  qcom,phy-status-bit = <6>;
  qcom,phy-power-down-offset = <0x240>;

  qcom,phy-sequence = <0x0240 0x03 0x0
    0x00c0 0x01 0x0
    0x00cc 0x62 0x0
    0x00d0 0x02 0x0
    0x0060 0xf8 0x0
    0x0064 0x01 0x0
    0x0000 0x93 0x0
    0x0004 0x01 0x0
    0x00e0 0x90 0x0
    0x00e4 0x82 0x0
    0x00f4 0x07 0x0
    0x0070 0x02 0x0
    0x0010 0x02 0x0
    0x0074 0x16 0x0
    0x0014 0x16 0x0
    0x0078 0x36 0x0
    0x0018 0x36 0x0
    0x0110 0x08 0x0
    0x00bc 0x0a 0x0
    0x0120 0x42 0x0
    0x0080 0x04 0x0
    0x0084 0x0d 0x0
    0x0020 0x0a 0x0
    0x0024 0x1a 0x0
    0x0088 0x41 0x0
    0x0028 0x34 0x0
    0x0090 0xab 0x0
    0x0094 0xaa 0x0
    0x0098 0x01 0x0
    0x0030 0x55 0x0
    0x0034 0x55 0x0
    0x0038 0x01 0x0
    0x0140 0x14 0x0
    0x0164 0x34 0x0
    0x003c 0x01 0x0
    0x001c 0x04 0x0
    0x0174 0x16 0x0
    0x01bc 0x0f 0x0
    0x0170 0xa0 0x0
    0x11a4 0x38 0x0
    0x10dc 0x11 0x0
    0x1160 0xbf 0x0
    0x1164 0xbf 0x0
    0x1168 0xb7 0x0
    0x116c 0xea 0x0
    0x115c 0x3f 0x0
    0x1174 0x5c 0x0
    0x1178 0x9c 0x0
    0x117c 0x1a 0x0
    0x1180 0x89 0x0
    0x1170 0xdc 0x0
    0x1188 0x94 0x0
    0x118c 0x5b 0x0
    0x1190 0x1a 0x0
    0x1194 0x89 0x0
    0x10cc 0x00 0x0
    0x1008 0x09 0x0
    0x1014 0x05 0x0
    0x104c 0x08 0x0
    0x1050 0x08 0x0
    0x10d8 0x0f 0x0
    0x1118 0x1c 0x0
    0x10f8 0x07 0x0
    0x11f8 0x08 0x0
    0x0e84 0x15 0x0
    0x0e90 0x3f 0x0
    0x0ee4 0x02 0x0
    0x0e40 0x06 0x0
    0x0e3c 0x18 0x0
    0x19a4 0x38 0x0
    0x18dc 0x11 0x0
    0x1960 0xbf 0x0
    0x1964 0xbf 0x0
    0x1968 0xb7 0x0
    0x196c 0xea 0x0
    0x195c 0x3f 0x0
    0x1974 0x5c 0x0
    0x1978 0x9c 0x0
    0x197c 0x1a 0x0
    0x1980 0x89 0x0
    0x1970 0xdc 0x0
    0x1988 0x94 0x0
    0x198c 0x5b 0x0
    0x1990 0x1a 0x0
    0x1994 0x89 0x0
    0x18cc 0x00 0x0
    0x1808 0x09 0x0
    0x1814 0x05 0x0
    0x184c 0x08 0x0
    0x1850 0x08 0x0
    0x18d8 0x0f 0x0
    0x1918 0x1c 0x0
    0x18f8 0x07 0x0
    0x19f8 0x08 0x0
    0x1684 0x15 0x0
    0x1690 0x3f 0x0
    0x16e4 0x02 0x0
    0x1640 0x06 0x0
    0x163c 0x18 0x0
    0x02dc 0x05 0x0
    0x0388 0x77 0x0
    0x0398 0x0b 0x0
    0x06a4 0x1e 0x0
    0x03e0 0x0f 0x0
    0x060c 0x1d 0x0
    0x0614 0x07 0x0
    0x0620 0xc1 0x0
    0x0694 0x00 0x0
    0x03d0 0x8c 0x0
    0x0200 0x00 0x0
    0x0244 0x03 0x0>;

  qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
     0x04D0 0x04D4 0x03C0 0x0630 0x0230
     0x0000>;
  qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01F4 0x0730
     0x0734 0x0738 0x073C>;
  qcom,phy-debug-reg = <0x01CC 0x01D0 0x01D4 0x01D8 0x01DC
     0x01E0 0x01E4 0x01F8 0x0ED0 0x16D0
     0x0EDC 0x16DC 0x11E0 0x19E0 0x0A00
     0x1200 0x0A04 0x1204 0x0A08 0x1208
     0x0A0C 0x120C 0x0A10 0x1210 0x0A14
     0x1214 0x0A18 0x1218 0x0c20 0x1420
     0x0214 0x0218 0x021C 0x0220 0x0224
     0x0228 0x022C 0x0230 0x0234 0x0238
     0x023C 0x0600 0x0604>;

  pcie0_rp: pcie0_rp {
   reg = <0 0 0 0 0>;
  };
 };

 pcie0_msi: qcom,pcie0_msi@0x17110040 {
  compatible = "qcom,pci-msi";
  msi-controller;
  reg = <0x17110040 0x0>;
  interrupt-parent = <&intc>;
  interrupts = <0 768 1>,
   <0 769 1>,
   <0 770 1>,
   <0 771 1>,
   <0 772 1>,
   <0 773 1>,
   <0 774 1>,
   <0 775 1>,
   <0 776 1>,
   <0 777 1>,
   <0 778 1>,
   <0 779 1>,
   <0 780 1>,
   <0 781 1>,
   <0 782 1>,
   <0 783 1>,
   <0 784 1>,
   <0 785 1>,
   <0 786 1>,
   <0 787 1>,
   <0 788 1>,
   <0 789 1>,
   <0 790 1>,
   <0 791 1>,
   <0 792 1>,
   <0 793 1>,
   <0 794 1>,
   <0 795 1>,
   <0 796 1>,
   <0 797 1>,
   <0 798 1>,
   <0 799 1>;
  status = "disabled";
 };

 pcie1: qcom,pcie@1c08000 {
  compatible = "qcom,pci-msm";
  device_type = "pci";

  reg = <0x01c08000 0x3000>,
   <0x01c0e000 0x2000>,
   <0x40000000 0xf1d>,
   <0x40000f20 0xa8>,
   <0x40001000 0x1000>,
   <0x40100000 0x100000>;
  reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";

  cell-index = <1>;
  linux,pci-domain = <1>;

  #address-cells = <3>;
  #size-cells = <2>;
  ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
   <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;

  interrupts = <0 306 4
    0 434 4
    0 435 4
    0 438 4
    0 439 4>;

  interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
    "int_d";

  msi-map = <0x0 &gic_its 0x1480 0x1>,
   <0x100 &gic_its 0x1481 0x1>;

  perst-gpio = <&tlmm 97 0>;
  wake-gpio = <&tlmm 99 0>;
  pinctrl-names = "default", "sleep";
  pinctrl-0 = <&pcie1_perst_default
    &pcie1_clkreq_default
    &pcie1_wake_default>;
  pinctrl-1 = <&pcie1_perst_default
    &pcie1_clkreq_sleep
    &pcie1_wake_default>;

  gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
  gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
  vreg-1p2-supply = <&pm_v6e_l3>;
  vreg-0p9-supply = <&pm_v6c_l3>;
  vreg-qref-supply = <&pm_v6e_l1>;
  vreg-cx-supply = <&VDD_CX_LEVEL>;
  vreg-mx-supply = <&VDD_MXA_LEVEL>;

  qcom,vreg-1p2-voltage-level = <1200000 1200000 26100>;
  qcom,vreg-0p9-voltage-level = <912000 880000 193000>;
  qcom,vreg-cx-voltage-level = <65535
      256 0>;
  qcom,vreg-mx-voltage-level = <65535
      256 0>;
  qcom,vreg-qref-voltage-level = <880000 880000 25700>;
  qcom,bw-scale =
    <64
    64
    19200000

    64
    64
    19200000

    64
    64
    100000000

    256
    256
    100000000>;

  interconnect-names = "icc_path";
  interconnects = <&pcie_noc 46 &mc_virt 512>;

  clocks = <&gcc 52>,
   <&rpmhcc 0>,
   <&gcc 44>,
   <&gcc 46>,
   <&gcc 47>,
   <&gcc 54>,
   <&tcsrcc 1>,
   <&gcc 55>,
   <&gcc 50>,
   <&gcc 14>,
   <&gcc 0>,
   <&gcc 12>,
   <&gcc 53>,
   <&pcie_1_pipe_clk>,
   <&gcc 48>;
  clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
    "pcie_aux_clk", "pcie_cfg_ahb_clk",
    "pcie_mstr_axi_clk", "pcie_slv_axi_clk",
    "pcie_clkref_en", "pcie_slv_q2a_axi_clk",
    "pcie_rate_change_clk",
    "gcc_ddrss_pcie_sf_qtb_clk",
    "pcie_aggre_noc_axi_clk",
    "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
    "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
  clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>,
    <0>, <100000000>, <0>, <0>, <0>, <0>, <0>, <0>;

  clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
    <0>, <0>, <0>, <0>, <0>, <0>, <0>;

  resets = <&gcc 8>,
   <&gcc 11>,
   <&gcc 9>,
   <&gcc 10>;
  reset-names = "pcie_1_core_reset",
    "pcie_1_phy_reset",
    "pcie_1_link_down_reset",
    "pcie_1_phy_nocsr_com_phy_reset";

  dma-coherent;
  qcom,smmu-sid-base = <0x1480>;
  iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
   <0x100 &apps_smmu 0x1481 0x1>;

  qcom,boot-option = <0x1>;
  qcom,no-l0s-supported;
  qcom,aux-clk-freq = <17>;
  qcom,drv-name = "lpass";
  qcom,drv-l1ss-timeout-us = <5000>;
  qcom,eq-fmdc-t-min-phase23 = <1>;
  qcom,slv-addr-space-size = <0x20000000>;
  qcom,ep-latency = <10>;
  qcom,num-parf-testbus-sel = <0xb9>;
  qcom,l1-2-th-scale = <2>;
  qcom,l1-2-th-value = <150>;

  qcom,pcie-phy-ver = <100>;
  qcom,phy-status-offset = <0x1214>;
  qcom,phy-status-bit = <7>;
  qcom,phy-power-down-offset = <0x1240>;

  qcom,phy-sequence = <0x1240 0x03 0x0
    0x0030 0x1d 0x0
    0x0034 0x03 0x0
    0x0078 0x01 0x0
    0x007c 0x00 0x0
    0x0080 0x51 0x0
    0x00ac 0x34 0x0
    0x0208 0x0c 0x0
    0x020c 0x0a 0x0
    0x0218 0x04 0x0
    0x0220 0x16 0x0
    0x0234 0x00 0x0
    0x029c 0x80 0x0
    0x02a0 0x7c 0x0
    0x02b4 0x05 0x0
    0x02e8 0x0a 0x0
    0x030c 0x0d 0x0
    0x0320 0x0b 0x0
    0x0348 0x1c 0x0
    0x0388 0x20 0x0
    0x0394 0x30 0x0
    0x03dc 0x09 0x0
    0x03f4 0x14 0x0
    0x03f8 0xb3 0x0
    0x03fc 0x58 0x0
    0x0400 0x9a 0x0
    0x0404 0x26 0x0
    0x0408 0xb6 0x0
    0x040c 0xee 0x0
    0x0410 0xdb 0x0
    0x0414 0xdb 0x0
    0x0418 0xa0 0x0
    0x041c 0xdf 0x0
    0x0420 0x78 0x0
    0x0424 0x76 0x0
    0x0428 0xff 0x0
    0x0830 0x1d 0x0
    0x0834 0x03 0x0
    0x0878 0x01 0x0
    0x087c 0x00 0x0
    0x0880 0x51 0x0
    0x08ac 0x34 0x0
    0x0a08 0x0c 0x0
    0x0a0c 0x0a 0x0
    0x0a18 0x04 0x0
    0x0a20 0x16 0x0
    0x0a34 0x00 0x0
    0x0a9c 0x80 0x0
    0x0aa0 0x7c 0x0
    0x0ab4 0x05 0x0
    0x0ae8 0x0a 0x0
    0x0b0c 0x0d 0x0
    0x0b20 0x0b 0x0
    0x0b48 0x1c 0x0
    0x0b88 0x20 0x0
    0x0b94 0x30 0x0
    0x0bdc 0x09 0x0
    0x0bf4 0x14 0x0
    0x0bf8 0xb3 0x0
    0x0bfc 0x58 0x0
    0x0c00 0x9a 0x0
    0x0c04 0x26 0x0
    0x0c08 0xb6 0x0
    0x0c0c 0xee 0x0
    0x0c10 0xdb 0x0
    0x0c14 0xdb 0x0
    0x0c18 0xa0 0x0
    0x0c1c 0xdf 0x0
    0x0c20 0x78 0x0
    0x0c24 0x76 0x0
    0x0c28 0xff 0x0
    0x0ea0 0x01 0x0
    0x0eb4 0x00 0x0
    0x0ec4 0x00 0x0
    0x0ec8 0x1f 0x0
    0x0ed4 0x12 0x0
    0x0ed8 0x12 0x0
    0x0edc 0xdb 0x0
    0x0ee0 0x9a 0x0
    0x0ee4 0x38 0x0
    0x0ee8 0xb6 0x0
    0x0eec 0x64 0x0
    0x0ef0 0x1f 0x0
    0x0ef4 0x1f 0x0
    0x0ef8 0x1f 0x0
    0x0efc 0x1f 0x0
    0x0f00 0x1f 0x0
    0x0f04 0x1f 0x0
    0x0f0c 0x1f 0x0
    0x0f14 0x1f 0x0
    0x0f1c 0x1f 0x0
    0x0f28 0x5b 0x0
    0x1000 0x26 0x0
    0x1004 0x03 0x0
    0x1010 0x06 0x0
    0x1014 0x16 0x0
    0x1018 0x36 0x0
    0x101c 0x04 0x0
    0x1020 0x0a 0x0
    0x1024 0x1a 0x0
    0x1028 0x68 0x0
    0x1030 0xab 0x0
    0x1034 0xaa 0x0
    0x1038 0x02 0x0
    0x103c 0x12 0x0
    0x1060 0xf8 0x0
    0x1064 0x01 0x0
    0x1070 0x06 0x0
    0x1074 0x16 0x0
    0x1078 0x36 0x0
    0x107c 0x0a 0x0
    0x1080 0x04 0x0
    0x1084 0x0d 0x0
    0x1088 0x41 0x0
    0x1090 0xab 0x0
    0x1094 0xaa 0x0
    0x1098 0x01 0x0
    0x109c 0x00 0x0
    0x10bc 0x0a 0x0
    0x10c0 0x01 0x0
    0x10cc 0x62 0x0
    0x10d0 0x02 0x0
    0x10d8 0x40 0x0
    0x10dc 0x14 0x0
    0x10e0 0x90 0x0
    0x10e4 0x82 0x0
    0x10f4 0x0f 0x0
    0x1110 0x08 0x0
    0x1120 0x46 0x0
    0x1124 0x04 0x0
    0x1140 0x14 0x0
    0x1164 0x34 0x0
    0x1170 0xa0 0x0
    0x1174 0x06 0x0
    0x1184 0x88 0x0
    0x1188 0x14 0x0
    0x1198 0x0f 0x0
    0x1378 0x2e 0x0
    0x1390 0xcc 0x0
    0x13f8 0x00 0x0
    0x13fc 0x22 0x0
    0x141c 0xc1 0x0
    0x1490 0x00 0x0
    0x14a0 0x16 0x0
    0x1508 0x02 0x0
    0x155c 0x2e 0x0
    0x157c 0x03 0x0
    0x1584 0x28 0x0
    0x13dc 0x04 0x0
    0x13e0 0x02 0x0
    0x1418 0xc0 0x0
    0x140c 0x1d 0x0
    0x158c 0x0f 0x0
    0x15ac 0xf2 0x0
    0x15c0 0xf2 0x0
    0x1200 0x00 0x0
    0x1244 0x03 0x0>;

  qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
     0x04D0 0x04D4 0x03C0 0x0630 0x0230
     0x0000>;
  qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x01F4 0x0730
     0x0734 0x0738 0x073C>;
  qcom,phy-debug-reg = <0x11CC 0x11D0 0x11D4 0x11D8 0x11DC
     0x11E0 0x11E4 0x11F8 0x00B8 0x08B8
     0x00C4 0x08C4 0x0464 0x0C64 0x1800
     0x1C00 0x1804 0x1C04 0x1808 0x1C08
     0x180C 0x1C0C 0x1810 0x1C10 0x1814
     0x1c14 0x1818 0x1C18 0x1A20 0x1E20
     0x1214 0x1218 0x121C 0x1220 0x1224
     0x1228 0x122C 0x1230 0x1234 0x1238
     0x123C 0x1400 0x1404>;
  pcie1_rp: pcie1_rp {
   reg = <0 0 0 0 0>;
  };
 };

 pcie1_msi: qcom,pcie1_msi@0x17110040 {
  status = "disabled";
  compatible = "qcom,pci-msi";
  msi-controller;
  reg = <0x17110040 0x0>;
  interrupt-parent = <&intc>;
  interrupts = <0 800 1>,
        <0 801 1>,
        <0 802 1>,
        <0 803 1>,
        <0 804 1>,
        <0 805 1>,
        <0 806 1>,
        <0 807 1>,
        <0 808 1>,
        <0 809 1>,
        <0 810 1>,
        <0 811 1>,
        <0 812 1>,
        <0 813 1>,
        <0 814 1>,
        <0 815 1>,
        <0 816 1>,
        <0 817 1>,
        <0 818 1>,
        <0 819 1>,
        <0 820 1>,
        <0 821 1>,
        <0 822 1>,
        <0 823 1>,
        <0 824 1>,
        <0 825 1>,
        <0 826 1>,
        <0 827 1>,
        <0 828 1>,
        <0 829 1>,
        <0 830 1>,
        <0 831 1>,
        <0 832 1>,
        <0 833 1>,
        <0 834 1>,
        <0 835 1>,
        <0 836 1>,
        <0 837 1>,
        <0 838 1>,
        <0 839 1>,
        <0 840 1>,
        <0 841 1>,
        <0 842 1>,
        <0 843 1>,
        <0 844 1>,
        <0 845 1>,
        <0 846 1>,
        <0 847 1>;
 };

 pcie_ep: qcom,pcie@0x40000000 {
  compatible = "qcom,pcie-ep";
   reg = <0x40002000 0x1000>,
    <0x40000000 0xf20>,
    <0x40000f20 0xa8>,
    <0x40001000 0x1000>,
    <0x1c08000 0x3000>,
    <0x1c0e000 0x2000>,
    <0x1c0b000 0x1000>;
   reg-names = "msi", "dm_core", "elbi", "iatu",
     "parf", "phy", "mmio";

   interrupts = <0 306 4>;
   interrupt-names = "int_global";

   pinctrl-names = "default";
   pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
         &pcie_ep_wake_default>;
   clkreq-gpio = <&tlmm 98 0>;
   perst-gpio = <&tlmm 97 0>;
   wake-gpio = <&tlmm 99 0>;

   gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;
   gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
   vreg-1p2-supply = <&pm_v6e_l3>;
   vreg-0p9-supply = <&pm_v6c_l3>;
   vreg-qref-supply = <&pm_v6e_l1>;
   vreg-mx-supply = <&VDD_MXA_LEVEL>;

   qcom,vreg-1p2-voltage-level = <1200000 1200000 26100>;
   qcom,vreg-0p9-voltage-level = <912000 880000 193000>;
   qcom,vreg-mx-voltage-level = <65535 256 0>;

   resets = <&gcc 8>,
    <&gcc 11>,
    <&gcc 9>,
    <&gcc 10>;
   reset-names = "pcie_core_reset",
     "pcie_phy_reset",
     "pcie_link_down_reset",
     "pcie_phy_nocsr_com_phy_reset";

   interconnect-names = "icc_path";
   interconnects = <&pcie_noc 46 &mc_virt 512>;

   clocks = <&gcc 52>,
    <&rpmhcc 0>,
    <&gcc 44>,
    <&gcc 46>,
    <&gcc 47>,
    <&gcc 54>,
    <&tcsrcc 1>,
    <&gcc 55>,
    <&gcc 14>,
    <&gcc 0>,
    <&gcc 12>,
    <&gcc 53>,
    <&pcie_1_pipe_clk>,
    <&gcc 48>;
   clock-names = "pcie_pipe_clk", "pcie_0_ref_clk_src",
     "pcie_aux_clk", "pcie_cfg_ahb_clk",
     "pcie_mstr_axi_clk", "pcie_slv_axi_clk",
     "pcie_ldo", "pcie_slv_q2a_axi_clk",
     "pcie_ddrss_sf_tbu_clk",
     "pcie_aggre_noc_0_axi_clk",
     "gcc_cnoc_pcie_sf_axi_clk", "pcie_pipe_clk_mux",
     "pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";

   qcom,pcie-vendor-id = /bits/ 16 <0x17cb>;
   qcom,pcie-device-id = /bits/ 16 <0x0111>;
   qcom,pcie-link-speed = <4>;
   qcom,pcie-phy-ver = <8>;
   qcom,no-path-from-ipa-to-pcie;
   qcom,pcie-aggregated-irq;
   qcom,pcie-mhi-a7-irq;
   qcom,tcsr-not-supported;
   qcom,phy-status-reg2 = <0x1214>;
   qcom,mhi-soc-reset-offset = <0x68c>;
   qcom,aux-clk = <0x14>;

   iommus = <&apps_smmu 0x1480 0x0>;
   qcom,iommu-dma = "bypass";

   qcom,phy-init = <0x1240 0x01 0x0
     0x0030 0x1d 0x0
     0x0034 0x03 0x0
     0x0078 0x01 0x0
     0x007c 0x00 0x0
     0x0080 0x51 0x0
     0x00ac 0x34 0x0
     0x0208 0x0c 0x0
     0x020c 0x0a 0x0
     0x0218 0x04 0x0
     0x0220 0x16 0x0
     0x0234 0x00 0x0
     0x029c 0x80 0x0
     0x02a0 0x7c 0x0
     0x02b4 0x05 0x0
     0x02e8 0x0a 0x0
     0x030c 0x0d 0x0
     0x0320 0x0b 0x0
     0x0348 0x1c 0x0
     0x0388 0x20 0x0
     0x0394 0x30 0x0
     0x03dc 0x09 0x0
     0x03f4 0x14 0x0
     0x03f8 0xb3 0x0
     0x03fc 0x58 0x0
     0x0400 0x9a 0x0
     0x0404 0x26 0x0
     0x0408 0xb6 0x0
     0x040c 0xee 0x0
     0x0410 0xdb 0x0
     0x0414 0xdb 0x0
     0x0418 0xa0 0x0
     0x041c 0xdf 0x0
     0x0420 0x78 0x0
     0x0424 0x76 0x0
     0x0428 0xff 0x0
     0x0830 0x1d 0x0
     0x0834 0x03 0x0
     0x0878 0x01 0x0
     0x087c 0x00 0x0
     0x0880 0x51 0x0
     0x08ac 0x34 0x0
     0x0a08 0x0c 0x0
     0x0a0c 0x0a 0x0
     0x0a18 0x04 0x0
     0x0a20 0x16 0x0
     0x0a34 0x00 0x0
     0x0a9c 0x80 0x0
     0x0aa0 0x7c 0x0
     0x0ab4 0x05 0x0
     0x0ae8 0x0a 0x0
     0x0b0c 0x0d 0x0
     0x0b20 0x0b 0x0
     0x0b48 0x1c 0x0
     0x0b88 0x20 0x0
     0x0b94 0x30 0x0
     0x0bdc 0x09 0x0
     0x0bf4 0x14 0x0
     0x0bf8 0xb3 0x0
     0x0bfc 0x58 0x0
     0x0c00 0x9a 0x0
     0x0c04 0x26 0x0
     0x0c08 0xb6 0x0
     0x0c0c 0xee 0x0
     0x0c10 0xdb 0x0
     0x0c14 0xdb 0x0
     0x0c18 0xa0 0x0
     0x0c1c 0xdf 0x0
     0x0c20 0x78 0x0
     0x0c24 0x76 0x0
     0x0c28 0xff 0x0
     0x0ea0 0x01 0x0
     0x0eb4 0x00 0x0
     0x0ec4 0x00 0x0
     0x0ec8 0x1f 0x0
     0x0ed4 0x12 0x0
     0x0ed8 0x12 0x0
     0x0edc 0xdb 0x0
     0x0ee0 0x9a 0x0
     0x0ee4 0x38 0x0
     0x0ee8 0xb6 0x0
     0x0eec 0x64 0x0
     0x0ef0 0x1f 0x0
     0x0ef4 0x1f 0x0
     0x0ef8 0x1f 0x0
     0x0efc 0x1f 0x0
     0x0f00 0x1f 0x0
     0x0f04 0x1f 0x0
     0x0f0c 0x1f 0x0
     0x0f14 0x1f 0x0
     0x0f1c 0x1f 0x0
     0x0f28 0x5b 0x0
     0x1010 0x28 0x0
     0x1014 0x17 0x0
     0x1018 0x03 0x0
     0x101c 0x04 0x0
     0x1020 0xff 0x0
     0x1024 0x09 0x0
     0x1028 0x28 0x0
     0x103c 0x12 0x0
     0x1040 0xfb 0x0
     0x1044 0x00 0x0
     0x1070 0x34 0x0
     0x1074 0x11 0x0
     0x1078 0x01 0x0
     0x107c 0x0a 0x0
     0x1080 0xff 0x0
     0x1084 0x04 0x0
     0x1088 0x19 0x0
     0x109c 0x00 0x0
     0x10a0 0xfb 0x0
     0x10a4 0x00 0x0
     0x10bc 0x06 0x0
     0x10d8 0x40 0x0
     0x10dc 0x14 0x0
     0x10e4 0x07 0x0
     0x10f4 0x1f 0x0
     0x1110 0x00 0x0
     0x1120 0x46 0x0
     0x1124 0x04 0x0
     0x1140 0x14 0x0
     0x1170 0xa0 0x0
     0x1174 0x06 0x0
     0x1184 0x88 0x0
     0x1188 0x14 0x0
     0x1198 0x0f 0x0
     0x1378 0x2e 0x0
     0x1390 0xcc 0x0
     0x13f8 0x00 0x0
     0x13fc 0x22 0x0
     0x14a0 0x16 0x0
     0x14f0 0x27 0x0
     0x14f4 0x27 0x0
     0x1508 0x02 0x0
     0x155c 0x2e 0x0
     0x157c 0x03 0x0
     0x1584 0x28 0x0
     0x13dc 0x04 0x0
     0x13e0 0x02 0x0
     0x1418 0xc0 0x0
     0x158c 0x0f 0x0
     0x15ac 0xf2 0x0
     0x15c0 0xf2 0x0
     0x1370 0x17 0x0
     0x1200 0x00 0x0
     0x1244 0x03 0x0>;

   status = "disabled";
 };

 mhi_device: mhi_dev@1c0b000 {
  compatible = "qcom,msm-mhi-dev";
  reg = <0x1c0b000 0x1000>;
  reg-names = "mhi_mmio_base";
  qcom,use-mhi-dma-software-channel;
  qcom,mhi-ep-msi = <0>;
  qcom,mhi-version = <0x1000000>;
  interrupts = <0 440 4>;
  interrupt-names = "mhi-device-inta";
  qcom,mhi-ifc-id = <0x011117cb>;
  qcom,mhi-local-pa-base = <0x4 0x00000000>;
  qcom,no-path-from-ipa-to-pcie;
  qcom,mhi-config-iatu;
  qcom,mhi-interrupt;
  qcom,no-m0-timeout;
  status = "disabled";
 };

 mhi_net_device: qcom,mhi_net_dev {
  compatible = "qcom,msm-mhi-dev-net";
  qcom,tx_rx_reqs = <1024>;
  status = "disabled";
 };
};
# 3672 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-mhi.dtsi" 1
&pcie1_rp {
 #address-cells = <5>;
 #size-cells = <0>;

 mhi_0: qcom,mhi@0 {
  reg = <0 0 0 0 0 >;

  status = "disabled";

  pci-ids = "17cb:0111";


  qcom,iommu-group = <&mhi_0_iommu_group>;



  mhi,max-channels = <2>;
  mhi,timeout = <2000>;
  mhi,name = "sxr";

  #address-cells = <1>;
  #size-cells = <1>;

  interconnects = <&pcie_noc 46 &mc_virt 512>;
  interconnect-names = "pcie_to_ddr";

  qcom,mhi-bus-bw-cfg = <0 0>,
    <250000 0>,
    <500000 0>,
    <1000000 0>,
    <2000000 0>;

  mhi_0_iommu_group: mhi_0_iommu_group {
   qcom,iommu-dma-addr-pool = <0x20000000 0x1fffffff>;
   qcom,iommu-dma = "atomic";
   qcom,iommu-pagetable = "coherent";
  };
 };
};
# 3673 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/msm-rdbg.dtsi" 1
&soc {

 qcom,smp2p_interrupt_rdbg_2_out {
  compatible = "qcom,smp2p-interrupt-rdbg-2-out";
  qcom,smem-states = <&smp2p_rdbg2_out 0>;
  qcom,smem-state-names = "rdbg-smp2p-out";
 };

 qcom,smp2p_interrupt_rdbg_2_in {
  compatible = "qcom,smp2p-interrupt-rdbg-2-in";
  interrupts-extended = <&smp2p_rdbg2_in 0 0>;
  interrupt-names = "rdbg-smp2p-in";
 };

 qcom,smp2p_interrupt_rdbg_5_out {
  compatible = "qcom,smp2p-interrupt-rdbg-5-out";
  qcom,smem-states = <&smp2p_rdbg5_out 0>;
  qcom,smem-state-names = "rdbg-smp2p-out";
 };

 qcom,smp2p_interrupt_rdbg_5_in {
  compatible = "qcom,smp2p-interrupt-rdbg-5-in";
  interrupts-extended = <&smp2p_rdbg5_in 0 0>;
  interrupt-names = "rdbg-smp2p-in";
 };
};
# 3674 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-thermal.dtsi" 1
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal_qti.h" 1






# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 8 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal_qti.h" 2
# 2 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-thermal.dtsi" 2

&msm_gpu {
 #cooling-cells = <2>;
};

&soc {
 tsens0: tsens0@c271000 {
  compatible = "qcom,tsens-v2";
  reg = <0x0c271000 0x1ff>,
   <0x0c222000 0x1ff>;
  #qcom,sensors = <16>;
  interrupts = <0 506 4>,
        <0 640 4>;
  interrupt-names = "uplow","critical";
  #thermal-sensor-cells = <1>;
 };

 tsens1: tsens1@c272000 {
  compatible = "qcom,tsens-v2";
  reg = <0x0c272000 0x1ff>,
   <0x0c223000 0x1ff>;
  #qcom,sensors = <16>;
  interrupts = <0 507 4>,
        <0 641 4>;
  interrupt-names = "uplow","critical";
  #thermal-sensor-cells = <1>;
 };

 tsens2: tsens2@c273000 {
  compatible = "qcom,tsens-v2";
  reg = <0x0c273000 0x1ff>,
   <0x0c224000 0x1ff>;
  #qcom,sensors = <9>;
  interrupts = <0 508 4>,
        <0 642 4>;
  interrupt-names = "uplow","critical";
  #thermal-sensor-cells = <1>;
 };

 qcom,cpu-pause {
  compatible = "qcom,thermal-pause";

  cpu1_pause: cpu1-pause {
   qcom,cpus = <&CPU1>;
   qcom,cdev-alias = "thermal-pause-2";
   #cooling-cells = <2>;
  };

  cpu2_pause: cpu2-pause {
   qcom,cpus = <&CPU2>;
   qcom,cdev-alias = "thermal-pause-4";
   #cooling-cells = <2>;
  };

  cpu3_pause: cpu3-pause {
   qcom,cpus = <&CPU3>;
   qcom,cdev-alias = "thermal-pause-8";
   #cooling-cells = <2>;
  };

  cpu4_pause: cpu4-pause {
   qcom,cpus = <&CPU4>;
   qcom,cdev-alias = "thermal-pause-10";
   #cooling-cells = <2>;
  };

  cpu5_pause: cpu5-pause {
   qcom,cpus = <&CPU5>;
   qcom,cdev-alias = "thermal-pause-20";
   #cooling-cells = <2>;
  };

  cpu6_pause: cpu6-pause {
   qcom,cpus = <&CPU6>;
   qcom,cdev-alias = "thermal-pause-40";
   #cooling-cells = <2>;
  };

  cpu7_pause: cpu7-pause {
   qcom,cpus = <&CPU7>;
   qcom,cdev-alias = "thermal-pause-80";
   #cooling-cells = <2>;
  };

  APC1_pause: apc1-pause {
   qcom,cpus = <&CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
   qcom,cdev-alias = "thermal-pause-F8";
   #cooling-cells = <2>;
  };

  cpu_3_4_5_pause: cpu-3-4-5-pause {
   qcom,cpus = <&CPU3 &CPU4 &CPU5>;
   qcom,cdev-alias = "thermal-pause-38";
   #cooling-cells = <2>;
  };

  cpu_6_7_pause: cpu-6-7-pause {
   qcom,cpus = <&CPU6 &CPU7>;
   qcom,cdev-alias = "thermal-pause-C0";
   #cooling-cells = <2>;
  };


  pause-cpu1 {
   qcom,cpus = <&CPU1>;
   qcom,cdev-alias = "pause-cpu1";
  };

  pause-cpu2 {
   qcom,cpus = <&CPU2>;
   qcom,cdev-alias = "pause-cpu2";
  };

  pause-cpu3 {
   qcom,cpus = <&CPU3>;
   qcom,cdev-alias = "pause-cpu3";
  };

  pause-cpu4 {
   qcom,cpus = <&CPU4>;
   qcom,cdev-alias = "pause-cpu4";
  };

  pause-cpu5 {
   qcom,cpus = <&CPU5>;
   qcom,cdev-alias = "pause-cpu5";
  };

  pause-cpu6 {
   qcom,cpus = <&CPU6>;
   qcom,cdev-alias = "pause-cpu6";
  };

  pause-cpu7 {
   qcom,cpus = <&CPU7>;
   qcom,cdev-alias = "pause-cpu7";
  };
 };

 qcom,cpu-hotplug {
  compatible = "qcom,cpu-hotplug";

  cpu1_hotplug: cpu1-hotplug {
   qcom,cpu = <&CPU1>;
   qcom,cdev-alias = "cpu-hotplug1";
   #cooling-cells = <2>;
  };

  cpu2_hotplug: cpu2-hotplug {
   qcom,cpu = <&CPU2>;
   qcom,cdev-alias = "cpu-hotplug2";
   #cooling-cells = <2>;
  };

  cpu3_hotplug: cpu3-hotplug {
   qcom,cpu = <&CPU3>;
   qcom,cdev-alias = "cpu-hotplug3";
   #cooling-cells = <2>;
  };

  cpu4_hotplug: cpu4-hotplug {
   qcom,cpu = <&CPU4>;
   qcom,cdev-alias = "cpu-hotplug4";
   #cooling-cells = <2>;
  };

  cpu5_hotplug: cpu5-hotplug {
   qcom,cpu = <&CPU5>;
   qcom,cdev-alias = "cpu-hotplug5";
   #cooling-cells = <2>;
  };

  cpu6_hotplug: cpu6-hotplug {
   qcom,cpu = <&CPU6>;
   qcom,cdev-alias = "cpu-hotplug6";
   #cooling-cells = <2>;
  };

  cpu7_hotplug: cpu7-hotplug {
   qcom,cpu = <&CPU7>;
   qcom,cdev-alias = "cpu-hotplug7";
   #cooling-cells = <2>;
  };
 };

 qcom,cpu-voltage-cdev {
  compatible = "qcom,cc-cooling-devices";
  apc1_cluster: thermal-cluster-1-2 {
   qcom,cluster0 = <&CPU3 &CPU4 &CPU5 &CPU6>;
   qcom,cluster1 = <&CPU7>;
   #cooling-cells = <2>;
  };
 };

 ddr_cdev: qcom,ddr-cdev {
  compatible = "qcom,ddr-cooling-device";
  #cooling-cells = <2>;
  qcom,bus-width = <4>;
  qcom,freq-table =
   < 547000 >,
   < 768000 >,
   < 1555200 >,
   < 1708800 >,
   < 2092800 >,
   < 2736000 >,
   < 3196800 >,
   < 3744000 >,
   < 4262400 >;
  interconnects = <&mc_virt 3 &mc_virt 512>;
 };

 qcom,limits-dcvs {
  compatible = "qcom,msm-hw-limits";
  isens_vref_0p8-supply = <&pm_v6e_l1_ao>;
  isens-vref-0p8-settings = <880000 880000 30000>;
  isens_vref_1p8-supply = <&pm_v6e_l3_ao>;
  isens-vref-1p8-settings = <1200000 1200000 8000>;
 };

 qmi_tmd: qmi-tmd-devices {
  compatible = "qcom,qmi-cooling-devices";
  cdsp {
   qcom,instance-id = <0x43>;

   cdsp_sw: cdsp {
    qcom,qmi-dev-name = "cdsp_sw";
    #cooling-cells = <2>;
   };

   cdsp_hw: cdsp_hw {
    qcom,qmi-dev-name = "cdsp_hw";
    #cooling-cells = <2>;
   };
  };
 };

 qcom,userspace-cdev {
  compatible = "qcom,userspace-cooling-devices";

  display_fps: display-fps {
   qcom,max-level = <16>;
   #cooling-cells = <2>;
  };
 };

 qcom,devfreq-cdev {
  compatible = "qcom,devfreq-cdev";
  qcom,devfreq = <&msm_gpu>;
 };

 qcom,cpufreq-cdev {
  compatible = "qcom,cpufreq-cdev";
  cpu-cluster0 {
   qcom,cpus = <&CPU0 &CPU1 &CPU2>;
  };

  cpu-cluster1 {
   qcom,cpus = <&CPU3 &CPU4 &CPU5 &CPU6>;
  };

  cpu-cluster2 {
   qcom,cpus = <&CPU7>;
  };
 };

 limits_stat: limits-stat {
  compatible = "qcom,limits-stat";
  qcom,limits-stat-sensor-names = "cpu-0-0",
      "cpu-0-1",
      "cpu-0-2",
      "cpu-1-0",
      "cpu-1-1",
      "cpu-1-2",
      "cpu-1-3",
      "cpu-1-4",
      "gpuss-0",
      "gpuss-1",
      "nspss-0",
      "nspss-1",
      "nspss-2";
 };
};

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-thermal-modem.dtsi" 1
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/thermal/thermal_qti.h" 1
# 2 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-thermal-modem.dtsi" 2

&soc {
 qmi-tmd-devices {
  compatible = "qcom,qmi-cooling-devices";

  modem {
   qcom,instance-id = <0x0>;

   modem_lte_dsc: modem_lte_dsc {
    qcom,qmi-dev-name = "modem_lte_dsc";
    #cooling-cells = <2>;
   };

   modem_nr_dsc: modem_nr_dsc {
    qcom,qmi-dev-name = "modem_nr_dsc";
    #cooling-cells = <2>;
   };

   modem_nr_scg_dsc: modem_nr_scg_dsc {
    qcom,qmi-dev-name = "modem_nr_scg_dsc";
    #cooling-cells = <2>;
   };

   sdr0_lte_dsc: sdr0_lte_dsc {
    qcom,qmi-dev-name = "sdr0_lte_dsc";
    #cooling-cells = <2>;
   };

   sdr1_lte_dsc: sdr1_lte_dsc {
    qcom,qmi-dev-name = "sdr1_lte_dsc";
    #cooling-cells = <2>;
   };

   sdr0_nr_dsc: sdr0_nr_dsc {
    qcom,qmi-dev-name = "sdr0_nr_dsc";
    #cooling-cells = <2>;
   };

   sdr1_nr_dsc: sdr1_nr_dsc {
    qcom,qmi-dev-name = "sdr1_nr_dsc";
    #cooling-cells = <2>;
   };

   sdr0_nr_scg_dsc: sdr0_nr_scg_dsc {
    qcom,qmi-dev-name = "sdr0_nr_scg_dsc";
    #cooling-cells = <2>;
   };

   sdr1_nr_scg_dsc: sdr1_nr_scg_dsc {
    qcom,qmi-dev-name = "sdr1_nr_scg_dsc";
    #cooling-cells = <2>;
   };

   pa_lte_sdr0_dsc: pa_lte_sdr0_dsc {
    qcom,qmi-dev-name = "pa_lte_sdr0_dsc";
    #cooling-cells = <2>;
   };

   pa_lte_sdr1_dsc: pa_lte_sdr1_dsc {
    qcom,qmi-dev-name = "pa_lte_sdr1_dsc";
    #cooling-cells = <2>;
   };

   pa_nr_sdr0_dsc: pa_nr_sdr0_dsc {
    qcom,qmi-dev-name = "pa_nr_sdr0_dsc";
    #cooling-cells = <2>;
   };

   pa_nr_sdr1_dsc: pa_nr_sdr1_dsc {
    qcom,qmi-dev-name = "pa_nr_sdr1_dsc";
    #cooling-cells = <2>;
   };

   pa_nr_sdr0_scg_dsc: pa_nr_sdr0_scg_dsc {
    qcom,qmi-dev-name = "pa_nr_sdr0_scg_dsc";
    #cooling-cells = <2>;
   };

   pa_nr_sdr1_scg_dsc: pa_nr_sdr1_scg_dsc {
    qcom,qmi-dev-name = "pa_nr_sdr1_scg_dsc";
    #cooling-cells = <2>;
   };

   mmw0_dsc: mmw0_dsc {
    qcom,qmi-dev-name = "mmw0_dsc";
    #cooling-cells = <2>;
   };

   mmw1_dsc: mmw1_dsc {
    qcom,qmi-dev-name = "mmw1_dsc";
    #cooling-cells = <2>;
   };

   mmw2_dsc: mmw2_dsc {
    qcom,qmi-dev-name = "mmw2_dsc";
    #cooling-cells = <2>;
   };

   mmw3_dsc: mmw3_dsc {
    qcom,qmi-dev-name = "mmw3_dsc";
    #cooling-cells = <2>;
   };

   mmw_ific_dsc: mmw_ific_dsc {
    qcom,qmi-dev-name = "mmw_ific_dsc";
    #cooling-cells = <2>;
   };

   qmi_wlan: wlan {
    qcom,qmi-dev-name = "wlan";
    #cooling-cells = <2>;
   };

   modem_bw_backoff: modem_bw_backoff {
    qcom,qmi-dev-name = "modem_bw_backoff";
    #cooling-cells = <2>;
   };

   modem_vdd: modem_vdd {
    qcom,qmi-dev-name = "cpuv_restriction_cold";
    #cooling-cells = <2>;
   };

   modem_lte_sub1_dsc: modem_lte_sub1_dsc {
    qcom,qmi-dev-name = "modem_lte_sub1_dsc";
    #cooling-cells = <2>;
   };

   modem_nr_sub1_dsc: modem_nr_sub1_dsc {
    qcom,qmi-dev-name = "modem_nr_sub1_dsc";
    #cooling-cells = <2>;
   };

   modem_nr_scg_sub1_dsc: modem_nr_scg_sub1_dsc {
    qcom,qmi-dev-name = "modem_nr_scg_sub1_dsc";
    #cooling-cells = <2>;
   };

   pa_lte_sdr0_sub1_dsc: pa_lte_sdr0_sub1_dsc {
    qcom,qmi-dev-name = "pa_lte_sdr0_sub1_dsc";
    #cooling-cells = <2>;
   };

   pa_lte_sdr1_sub1_dsc: pa_lte_sdr1_sub1_dsc {
    qcom,qmi-dev-name = "pa_lte_sdr1_sub1_dsc";
    #cooling-cells = <2>;
   };

   pa_nr_sdr0_sub1_dsc: pa_nr_sdr0_sub1_dsc {
    qcom,qmi-dev-name = "pa_nr_sdr0_sub1_dsc";
    #cooling-cells = <2>;
   };

   pa_nr_sdr1_sub1_dsc: pa_nr_sdr1_sub1_dsc {
    qcom,qmi-dev-name = "pa_nr_sdr1_sub1_dsc";
    #cooling-cells = <2>;
   };
  };
 };

 qmi_sensor: qmi-ts-sensors {
  compatible = "qcom,qmi-sensors";
  #thermal-sensor-cells = <1>;

  modem {
   qcom,instance-id = <0x0>;
   qcom,qmi-sensor-names = "pa",
      "pa_1",
      "modem_bcl_warn",
      "sdr0_pa",
      "sdr0",
      "sdr1_pa",
      "sdr1",
      "mmw0",
      "mmw1",
      "mmw2",
      "mmw3",
      "mmw_pa1",
      "mmw_pa2",
      "mmw_pa3",
      "mmw_ific0",
      "epm0",
      "epm1",
      "epm2",
      "epm3",
      "epm4",
      "epm5",
      "epm6",
      "epm7",
      "sdr_mmw_therm",
      "sub1_modem_cfg",
      "sub1_lte_cc",
      "sub1_mcg_fr1_cc",
      "sub1_mcg_fr2_cc",
      "sub1_scg_fr1_cc",
      "sub1_scg_fr2_cc";
  };
 };
};

&thermal_zones {
 pa {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +0)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 pa1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +1)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 bcl_warn {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +31)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sdr0_pa {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +72)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sdr0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +38)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sdr1_pa {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +73)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sdr1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +45)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +46)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +47)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw2 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +48)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw3 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +49)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw_pa1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +26)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw_pa2 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +27)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw_pa3 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +28)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 mmw_ific0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +50)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +64)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +65)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm2 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +66)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm3 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +67)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm4 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +68)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm5 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +69)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm6 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +70)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 epm7 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +71)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sdr_mmw_therm {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +29)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sub1_modem_cfg {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +51)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sub1_lte_cc {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +52)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sub1_mcg_fr1_cc {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +53)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sub1_mcg_fr2_cc {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +54)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sub1_scg_fr1_cc {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +55)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };

 sub1_scg_fr2_cc {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&qmi_sensor
    (0x0 +56)>;
  trips {
   thermal-engine-config0 {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };
  };
 };
};
# 286 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-thermal.dtsi" 2

&thermal_zones {
 aoss-0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 0>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 cpuss-0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 1>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 cpuss-1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 2>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 cpuss-2 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 3>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 cpuss-3 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 4>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 cpu-1-0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 5>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu3_emerg0: cpu3-emerg0-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu3_emerg0_1: cpu3-emerg0-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu10_cdev {
    trip = <&cpu3_emerg0>;
    cooling-device = <&cpu3_pause 1 1>;
   };

   cpu10_cdev1 {
    trip = <&cpu3_emerg0_1>;
    cooling-device = <&cpu3_hotplug 1 1>;
   };
  };
 };

 cpu-1-1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 6>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu3_emerg1: cpu3-emerg1-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu3_emerg1_1: cpu3-emerg1-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu11_cdev {
    trip = <&cpu3_emerg1>;
    cooling-device = <&cpu3_pause 1 1>;
   };

   cpu11_cdev1 {
    trip = <&cpu3_emerg1_1>;
    cooling-device = <&cpu3_hotplug 1 1>;
   };
  };
 };

 cpu-1-2 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 7>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu4_emerg0: cpu4-emerg0-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu4_emerg0_1: cpu4-emerg0-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu12_cdev {
    trip = <&cpu4_emerg0>;
    cooling-device = <&cpu4_pause 1 1>;
   };

   cpu12_cdev1 {
    trip = <&cpu4_emerg0_1>;
    cooling-device = <&cpu4_hotplug 1 1>;
   };
  };
 };

 cpu-1-3 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 8>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu4_emerg1: cpu4-emerg1-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu4_emerg1_1: cpu4-emerg1-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu13_cdev {
    trip = <&cpu4_emerg1>;
    cooling-device = <&cpu4_pause 1 1>;
   };

   cpu13_cdev1 {
    trip = <&cpu4_emerg1_1>;
    cooling-device = <&cpu4_hotplug 1 1>;
   };
  };
 };

 cpu-1-4 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 9>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu5_emerg0: cpu5-emerg0-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu5_emerg0_1: cpu5-emerg0-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu14_cdev {
    trip = <&cpu5_emerg0>;
    cooling-device = <&cpu5_pause 1 1>;
   };

   cpu14_cdev1 {
    trip = <&cpu5_emerg0_1>;
    cooling-device = <&cpu5_hotplug 1 1>;
   };
  };
 };

 cpu-1-5 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 10>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu5_emerg1: cpu5-emerg1-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu5_emerg1_1: cpu5-emerg1-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu15_cdev {
    trip = <&cpu5_emerg1>;
    cooling-device = <&cpu5_pause 1 1>;
   };

   cpu15_cdev1 {
    trip = <&cpu5_emerg1_1>;
    cooling-device = <&cpu5_hotplug 1 1>;
   };
  };
 };

 cpu-1-6 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 11>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu6_emerg0: cpu6-emerg0-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu6_emerg0_1: cpu6-emerg0-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu16_cdev {
    trip = <&cpu6_emerg0>;
    cooling-device = <&cpu6_pause 1 1>;
   };

   cpu16_cdev1 {
    trip = <&cpu6_emerg0_1>;
    cooling-device = <&cpu6_hotplug 1 1>;
   };
  };
 };

 cpu-1-7 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 12>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu6_emerg1: cpu6-emerg1-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu6_emerg1_1: cpu6-emerg1-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu17_cdev {
    trip = <&cpu6_emerg1>;
    cooling-device = <&cpu6_pause 1 1>;
   };

   cpu17_cdev1 {
    trip = <&cpu6_emerg1_1>;
    cooling-device = <&cpu6_hotplug 1 1>;
   };
  };
 };

 cpu-1-8 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 13>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu7_emerg0: cpu7-emerg0-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu7_emerg0_1: cpu7-emerg0-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu18_cdev {
    trip = <&cpu7_emerg0>;
    cooling-device = <&cpu7_pause 1 1>;
   };

   cpu18_cdev1 {
    trip = <&cpu7_emerg0_1>;
    cooling-device = <&cpu7_hotplug 1 1>;
   };
  };
 };

 cpu-1-9 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 14>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu7_emerg1: cpu7-emerg1-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu7_emerg1_1: cpu7-emerg1-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu19_cdev {
    trip = <&cpu7_emerg1>;
    cooling-device = <&cpu7_pause 1 1>;
   };

   cpu19_cdev1 {
    trip = <&cpu7_emerg1_1>;
    cooling-device = <&cpu7_hotplug 1 1>;
   };
  };
 };

 cpu-1-10 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens0 15>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu7_emerg2: cpu7-emerg2-cfg {
    temperature = <108000>;
    hysteresis = <8000>;
    type = "passive";
   };

   cpu7_emerg2_1: cpu7-emerg2-1-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu110_cdev {
    trip = <&cpu7_emerg2>;
    cooling-device = <&cpu7_pause 1 1>;
   };

   cpu110_cdev1 {
    trip = <&cpu7_emerg2_1>;
    cooling-device = <&cpu7_hotplug 1 1>;
   };
  };
 };

 aoss-1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 0>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 cpu-0-0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 1>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 cpu-0-1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 2>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu1_emerg: cpu1-emerg-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   cpu1_emerg1: cpu1-emerg1-cfg {
    temperature = <112000>;
    hysteresis = <12000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu01_cdev {
    trip = <&cpu1_emerg>;
    cooling-device = <&cpu1_pause 1 1>;
   };

   cpu01_cdev1 {
    trip = <&cpu1_emerg1>;
    cooling-device = <&cpu1_hotplug 1 1>;
   };
  };
 };

 cpu-0-2 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 3>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   cpu2_emerg: cpu2-emerg-cfg {
    temperature = <110000>;
    hysteresis = <10000>;
    type = "passive";
   };

   cpu2_emerg1: cpu2-emerg1-cfg {
    temperature = <112000>;
    hysteresis = <12000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   cpu02_cdev {
    trip = <&cpu2_emerg>;
    cooling-device = <&cpu2_pause 1 1>;
   };

   cpu02_cdev1 {
    trip = <&cpu2_emerg1>;
    cooling-device = <&cpu2_hotplug 1 1>;
   };
  };
 };

 nspss-0 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 4>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   nspss_0_config: junction-config {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   nsp_cdev {
    trip = <&nspss_0_config>;
    cooling-device = <&cdsp_sw (~0)
       (~0)>;
   };
  };
 };

 nspss-1 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 5>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   nspss_1_config: junction-config {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   nsp_cdev {
    trip = <&nspss_1_config>;
    cooling-device = <&cdsp_sw (~0)
       (~0)>;
   };
  };
 };

 nspss-2 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 6>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   nspss_2_config: junction-config {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   nsp_cdev {
    trip = <&nspss_2_config>;
    cooling-device = <&cdsp_sw (~0)
       (~0)>;
   };
  };
 };

 nspss-3 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 7>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   nspss_3_config: junction-config {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   nsp_cdev {
    trip = <&nspss_3_config>;
    cooling-device = <&cdsp_sw (~0)
       (~0)>;
   };
  };
 };

 video {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 8>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 ddr {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 9>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   ddr_config0: ddr0-config {
    temperature = <90000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gold_cdev0 {
    trip = <&ddr_config0>;
    cooling-device = <&CPU3
     (~0) (~0)>;
   };

   gold_cdev1 {
    trip = <&ddr_config0>;
    cooling-device = <&CPU4
     (~0) (~0)>;
   };

   gold_cdev2 {
    trip = <&ddr_config0>;
    cooling-device = <&CPU5
     (~0) (~0)>;
   };

   gold_cdev3 {
    trip = <&ddr_config0>;
    cooling-device = <&CPU6
     (~0) (~0)>;
   };

   gold_plus_cdev {
    trip = <&ddr_config0>;
    cooling-device = <&CPU7
     (~0) (~0)>;
   };

   ddr_cdev {
    trip = <&ddr_config0>;
    cooling-device = <&ddr_cdev 5 5>;
   };
  };
 };

 mdmss-0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 10>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   mdmss0_config0: mdmss0-config0 {
    temperature = <102000>;
    hysteresis = <3000>;
    type = "passive";
   };

   mdmss0_config1: mdmss0-config1 {
    temperature = <105000>;
    hysteresis = <3000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   lte_cdev0 {
    trip = <&mdmss0_config0>;
    cooling-device = <&modem_lte_dsc 8 8>;
   };

   nr_scg_cdev0 {
    trip = <&mdmss0_config0>;
    cooling-device = <&modem_nr_scg_dsc 10 10>;
   };

   nr_cdev0 {
    trip = <&mdmss0_config0>;
    cooling-device = <&modem_nr_dsc 6 6>;
   };

   lte_cdev2 {
    trip = <&mdmss0_config1>;
    cooling-device = <&modem_lte_dsc 255 255>;
   };

   nr_cdev2 {
    trip = <&mdmss0_config1>;
    cooling-device = <&modem_nr_dsc 255 255>;
   };
  };
 };

 mdmss-1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 11>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   mdmss1_config0: mdmss1-config0 {
    temperature = <102000>;
    hysteresis = <3000>;
    type = "passive";
   };

   mdmss1_config1: mdmss1-config1 {
    temperature = <105000>;
    hysteresis = <3000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   lte_cdev0 {
    trip = <&mdmss1_config0>;
    cooling-device = <&modem_lte_dsc 8 8>;
   };

   nr_scg_cdev0 {
    trip = <&mdmss1_config0>;
    cooling-device = <&modem_nr_scg_dsc 10 10>;
   };

   nr_cdev0 {
    trip = <&mdmss1_config0>;
    cooling-device = <&modem_nr_dsc 6 6>;
   };

   lte_cdev2 {
    trip = <&mdmss1_config1>;
    cooling-device = <&modem_lte_dsc 255 255>;
   };

   nr_cdev2 {
    trip = <&mdmss1_config1>;
    cooling-device = <&modem_nr_dsc 255 255>;
   };
  };
 };

 mdmss-2 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 12>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   mdmss2_config0: mdmss2-config0 {
    temperature = <102000>;
    hysteresis = <3000>;
    type = "passive";
   };

   mdmss2_config1: mdmss2-config1 {
    temperature = <105000>;
    hysteresis = <3000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   lte_cdev0 {
    trip = <&mdmss2_config0>;
    cooling-device = <&modem_lte_dsc 8 8>;
   };

   nr_scg_cdev0 {
    trip = <&mdmss2_config0>;
    cooling-device = <&modem_nr_scg_dsc 10 10>;
   };

   nr_cdev0 {
    trip = <&mdmss2_config0>;
    cooling-device = <&modem_nr_dsc 6 6>;
   };

   lte_cdev2 {
    trip = <&mdmss2_config1>;
    cooling-device = <&modem_lte_dsc 255 255>;
   };

   nr_cdev2 {
    trip = <&mdmss2_config1>;
    cooling-device = <&modem_nr_dsc 255 255>;
   };
  };
 };

 mdmss-3 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 13>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   mdmss3_config0: mdmss3-config0 {
    temperature = <102000>;
    hysteresis = <3000>;
    type = "passive";
   };

   mdmss3_config1: mdmss3-config1 {
    temperature = <105000>;
    hysteresis = <3000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   lte_cdev0 {
    trip = <&mdmss3_config0>;
    cooling-device = <&modem_lte_dsc 8 8>;
   };

   nr_scg_cdev0 {
    trip = <&mdmss3_config0>;
    cooling-device = <&modem_nr_scg_dsc 10 10>;
   };

   nr_cdev0 {
    trip = <&mdmss3_config0>;
    cooling-device = <&modem_nr_dsc 6 6>;
   };

   lte_cdev2 {
    trip = <&mdmss3_config1>;
    cooling-device = <&modem_lte_dsc 255 255>;
   };

   nr_cdev2 {
    trip = <&mdmss3_config1>;
    cooling-device = <&modem_nr_dsc 255 255>;
   };
  };
 };

 camera-0 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 14>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 camera-1 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens1 15>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 aoss-2 {
  polling-delay-passive = <0>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 0>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };
 };

 gpuss-0 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 1>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu0_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu0_cdev {
    trip = <&gpu0_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };

 gpuss-1 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 2>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu1_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu1_cdev {
    trip = <&gpu1_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };

 gpuss-2 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 3>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu2_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu2_cdev {
    trip = <&gpu2_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };

 gpuss-3 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 4>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu3_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu3_cdev {
    trip = <&gpu3_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };

 gpuss-4 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 5>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu4_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu4_cdev {
    trip = <&gpu4_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };

 gpuss-5 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 6>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu5_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu5_cdev {
    trip = <&gpu5_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };

 gpuss-6 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 7>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu6_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu6_cdev {
    trip = <&gpu6_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };

 gpuss-7 {
  polling-delay-passive = <10>;
  polling-delay = <0>;
  thermal-sensors = <&tsens2 8>;
  trips {
   thermal-engine-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   thermal-hal-config {
    temperature = <125000>;
    hysteresis = <1000>;
    type = "passive";
   };

   gpu7_tj_cfg: tj_cfg {
    temperature = <95000>;
    hysteresis = <5000>;
    type = "passive";
   };

   reset-mon-cfg {
    temperature = <115000>;
    hysteresis = <5000>;
    type = "passive";
   };
  };

  cooling-maps {
   gpu7_cdev {
    trip = <&gpu7_tj_cfg>;
    cooling-device = <&msm_gpu 0 (~0)>;
   };
  };
 };
};
# 3675 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-gdsc.dtsi" 1
&soc {

 cam_cc_camss_top_gdsc: qcom,gdsc@add5004 {
  compatible = "qcom,gdsc";
  reg = <0xadd5004 0x4>;
  regulator-name = "cam_cc_camss_top_gdsc";
  qcom,retain-regs;
  status = "disabled";
 };

 cam_cc_bps_gdsc: qcom,gdsc@adf0004 {
  compatible = "qcom,gdsc";
  reg = <0xadf0004 0x4>;
  regulator-name = "cam_cc_bps_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,support-hw-trigger;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_ife_0_gdsc: qcom,gdsc@adf1004 {
  compatible = "qcom,gdsc";
  reg = <0xadf1004 0x4>;
  regulator-name = "cam_cc_ife_0_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_ife_1_gdsc: qcom,gdsc@adf2004 {
  compatible = "qcom,gdsc";
  reg = <0xadf2004 0x4>;
  regulator-name = "cam_cc_ife_1_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_ife_2_gdsc: qcom,gdsc@adf2294 {
  compatible = "qcom,gdsc";
  reg = <0xadf2294 0x4>;
  regulator-name = "cam_cc_ife_2_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_ipe_0_gdsc: qcom,gdsc@adf03b8 {
  compatible = "qcom,gdsc";
  reg = <0xadf03b8 0x4>;
  regulator-name = "cam_cc_ipe_0_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,support-hw-trigger;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_sbi_gdsc: qcom,gdsc@adf052c {
  compatible = "qcom,gdsc";
  reg = <0xadf052c 0x4>;
  regulator-name = "cam_cc_sbi_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_sfe_0_gdsc: qcom,gdsc@adf3280 {
  compatible = "qcom,gdsc";
  reg = <0xadf3280 0x4>;
  regulator-name = "cam_cc_sfe_0_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_sfe_1_gdsc: qcom,gdsc@adf33e0 {
  compatible = "qcom,gdsc";
  reg = <0xadf33e0 0x4>;
  regulator-name = "cam_cc_sfe_1_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 cam_cc_titan_top_gdsc: qcom,gdsc@adf4058 {
  compatible = "qcom,gdsc";
  reg = <0xadf4058 0x4>;
  regulator-name = "cam_cc_titan_top_gdsc";
  proxy-supply = <&cam_cc_titan_top_gdsc>;
  qcom,gds-timeout = <1500>;
  qcom,proxy-consumer-enable;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };


 disp_cc_mdss_core_gdsc: qcom,gdsc@af09000 {
  compatible = "qcom,gdsc";
  reg = <0xaf09000 0x4>;
  regulator-name = "disp_cc_mdss_core_gdsc";
  proxy-supply = <&disp_cc_mdss_core_gdsc>;
  qcom,gds-timeout = <1500>;
  qcom,proxy-consumer-enable;
  qcom,support-hw-trigger;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 disp_cc_mdss_core_int2_gdsc: qcom,gdsc@af0b000 {
  compatible = "qcom,gdsc";
  reg = <0xaf0b000 0x4>;
  regulator-name = "disp_cc_mdss_core_int2_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,support-hw-trigger;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_apcs_gdsc_vote_ctrl: syscon@152020 {
  compatible = "syscon";
  reg = <0x152020 0x4>;
 };

 gcc_apcs_gdsc_sleep_ctrl: syscon@152024 {
  compatible = "syscon";
  reg = <0x152024 0x4>;
 };


 gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
  compatible = "qcom,gdsc";
  reg = <0x16b004 0x4>;
  regulator-name = "gcc_pcie_0_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,no-status-check-on-disable;
  qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 0>;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_pcie_0_phy_gdsc: qcom,gdsc@16c000 {
  compatible = "qcom,gdsc";
  reg = <0x16c000 0x4>;
  regulator-name = "gcc_pcie_0_phy_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,no-status-check-on-disable;
  qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 3>;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
  compatible = "qcom,gdsc";
  reg = <0x18d004 0x4>;
  regulator-name = "gcc_pcie_1_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,no-status-check-on-disable;
  qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 1>;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_pcie_1_phy_gdsc: qcom,gdsc@18e000 {
  compatible = "qcom,gdsc";
  reg = <0x18e000 0x4>;
  regulator-name = "gcc_pcie_1_phy_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,no-status-check-on-disable;
  qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl 4>;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_ufs_mem_phy_gdsc: qcom,gdsc@19e000 {
  compatible = "qcom,gdsc";
  reg = <0x19e000 0x4>;
  regulator-name = "gcc_ufs_mem_phy_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
  compatible = "qcom,gdsc";
  reg = <0x177004 0x4>;
  regulator-name = "gcc_ufs_phy_gdsc";
  proxy-supply = <&gcc_ufs_phy_gdsc>;
  qcom,gds-timeout = <1500>;
  qcom,proxy-consumer-enable;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_usb30_prim_gdsc: qcom,gdsc@139004 {
  compatible = "qcom,gdsc";
  reg = <0x139004 0x4>;
  regulator-name = "gcc_usb30_prim_gdsc";
  proxy-supply = <&gcc_usb30_prim_gdsc>;
  qcom,gds-timeout = <1500>;
  qcom,proxy-consumer-enable;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 gcc_usb3_phy_gdsc: qcom,gdsc@150018 {
  compatible = "qcom,gdsc";
  reg = <0x150018 0x4>;
  regulator-name = "gcc_usb3_phy_gdsc";
  proxy-supply = <&gcc_usb3_phy_gdsc>;
  qcom,gds-timeout = <1500>;
  qcom,proxy-consumer-enable;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };


 gpu_cc_cx_gdsc_hw_ctrl: syscon@3d9953c {
  compatible = "syscon";
  reg = <0x3d9953c 0x4>;
 };

 gpu_cc_cx_gdsc: qcom,gdsc@3d99108 {
  compatible = "qcom,gdsc";
  reg = <0x3d99108 0x4>;
  regulator-name = "gpu_cc_cx_gdsc";
  hw-ctrl-addr = <&gpu_cc_cx_gdsc_hw_ctrl>;
  qcom,no-status-check-on-disable;
  qcom,clk-dis-wait-val = <8>;
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  status = "disabled";
 };

 gpu_cc_gx_domain_addr: syscon@3d99504 {
  compatible = "syscon";
  reg = <0x3d99504 0x4>;
 };

 gpu_cc_gx_sw_reset: syscon@3d99058 {
  compatible = "syscon";
  reg = <0x3d99058 0x4>;
 };

 gpu_cc_gx_acd_reset: syscon@3d99358 {
  compatible = "syscon";
  reg = <0x3d99358 0x4>;
 };

 gpu_cc_gx_acd_iroot_reset: syscon@3d9958c {
  compatible = "syscon";
  reg = <0x3d9958c 0x4>;
 };

 gpu_cc_gx_gdsc: qcom,gdsc@3d9905c {
  compatible = "qcom,gdsc";
  reg = <0x3d9905c 0x4>;
  regulator-name = "gpu_cc_gx_gdsc";
  domain-addr = <&gpu_cc_gx_domain_addr>;
  sw-reset = <&gpu_cc_gx_sw_reset>,
      <&gpu_cc_gx_acd_reset>,
      <&gpu_cc_gx_acd_iroot_reset>;
  qcom,reset-aon-logic;
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };


 video_cc_mvs0_gdsc: qcom,gdsc@abf80a4 {
  compatible = "qcom,gdsc";
  reg = <0xabf80a4 0x4>;
  regulator-name = "video_cc_mvs0_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,support-hw-trigger;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 video_cc_mvs0c_gdsc: qcom,gdsc@abf804c {
  compatible = "qcom,gdsc";
  reg = <0xabf804c 0x4>;
  regulator-name = "video_cc_mvs0c_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 video_cc_mvs1_gdsc: qcom,gdsc@abf80cc {
  compatible = "qcom,gdsc";
  reg = <0xabf80cc 0x4>;
  regulator-name = "video_cc_mvs1_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,support-hw-trigger;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };

 video_cc_mvs1c_gdsc: qcom,gdsc@abf8078 {
  compatible = "qcom,gdsc";
  reg = <0xabf8078 0x4>;
  regulator-name = "video_cc_mvs1c_gdsc";
  qcom,gds-timeout = <1500>;
  qcom,retain-regs;
  qcom,support-cfg-gdscr;
  status = "disabled";
 };
};
# 3676 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama.dtsi" 2

&qupv3_se7_2uart {
 status = "ok";
};

&qupv3_hub_i2c2 {
 status = "ok";
 fsa4480: fsa4480@42 {
  compatible = "qcom,fsa4480-i2c";
  reg = <0x42>;
 };
};
&cam_cc_bps_gdsc {
 clocks = <&gcc 6>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&cam_cc_ife_0_gdsc {
 clocks = <&gcc 6>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&cam_cc_ife_1_gdsc {
 clocks = <&gcc 6>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";

};

&cam_cc_ife_2_gdsc {
 clock-names = "ahb_clk";
 clocks = <&gcc 6>;
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&cam_cc_ipe_0_gdsc {
 clock-names = "ahb_clk";
 clocks = <&gcc 6>;
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&cam_cc_sbi_gdsc {
 clocks = <&gcc 6>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&cam_cc_sfe_0_gdsc {
 clocks = <&gcc 6>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&cam_cc_sfe_1_gdsc {
 clocks = <&gcc 6>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&cam_cc_titan_top_gdsc {
 clocks = <&gcc 6>;
 clock-names = "ahb_clk";
 interconnects = <&mmss_noc 11 &mmss_noc 562>;
 interconnect-names = "mmnoc";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&disp_cc_mdss_core_gdsc {
 clocks = <&gcc 15>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_LEVEL>;
 status = "ok";
};

&disp_cc_mdss_core_int2_gdsc {
 clocks = <&gcc 15>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_LEVEL>;
 status = "ok";
};

&gcc_pcie_0_gdsc {
 clocks = <&gcc 0>;
 parent-supply = <&VDD_CX_LEVEL>;
 status = "ok";
};

&gcc_pcie_0_phy_gdsc {
 clocks = <&gcc 0>;
 parent-supply = <&VDD_MXA_LEVEL>;
 status = "ok";
};

&gcc_pcie_1_gdsc {
 clocks = <&gcc 0>;
 parent-supply = <&VDD_CX_LEVEL>;
 status = "ok";
};

&gcc_pcie_1_phy_gdsc {
 clocks = <&gcc 0>;
 parent-supply = <&VDD_MXA_LEVEL>;
 status = "ok";
};

&gcc_ufs_mem_phy_gdsc {
 clocks = <&gcc 0>;
 parent-supply = <&VDD_MXA_LEVEL>;
 status = "ok";
};

&gcc_ufs_phy_gdsc {
 clocks = <&gcc 0>;
 parent-supply = <&VDD_CX_LEVEL>;
 status = "ok";
};

&gcc_usb30_prim_gdsc {
 clocks = <&gcc 0>;
 status = "ok";
};

&gcc_usb3_phy_gdsc {
 clocks = <&gcc 0>;
 parent-supply = <&VDD_MXA_LEVEL>;
 status = "ok";
};

&gpu_cc_cx_gdsc {
 parent-supply = <&VDD_CX_LEVEL>;
 status = "ok";
};

&gpu_cc_gx_gdsc {
 parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
 status = "ok";
};

&video_cc_mvs0_gdsc {
 clocks = <&gcc 167>;
 clock-names = "ahb_clk";
 parent-supply = <&video_cc_mvs0c_gdsc>;
 status = "ok";
};

&video_cc_mvs0c_gdsc {
 clocks = <&gcc 167>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};

&video_cc_mvs1_gdsc {
 clocks = <&gcc 167>;
 clock-names = "ahb_clk";
 parent-supply = <&video_cc_mvs1c_gdsc>;
 status = "ok";
};

&video_cc_mvs1c_gdsc {
 clocks = <&gcc 167>;
 clock-names = "ahb_clk";
 parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
 status = "ok";
};
# 18 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-moto-common-base.dtsi" 2

/ {
 model = "Qualcomm Technologies, Inc. Kalama SoC";
 compatible = "qcom,kalama";
 qcom,board-id = <0 0>;




 channel-id-map = "";
 chosen: chosen { };
 aliases: aliases { };
 reserved_memory: reserved-memory { };
 mot_batterydata: qcom,battery-data { };
 utags: utags { };
 hw: hw { };
};

&reserved_memory {
 /delete-node/ ramoops_region;
};

&firmware {
 android {
  /delete-node/ fstab;
 };
};

/delete-node/ &mem_offline;

&apps_smmu {
 /delete-property/ dma-coherent;
};
# 16 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-rtwo-base.dts" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-moto-common-nxp-nfc.dtsi" 1
# 15 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-moto-common-nxp-nfc.dtsi"
&qupv3_se0_i2c {
        status = "ok";
        qcom,clk-freq-out = <1000000>;
        #address-cells = <1>;
        #size-cells = <0>;
        nq@28 {
                compatible = "qcom,sn-nci";
                reg = <0x28>;
                qcom,sn-irq = <&tlmm 55 0x00>;
                qcom,sn-ven = <&tlmm 30 0x00>;
                qcom,sn-clkreq = <&tlmm 31 0x00>;
                interrupt-parent = <&tlmm>;
                interrupts = <55 0>;
                interrupt-names = "nfc_irq";
                pinctrl-names = "nfc_active", "nfc_suspend";
                pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
                pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
        };
};

&tlmm {
        nfc_int_active: nfc_int_active {

                mux {

                     pins = "gpio55";
                     function = "gpio";
                };

                config {
                     pins = "gpio55";
                     drive-strength = <2>;
                     bias-pull-down;
                };
        };

        nfc_int_suspend: nfc_int_suspend {

                mux {

                     pins = "gpio55";
                     function = "gpio";
                };

                config {
                     pins = "gpio55";
                     drive-strength = <2>;
                     bias-pull-down;
                };
        };

        nfc_enable_active: nfc_enable_active {
                mux {

                     pins = "gpio30", "gpio31";
                     function = "gpio";
                };

                config {
                     pins = "gpio30", "gpio31";
                     drive-strength = <2>;
                     bias-disable;
                };
        };

        nfc_enable_suspend: nfc_enable_suspend {
                mux {
                     pins = "gpio30", "gpio31";
                     function = "gpio";
                };

                config {
                     pins = "gpio30", "gpio31";
                     drive-strength = <2>;
                     bias-disable;
                };
        };
};
# 17 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/kalama-rtwo-base.dts" 2


&qupv3_se0_i2c {
        status = "ok";
        qcom,clk-freq-out = <1000000>;
        #address-cells = <1>;
        #size-cells = <0>;
        nq@28 {
                compatible = "qcom,sn-nci";
                reg = <0x28>;
                qcom,sn-irq = <&tlmm 55 0x00>;
                qcom,sn-ven = <&tlmm 30 0x00>;
                qcom,sn-clkreq = <&tlmm 31 0x00>;
                qcom,clk-src = "BBCLK2";
                interrupt-parent = <&tlmm>;
                interrupts = <55 0>;
                interrupt-names = "nfc_irq";
                pinctrl-names = "nfc_active", "nfc_suspend";
                pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
                pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
                clocks = <&rpmhcc 2>;
                clock-names = "nfc_ref_clk";

        };
};