# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts"
# 1 "<built-in>" 1
# 1 "<built-in>" 3
# 10 "<built-in>" 3
# 1 "<command line>" 1
# 1 "<built-in>" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts" 2
/dts-v1/;
/plugin/;

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,gcc-crow.h" 1
# 5 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/clock/qcom,camcc-crow.h" 1
# 6 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interconnect/qcom,crow.h" 1
# 7 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1








# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 8 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts" 2
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/scripts/dtc/include-prefixes/dt-bindings/regulator/qcom,rpmh-regulator-levels.h" 1
# 9 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts" 2

# 1 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dtsi" 1
# 1 "/home/luuxis/evo/kernel/motorola/sm8550/../sm8550-modules/qcom/opensource/camera-kernel/dt-bindings/msm-camera.h" 1
# 2 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dtsi" 2

&tlmm {
 cci_i2c_sda0_active: cci_i2c_sda0_active {
  mux {

   pins = "gpio70";
   function = "cci_i2c_sda0";
  };

  config {
   pins = "gpio70";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_sda0_suspend: cci_i2c_sda0_suspend {
  mux {

   pins = "gpio70";
   function = "cci_i2c_sda0";
  };

  config {
   pins = "gpio70";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl0_active: cci_i2c_scl0_active {
  mux {

   pins = "gpio71";
   function = "cci_i2c_scl0";
  };

  config {
   pins = "gpio71";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl0_suspend: cci_i2c_scl0_suspend {
  mux {

   pins = "gpio71";
   function = "cci_i2c_scl0";
  };

  config {
   pins = "gpio71";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cci_i2c_sda1_active: cci_i2c_sda1_active {
  mux {

   pins = "gpio72";
   function = "cci_i2c_sda1";
  };

  config {
   pins = "gpio72";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_sda1_suspend: cci_i2c_sda1_suspend {
  mux {

   pins = "gpio72";
   function = "cci_i2c_sda1";
  };

  config {
   pins = "gpio72";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl1_active: cci_i2c_scl1_active {
  mux {

   pins = "gpio73";
   function = "cci_i2c_scl1";
  };

  config {
   pins = "gpio73";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl1_suspend: cci_i2c_scl1_suspend {
  mux {

   pins = "gpio73";
   function = "cci_i2c_scl1";
  };

  config {
   pins = "gpio73";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cci_i2c_sda2_active: cci_i2c_sda2_active {
  mux {

   pins = "gpio74";
   function = "cci_i2c_sda2";
  };

  config {
   pins = "gpio74";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_sda2_suspend: cci_i2c_sda2_suspend {
  mux {

   pins = "gpio74";
   function = "cci_i2c_sda2";
  };

  config {
   pins = "gpio74";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl2_active: cci_i2c_scl2_active {
  mux {

   pins = "gpio75";
   function = "cci_i2c_scl2";
  };

  config {
   pins = "gpio75";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl2_suspend: cci_i2c_scl2_suspend {
  mux {

   pins = "gpio75";
   function = "cci_i2c_scl2";
  };

  config {
   pins = "gpio75";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cci_i2c_sda3_active: cci_i2c_sda3_active {
  mux {

   pins = "gpio76";
   function = "cci_i2c_sda3";
  };

  config {
   pins = "gpio76";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_sda3_suspend: cci_i2c_sda3_suspend {
  mux {

   pins = "gpio76";
   function = "cci_i2c_sda3";
  };

  config {
   pins = "gpio76";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl3_active: cci_i2c_scl3_active {
  mux {

   pins = "gpio77";
   function = "cci_i2c_scl3";
  };

  config {
   pins = "gpio77";
   bias-pull-up;
   drive-strength = <2>;
  };
 };

 cci_i2c_scl3_suspend: cci_i2c_scl3_suspend {
  mux {

   pins = "gpio77";
   function = "cci_i2c_scl3";
  };

  config {
   pins = "gpio77";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk0_active: cam_sensor_mclk0_active {

  mux {
   pins = "gpio64";
   function = "cam_mclk";
  };

  config {
   pins = "gpio64";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {

  mux {
   pins = "gpio64";
   function = "cam_mclk";
  };

  config {
   pins = "gpio64";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk1_active: cam_sensor_mclk1_active {

  mux {
   pins = "gpio65";
   function = "cam_mclk";
  };

  config {
   pins = "gpio65";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {

  mux {
   pins = "gpio65";
   function = "cam_mclk";
  };

  config {
   pins = "gpio65";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk2_active: cam_sensor_mclk2_active {

  mux {
   pins = "gpio66";
   function = "cam_mclk";
  };

  config {
   pins = "gpio66";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {

  mux {
   pins = "gpio66";
   function = "cam_mclk";
  };

  config {
   pins = "gpio66";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk3_active: cam_sensor_mclk3_active {

  mux {
   pins = "gpio67";
   function = "cam_mclk";
  };

  config {
   pins = "gpio67";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {

  mux {
   pins = "gpio67";
   function = "cam_mclk";
  };

  config {
   pins = "gpio67";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk4_active: cam_sensor_mclk4_active {

  mux {
   pins = "gpio68";
   function = "cam_mclk";
  };

  config {
   pins = "gpio68";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend {

  mux {
   pins = "gpio68";
   function = "cam_mclk";
  };

  config {
   pins = "gpio68";
   bias-pull-down;
   drive-strength = <2>;
  };
 };

 cam_sensor_active_rst0: cam_sensor_active_rst0 {
  mux {
   pins = "gpio123";
   function = "gpio";
  };

  config {
   pins = "gpio123";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 {
  mux {
   pins = "gpio123";
   function = "gpio";
  };

  config {
   pins = "gpio123";
   bias-pull-down;
   drive-strength = <2>;
   output-low;
  };
 };

 cam_sensor_active_rst1: cam_sensor_active_rst1 {
  mux {
   pins = "gpio124";
   function = "gpio";
  };

  config {
   pins = "gpio124";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 {
  mux {
   pins = "gpio124";
   function = "gpio";
  };

  config {
   pins = "gpio124";
   bias-pull-down;
   drive-strength = <2>;
   output-low;
  };
 };

 cam_sensor_active_rst2: cam_sensor_active_rst2 {
  mux {
   pins = "gpio125";
   function = "gpio";
  };

  config {
   pins = "gpio125";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 {
  mux {
   pins = "gpio125";
   function = "gpio";
  };

  config {
   pins = "gpio125";
   bias-pull-down;
   drive-strength = <2>;
   output-low;
  };
 };

 cam_sensor_active_rst3: cam_sensor_active_rst3 {
  mux {
   pins = "gpio126";
   function = "gpio";
  };

  config {
   pins = "gpio126";
   bias-disable;
   drive-strength = <2>;
  };
 };

 cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 {
  mux {
   pins = "gpio126";
   function = "gpio";
  };

  config {
   pins = "gpio126";
   bias-pull-down;
   drive-strength = <2>;
   output-low;
  };
 };
};

&soc {

 #address-cells = <1>;
 #size-cells = <1>;
 interrupt-parent = <&intc>;

 qcom,cam-req-mgr {
  compatible = "qcom,cam-req-mgr";
  status = "ok";
 };

 qcom,cam-sync {
  compatible = "qcom,cam-sync";
  status = "ok";
 };

 cam_csiphy0: qcom,csiphy0@ace4000 {
  cell-index = <0>;
  compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy";
  reg = <0x0ace4000 0x2000>;
  reg-names = "csiphy";
  reg-cam-base = <0xe4000>;
  interrupt-names = "CSIPHY0";
  interrupts = <0 477 1>;
  regulator-names = "camss", "csi-vdd-1p2", "csi-vdd-0p9";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  csi-vdd-1p2-supply = <&L4B>;
  csi-vdd-0p9-supply = <&L2B>;
  rgltr-cntrl-support;
  rgltr-min-voltage = <0 1200000 880000>;
  rgltr-max-voltage = <0 1200000 912000>;
  rgltr-load-current = <0 17920 98480>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy0_clk",
   "csi0phytimer_clk_src",
   "csi0phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 45>,
   <&camcc 38>,
   <&camcc 37>;
  src-clock-name = "csi0phytimer_clk_src";
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  status = "ok";
 };

 cam_csiphy1: qcom,csiphy1@ace6000 {
  cell-index = <1>;
  compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy";
  reg = <0xace6000 0x2000>;
  reg-names = "csiphy";
  reg-cam-base = <0xe6000>;
  interrupt-names = "CSIPHY1";
  interrupts = <0 478 1>;
  regulator-names = "camss", "csi-vdd-1p2", "csi-vdd-0p9";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  csi-vdd-1p2-supply = <&L4B>;
  csi-vdd-0p9-supply = <&L2B>;
  rgltr-cntrl-support;
  rgltr-min-voltage = <0 1200000 880000>;
  rgltr-max-voltage = <0 1200000 912000>;
  rgltr-load-current = <0 17920 98480>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy1_clk",
   "csi1phytimer_clk_src",
   "csi1phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 46>,
   <&camcc 40>,
   <&camcc 39>;
  src-clock-name = "csi1phytimer_clk_src";
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  status = "ok";
 };

 cam_csiphy2: qcom,csiphy2@ace8000 {
  cell-index = <2>;
  compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy";
  reg = <0xace8000 0x2000>;
  reg-names = "csiphy";
  reg-cam-base = <0xe8000>;
  interrupt-names = "CSIPHY2";
  interrupts = <0 479 1>;
  regulator-names = "camss", "csi-vdd-1p2", "csi-vdd-0p9";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  csi-vdd-1p2-supply = <&L4B>;
  csi-vdd-0p9-supply = <&L2B>;
  rgltr-cntrl-support;
  rgltr-min-voltage = <0 1200000 880000>;
  rgltr-max-voltage = <0 1200000 912000>;
  rgltr-load-current = <0 17920 98480>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy2_clk",
   "csi2phytimer_clk_src",
   "csi2phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 47>,
   <&camcc 42>,
   <&camcc 41>;
  src-clock-name = "csi2phytimer_clk_src";
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  status = "ok";
 };

 cam_csiphy3: qcom,csiphy3@acea000 {
  cell-index = <3>;
  compatible = "qcom,csiphy-v2.1.2", "qcom,csiphy";
  reg = <0xacea000 0x2000>;
  reg-names = "csiphy";
  reg-cam-base = <0xea000>;
  interrupt-names = "CSIPHY3";
  interrupts = <0 448 1>;
  regulator-names = "camss", "csi-vdd-1p2", "csi-vdd-0p9";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  csi-vdd-1p2-supply = <&L4B>;
  csi-vdd-0p9-supply = <&L2B>;
  rgltr-cntrl-support;
  rgltr-min-voltage = <0 1200000 880000>;
  rgltr-max-voltage = <0 1200000 912000>;
  rgltr-load-current = <0 17920 98480>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy3_clk",
   "csi3phytimer_clk_src",
   "csi3phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 48>,
   <&camcc 44>,
   <&camcc 43>;
  src-clock-name = "csi3phytimer_clk_src";
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  status = "ok";
 };

 cam_cci0: qcom,cci0@ac15000 {
  cell-index = <0>;
  compatible = "qcom,cci", "simple-bus";
  reg = <0xac15000 0x1000>;
  reg-names = "cci";
  reg-cam-base = <0x15000>;
  interrupt-names = "CCI0";
  interrupts = <0 426 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names = "cci_0_clk_src",
   "cci_0_clk";
  clocks = <&camcc 28>,
   <&camcc 27>;
  clock-rates = <37500000 0>;
  clock-cntl-level = "lowsvs";
  src-clock-name = "cci_0_clk_src";
  pctrl-idx-mapping = <0 1>;
  pctrl-map-names = "m0", "m1";
  pinctrl-names = "m0_active", "m0_suspend",
   "m1_active", "m1_suspend";
  pinctrl-0 = <&cci_i2c_scl0_active &cci_i2c_sda0_active>;
  pinctrl-1 = <&cci_i2c_scl0_suspend &cci_i2c_sda0_suspend>;
  pinctrl-2 = <&cci_i2c_scl1_active &cci_i2c_sda1_active>;
  pinctrl-3 = <&cci_i2c_scl1_suspend &cci_i2c_sda1_suspend>;
  status = "ok";

  i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
   hw-thigh = <201>;
   hw-tlow = <174>;
   hw-tsu-sto = <204>;
   hw-tsu-sta = <231>;
   hw-thd-dat = <22>;
   hw-thd-sta = <162>;
   hw-tbuf = <227>;
   hw-scl-stretch-en = <0>;
   hw-trdhld = <6>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };

  i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
   hw-thigh = <38>;
   hw-tlow = <56>;
   hw-tsu-sto = <40>;
   hw-tsu-sta = <40>;
   hw-thd-dat = <22>;
   hw-thd-sta = <35>;
   hw-tbuf = <62>;
   hw-scl-stretch-en = <0>;
   hw-trdhld = <6>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };

  i2c_freq_custom_cci0: qcom,i2c_custom_mode {
   hw-thigh = <16>;
   hw-tlow = <22>;
   hw-tsu-sto = <17>;
   hw-tsu-sta = <18>;
   hw-thd-dat = <16>;
   hw-thd-sta = <15>;
   hw-tbuf = <24>;
   hw-scl-stretch-en = <1>;
   hw-trdhld = <3>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };

  i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
   hw-thigh = <16>;
   hw-tlow = <22>;
   hw-tsu-sto = <17>;
   hw-tsu-sta = <18>;
   hw-thd-dat = <16>;
   hw-thd-sta = <15>;
   hw-tbuf = <24>;
   hw-scl-stretch-en = <0>;
   hw-trdhld = <3>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };
 };

 cam_cci1: qcom,cci1@ac16000 {
  cell-index = <1>;
  compatible = "qcom,cci", "simple-bus";
  reg = <0xac16000 0x1000>;
  reg-names = "cci";
  reg-cam-base = <0x16000>;
  interrupt-names = "CCI1";
  interrupts = <0 427 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names = "cci_1_clk_src",
   "cci_1_clk";
  clocks = <&camcc 30>,
   <&camcc 29>;
  clock-rates = <37500000 0>;
  clock-cntl-level = "lowsvs";
  src-clock-name = "cci_1_clk_src";
  pctrl-idx-mapping = <0 1>;
  pctrl-map-names = "m0", "m1";
  pinctrl-names = "m0_active", "m0_suspend",
   "m1_active", "m1_suspend";
  pinctrl-0 = <&cci_i2c_scl2_active &cci_i2c_sda2_active>;
  pinctrl-1 = <&cci_i2c_scl2_suspend &cci_i2c_sda2_suspend>;
  pinctrl-2 = <&cci_i2c_scl3_active &cci_i2c_sda3_active>;
  pinctrl-3 = <&cci_i2c_scl3_suspend &cci_i2c_sda3_suspend>;
  status = "ok";

  i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
   hw-thigh = <201>;
   hw-tlow = <174>;
   hw-tsu-sto = <204>;
   hw-tsu-sta = <231>;
   hw-thd-dat = <22>;
   hw-thd-sta = <162>;
   hw-tbuf = <227>;
   hw-scl-stretch-en = <0>;
   hw-trdhld = <6>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };

  i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
   hw-thigh = <38>;
   hw-tlow = <56>;
   hw-tsu-sto = <40>;
   hw-tsu-sta = <40>;
   hw-thd-dat = <22>;
   hw-thd-sta = <35>;
   hw-tbuf = <62>;
   hw-scl-stretch-en = <0>;
   hw-trdhld = <6>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };

  i2c_freq_custom_cci1: qcom,i2c_custom_mode {
   hw-thigh = <16>;
   hw-tlow = <22>;
   hw-tsu-sto = <17>;
   hw-tsu-sta = <18>;
   hw-thd-dat = <16>;
   hw-thd-sta = <15>;
   hw-tbuf = <24>;
   hw-scl-stretch-en = <1>;
   hw-trdhld = <3>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };

  i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
   hw-thigh = <16>;
   hw-tlow = <22>;
   hw-tsu-sto = <17>;
   hw-tsu-sta = <18>;
   hw-thd-dat = <16>;
   hw-thd-sta = <15>;
   hw-tbuf = <24>;
   hw-scl-stretch-en = <0>;
   hw-trdhld = <3>;
   hw-tsp = <3>;
   cci-clk-src = <37500000>;
   status = "ok";
  };
 };

 qcom,cam_smmu {
  compatible = "qcom,msm-cam-smmu", "simple-bus";
  status = "ok";
  force_cache_allocs;
  need_shared_buffer_padding;

  msm_cam_smmu_tfe {
   compatible = "qcom,msm-cam-smmu-cb";
   iommus = <&apps_smmu 0x08A0 0x020>,
    <&apps_smmu 0x0880 0x020>;
   qcom,iommu-faults = "fatal";
   qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
   dma-coherent;
   cam-smmu-label = "tfe";
   tfe_iova_mem_map: iova-mem-map {

    iova-mem-region-io {
     iova-region-name = "io";

     iova-region-start = <0x100000>;

     iova-region-len = <0xffe00000>;
     iova-region-id = <0x3>;
     status = "ok";
    };
   };
  };

  msm_cam_smmu_icp {
   compatible = "qcom,msm-cam-smmu-cb";
   iommus = <&apps_smmu 0x18C0 0x00A0>,
    <&apps_smmu 0x1820 0x0000>,
    <&apps_smmu 0x1840 0x00A0>,
    <&apps_smmu 0x1860 0x00A0>,
    <&apps_smmu 0x18E0 0x00A0>,
    <&apps_smmu 0x1900 0x0000>;
   qcom,iommu-faults = "fatal";
   cam-smmu-label = "icp";
   qcom,iommu-dma-addr-pool = <0x14c00000 0xee300000>;
   dma-coherent;
   icp_iova_mem_map: iova-mem-map {
    iova-mem-region-shared {

     iova-region-name = "shared";
     iova-region-start = <0x4800000>;
     iova-region-len = <0xFC00000>;
     iova-region-id = <0x1>;
     status = "ok";
    };

    iova-mem-region-fwuncached-region {

     iova-region-name = "fw_uncached";
     iova-region-start = <0x14400000>;
     iova-region-len = <0x700000>;
     iova-region-id = <0x6>;
     status = "ok";
    };

    iova-mem-region-io {

     iova-region-name = "io";
     iova-region-start = <0x14c00000>;
     iova-region-len = <0xea300000>;
     iova-region-id = <0x3>;
     status = "ok";
    };

    iova-mem-qdss-region {

     iova-region-name = "qdss";
     iova-region-start = <0x14b00000>;
     iova-region-len = <0x100000>;
     iova-region-id = <0x5>;
     qdss-phy-addr = <0x16790000>;
     status = "ok";
    };
   };
  };

  msm_cam_smmu_cdm {
   compatible = "qcom,msm-cam-smmu-cb";
   iommus = <&apps_smmu 0x1800 0x000>;
   cam-smmu-label = "rt-cdm";
   qcom,iommu-faults = "fatal";
   qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
   multiple-client-devices;
   dma-coherent;
   rt_cdm_iova_mem_map: iova-mem-map {
    iova-mem-region-io {
     iova-region-name = "io";

     iova-region-start = <0x100000>;
     iova-region-len = <0xffe00000>;
     iova-region-id = <0x3>;
     status = "ok";
    };
   };
  };

  msm_cam_smmu_cre {
   compatible = "qcom,msm-cam-smmu-cb";
   iommus = <&apps_smmu 0x1920 0x000>,
    <&apps_smmu 0x1940 0x000>;
   qcom,iommu-faults = "fatal";
   multiple-client-devices;
   qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
   cam-smmu-label = "cre";
   dma-coherent;
   cre_iova_mem_map: iova-mem-map {

    iova-mem-region-io {
     iova-region-name = "io";

     iova-region-start = <0x100000>;
     iova-region-len = <0xffe00000>;
     iova-region-id = <0x3>;
     status = "ok";
    };
   };
  };

  msm_cam_smmu_jpeg {
   compatible = "qcom,msm-cam-smmu-cb";
   iommus = <&apps_smmu 0x1960 0x000>;
   qcom,iommu-faults = "fatal";
   cam-smmu-label = "jpeg";
   qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>;
   dma-coherent;
   jpeg_iova_mem_map: iova-mem-map {

    iova-mem-region-io {
     iova-region-name = "io";

     iova-region-start = <0x100000>;

     iova-region-len = <0xffe00000>;
     iova-region-id = <0x3>;
     status = "ok";
    };
   };
  };

  msm_cam_smmu_secure {
   compatible = "qcom,msm-cam-smmu-cb";
   cam-smmu-label = "cam-secure";
   qcom,secure-cb;
  };
 };

 qcom,cam-cpas@ac13000 {
  cell-index = <0>;
  compatible = "qcom,cam-cpas";
  label = "cpas";
  arch-compat = "cpas_top";
  reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh";
  reg = <0xac13000 0x1000>,
   <0xac19000 0xB000>,
   <0xbbf0000 0x1F00>;
  reg-cam-base = <0x13000 0x19000 0x0bbf0000>;
  cam_hw_fuse = <6 0x221C8138 0x1 1 0x8>;
  interrupt-names = "cpas_camnoc";
  interrupts = <0 459 1>;
  camnoc-axi-min-ib-bw = <3000000000>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "sys_tmr_clk",
   "soc_ahb_clk",
   "slow_ahb_clk_src",
   "cpas_ahb_clk",
   "core_ahb_clk",
   "fast_ahb_clk_src",
   "camnoc_axi_clk_src",
   "cam_cc_camnoc_nrt_axi_clk",
   "cam_cc_camnoc_rt_axi_clk",
   "camnoc_axi_hf_clk",
   "camnoc_axi_sf_clk";
  clocks =
   <&camcc 76>,
   <&camcc 75>,
   <&camcc 74>,
   <&camcc 32>,
   <&camcc 31>,
   <&camcc 49>,
   <&camcc 22>,
   <&camcc 25>,
   <&camcc 26>,
   <&camcc 23>,
   <&camcc 24>;
  clock-rates =
   <0 0 0 0 0 0 0 0 0 0 0>,
   <0 0 80000000 0 0 100000000 150000000 0 0 0 0>,
   <0 0 80000000 0 0 150000000 240000000 0 0 0 0>,
   <0 0 80000000 0 0 200000000 300000000 0 0 0 0>,
   <0 0 80000000 0 0 240000000 400000000 0 0 0 0>,
   <0 0 80000000 0 0 240000000 400000000 0 0 0 0>;
  clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1",
   "nominal", "turbo";
  src-clock-name = "camnoc_axi_clk_src";
  clock-names-option = "cam_icp_clk";
  clocks-option = <&camcc 52>;
  clock-rates-option = <400000000>;
  control-camnoc-axi-clk;
  camnoc-bus-width = <32>;
  camnoc-axi-clk-bw-margin-perc = <20>;
  interconnect-names = "cam_ahb";
  interconnects =<&gem_noc 2
   &config_noc 517>;
  rpmh-bcm-info = <12 0x4 0x800 0 4>;
  cam-ahb-num-cases = <8>;
  cam-ahb-bw-KBps =
   <0 0>, <0 150000>, <0 150000>, <0 150000>,<0 300000>,
   <0 300000>, <0 300000>, <0 300000>;
  vdd-corners = <16
   48
   64
   128
   192
   256
   320
   336
   384
   416>;
  vdd-corner-ahb-mapping = "suspend", "lowsvs",
   "lowsvs", "svs", "svs_l1",
   "nominal", "nominal", "nominal",
   "turbo", "turbo";
  client-id-based;
  client-names =
   "csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0", "cci1",
   "csid0", "csid1", "csid2", "csid3", "tfe0", "tfe1", "tfe2",
   "tfe3", "ipe0", "rt-cdm0", "rt-cdm1", "rt-cdm2",
   "cam-cdm-intf0", "bps0", "icp0", "tpg13", "tpg14", "tpg15",
   "tpg16", "cre0", "jpeg-dma0", "jpeg-enc0";
  status = "ok";

  camera-bus-nodes {
   level3-nodes {
    level-index = <3>;
    level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum {
     cell-index = <0>;
     node-name = "level3-rt0-rd-wr-sum";
     traffic-merge-type =
     <0>;
     ib-bw-voting-needed;
     qcom,axi-port-mnoc {
      interconnect-names = "cam_hf_0";
      interconnects =
      <&mmss_noc 13
      &mc_virt 512>;
     };
    };

    level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
     cell-index = <1>;
     node-name = "level3-nrt0-rd-wr-sum";
     traffic-merge-type =
     <0>;
     qcom,axi-port-mnoc {
      interconnect-names = "cam_sf_0";
      interconnects =
      <&mmss_noc 15
      &mc_virt 512>;
     };
    };

    level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
     cell-index = <2>;
     node-name = "level3-nrt1-rd-wr-sum";
     traffic-merge-type =
     <0>;
     qcom,axi-port-mnoc {
      interconnect-names =
       "cam_sf_icp";
      interconnects =
      <&mmss_noc 14
      &mc_virt 512>;
     };
    };
   };

   level2-nodes {
    level-index = <2>;
    camnoc-max-needed;
    level2_rt0_wr: level2-rt0-wr {
     cell-index = <3>;
     node-name = "level2-rt0-wr";
     parent-node = <&level3_rt0_rd_wr_sum>;
     traffic-merge-type =
     <1>;
    };

    level2_rt1_wr: level2-rt1-wr {
     cell-index = <4>;
     node-name = "level2-rt1-wr";
     parent-node = <&level3_rt0_rd_wr_sum>;
     traffic-merge-type =
     <1>;
    };

    level2_nrt0_wr: level2-nrt0-wr {
     cell-index = <5>;
     node-name = "level2-nrt0-wr";
     parent-node = <&level3_nrt0_rd_wr_sum>;
     traffic-merge-type =
     <1>;
    };

    level2_nrt0_rd: level2-nrt0-rd {
     cell-index = <6>;
     node-name = "level2-nrt0-rd";
     parent-node = <&level3_nrt0_rd_wr_sum>;
     traffic-merge-type =
     <1>;
    };

    level2_nrt1_rd: level2-nrt1-rd {
     cell-index = <7>;
     node-name = "level2-nrt1-rd";
     parent-node = <&level3_nrt1_rd_wr_sum>;
     traffic-merge-type =
     <0>;
     bus-width-factor = <4>;
    };
   };

   level1-nodes {
    level-index = <1>;
    camnoc-max-needed;
    level1_rt0_wr0: level1-rt0-wr0 {
     cell-index = <8>;
     node-name = "level1-tfe-bayer-status-wr";
     parent-node = <&level2_rt0_wr>;
     traffic-merge-type =
     <0>;
    };

    level1_rt1_wr0: level1-rt0-wr1 {
     cell-index = <9>;
     node-name = "level1-tfe-rdi-raw-wr";
     parent-node = <&level2_rt1_wr>;
     traffic-merge-type =
     <0>;
    };

    level1_nrt0_wr0: level1-nrt0-wr0 {
     cell-index = <10>;
     node-name = "level1-nrt0-wr0";
     parent-node = <&level2_nrt0_wr>;
     traffic-merge-type =
     <0>;
    };

    level1_nrt1_rd0: level1-nrt1-rd0 {
     cell-index = <11>;
     node-name = "level1-nrt0-rd0";
     parent-node = <&level2_nrt0_rd>;
     traffic-merge-type =
     <0>;
    };

    level1_nrt2_rd_wr: level1-nrt2-rd-wr {
     cell-index = <12>;
     node-name = "level1-nrt2-rd-wr";
     parent-node = <&level2_nrt0_wr>;
     traffic-merge-type =
     <0>;
    };

    level1_nrt3_wr0: level1-nrt0-wr1 {
     cell-index = <13>;
     node-name = "level1-nrt3-wr0";
     parent-node = <&level2_nrt0_wr>;
     traffic-merge-type =
     <0>;
    };

    level1_nrt4_rd0: level1-nrt4-rd0 {
     cell-index = <14>;
     node-name = "level1-nrt4-rd0";
     parent-node = <&level2_nrt0_rd>;
     traffic-merge-type =
     <0>;
    };

    level1_nrt5_rd0: level1-nrt5-rd0 {
     cell-index = <15>;
     node-name = "level1-nrt5-rd0";
     parent-node = <&level2_nrt0_rd>;
     traffic-merge-type =
     <0>;
    };
   };

   level0-nodes {
    level-index = <0>;
    tfe0_bayer_stats_wr: tfe0_bayer_stats_wr {
     cell-index = <16>;
     node-name = "tfe0-bayer-stats-wr";
     client-name = "tfe0";
     traffic-data =
     <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(0 + 1)
     (0 + 2)
     (0 + 3)>;
     parent-node = <&level1_rt0_wr0>;
    };

    tfe1_bayer_stats_wr: tfe1_bayer_stats_wr {
     cell-index = <17>;
     node-name = "tfe1-bayer-stats-wr";
     client-name = "tfe1";
     traffic-data =
     <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(0 + 1)
     (0 + 2)
     (0 + 3)>;
     parent-node = <&level1_rt0_wr0>;
    };

    tfe2_bayer_stats_wr: tfe2_bayer_stats_wr {
     cell-index = <18>;
     node-name = "tfe2-bayer-stats-wr";
     client-name = "tfe2";
     traffic-data =
     <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(0 + 1)
     (0 + 2)
     (0 + 3)>;
     parent-node = <&level1_rt0_wr0>;
    };

    tfe0_rdi_raw_wr: tfe0-rdi-pixel-raw-wr {
     cell-index = <19>;
     node-name = "tfe0-rdi-pixel-raw-wr";
     client-name = "tfe0";
     traffic-data =
     <(256 + 4)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(0 + 4)
     (0 + 5)
     (0 + 6)
     (0 + 9)>;
     parent-node = <&level1_rt1_wr0>;
    };

    tfe1_rdi_raw_wr: tfe1-rdi-pixel-raw-wr {
     cell-index = <20>;
     node-name = "tfe1-rdi-pixel-raw-wr";
     client-name = "tfe1";
     traffic-data =
     <(256 + 4)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(0 + 4)
     (0 + 5)
     (0 + 6)
     (0 + 9)>;
     parent-node = <&level1_rt1_wr0>;
    };

    tfe2_rdi_raw_wr: tfe2-rdi-pixel-raw-wr {
     cell-index = <21>;
     node-name = "tfe2-rdi-pixel-raw-wr";
     client-name = "tfe2";
     traffic-data =
     <(256 + 4)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(0 + 4)
     (0 + 5)
     (0 + 6)
     (0 + 9)>;
     parent-node = <&level1_rt1_wr0>;
    };

    tfe3_rdi_raw_wr: tfe3-rdi-pixel-raw-wr {
     cell-index = <22>;
     node-name = "tfe3-rdi-pixel-raw-wr";
     client-name = "tfe3";
     traffic-data =
     <(256 + 4)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(0 + 4)
     (0 + 5)
     (0 + 6)
     (0 + 9)>;
     parent-node = <&level1_rt1_wr0>;
    };

    ope_all_wr: ipe0-all-wr {
     cell-index = <23>;
     node-name = "ipe0-all-wr";
     client-name = "ipe0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(32 + 2)
     (32 + 3)
     (32 + 4)>;
     parent-node = <&level1_nrt0_wr0>;
    };

    bps_all_wr: bps0-all-wr {
     cell-index = <24>;
     node-name = "bps0-all-wr";
     client-name = "bps0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     parent-node = <&level1_nrt0_wr0>;
    };

    bps_all_rd: bps0-all-rd {
     cell-index = <25>;
     node-name = "bps0-all-rd";
     client-name = "bps0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt1_rd0>;
    };

    ope_ref_rd: ipe0-ref-rd {
     cell-index = <26>;
     node-name = "ipe0-ref-rd";
     client-name = "ipe0";
     traffic-data =
     <(32 + 1)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt1_rd0>;
    };

    ope_in_rd: ipe0-in-rd {
     cell-index = <27>;
     node-name = "ipe0-in-rd";
     client-name = "ipe0";
     traffic-data =
     <(32 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt1_rd0>;
    };

    cre_all_rd: cre-all-rd {
     cell-index = <28>;
     node-name = "cre-all-rd";
     client-name = "cre0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     constituent-paths =
     <(((96 + 31) + 1) + 0)>;
     parent-node = <&level1_nrt2_rd_wr>;
    };

    cre_all_wr: cre-all-wr {
     cell-index = <29>;
     node-name = "cre-all-wr";
     client-name = "cre0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     constituent-paths =
     <(((96 + 31) + 1) + 1)>;
     parent-node = <&level1_nrt2_rd_wr>;
    };

    jpeg_enc0_all_wr: jpeg-enc0-all-wr {
     cell-index = <30>;
     node-name = "jpeg-enc0-all-wr";
     client-name = "jpeg-enc0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     parent-node = <&level1_nrt3_wr0>;
    };

    jpeg_dma0_all_wr: jpeg-dma0-all-wr {
     cell-index = <31>;
     node-name = "jpeg-dma0-all-wr";
     client-name = "jpeg-dma0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <1>;
     parent-node = <&level1_nrt3_wr0>;
    };

    jpeg_enc0_all_rd: jpeg-enc0-all-rd {
     cell-index = <32>;
     node-name = "jpeg-enc0-all-rd";
     client-name = "jpeg-enc0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt4_rd0>;
    };

    jpeg_dma0_all_rd: jpeg-dma0-all-rd {
     cell-index = <33>;
     node-name = "jpeg-dma0-all-rd";
     client-name = "jpeg-dma0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt4_rd0>;
    };

    rt_cdm0_all_rd: rt-cdm0-all-rd {
     cell-index = <34>;
     node-name = "rt-cdm0-all-rd";
     client-name = "rt-cdm0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt5_rd0>;
    };

    rt_cdm1_all_rd: rt-cdm1-all-rd {
     cell-index = <35>;
     node-name = "rt-cdm1-all-rd";
     client-name = "rt-cdm1";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt5_rd0>;
    };

    rt_cdm2_all_rd: rt-cdm2-all-rd {
     cell-index = <36>;
     node-name = "rt-cdm2-all-rd";
     client-name = "rt-cdm2";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level1_nrt5_rd0>;
    };

    icp0_all_rd: icp0-all-rd {
     cell-index = <37>;
     node-name = "icp0-all-rd";
     client-name = "icp0";
     traffic-data = <(256 + 0)>;
     traffic-transaction-type =
     <0>;
     parent-node = <&level2_nrt1_rd>;
    };
   };
  };
 };

 qcom,cam-cdm-intf {
  compatible = "qcom,cam-cdm-intf";
  cell-index = <0>;
  label = "cam-cdm-intf";
  num-hw-cdm = <1>;
  cdm-client-names = "jpegdma",
   "jpegenc";
  status = "ok";
 };

 qcom,rt-cdm0@ac24000 {
  cell-index = <0>;
  compatible = "qcom,cam-rt-cdm2_1";
  label = "rt-cdm";
  reg = <0xac24000 0x400>;
  reg-names = "rt-cdm0";
  reg-cam-base = <0x24000>;
  interrupt-names = "rt-cdm0";
  interrupts = <0 135 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names = "cam_cc_cpas_ahb_clk";
  clocks = <&camcc 32>;
  clock-rates = <0>;
  clock-cntl-level = "svs";
  nrt-device;
  cdm-client-names = "tfe0", "tfe1", "tfe2", "dualtfe";
  config-fifo;
  fifo-depths = <64 0 0 0>;
  cam_hw_pid = <26>;
  single-context-cdm;
  status = "ok";
 };

 qcom,rt-cdm1@ac25000 {
  cell-index = <1>;
  compatible = "qcom,cam-rt-cdm2_1";
  label = "rt-cdm";
  reg = <0xac25000 0x400>;
  reg-names = "rt-cdm1";
  reg-cam-base = <0x25000>;
  interrupt-names = "rt-cdm1";
  interrupts = <0 136 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names = "cam_cc_cpas_ahb_clk";
  clocks = <&camcc 32>;
  clock-rates = <0>;
  clock-cntl-level = "svs";
  nrt-device;
  cdm-client-names = "securetfe0", "securetfe1", "securetfe2";
  config-fifo;
  fifo-depths = <64 0 0 0>;
  cam_hw_pid = <27>;
  single-context-cdm;
  status = "ok";
 };

 qcom,rt-cdm2@ac26000 {
  cell-index = <2>;
  compatible = "qcom,cam-rt-cdm2_1";
  label = "rt-cdm";
  reg = <0xac26000 0x400>;
  reg-names = "rt-cdm2";
  reg-cam-base = <0x26000>;
  interrupt-names = "rt-cdm2";
  interrupts = <0 122 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names = "cam_cc_cpas_ahb_clk";
  clocks = <&camcc 32>;
  clock-rates = <0>;
  clock-cntl-level = "svs";
  nrt-device;
  cdm-client-names = "tfe-lite0";
  config-fifo;
  fifo-depths = <64 0 0 0>;
  cam_hw_pid = <28>;
  single-context-cdm;
  status = "ok";
 };

 qcom,cam-isp {
  compatible = "qcom,cam-isp";
  arch-compat = "tfe";
  status = "ok";
 };

 cam_tfe_csid0: qcom,tfe_csid0@ac62000 {
  cell-index = <0>;
  compatible = "qcom,csid770";
  reg-names = "csid0", "cam_cpas_top";
  reg = <0xac62000 0x1000>,
   <0xac13000 0x1000>;
  reg-cam-base = <0x62000 0x13000>;
  interrupt-names = "csid0";
  interrupts = <0 464 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe0_ahb_clk",
   "tfe0_csid_clk_src",
   "tfe0_csid_clk",
   "tfe0_cphy_rx_clk",
   "tfe0_clk";
                clocks =
   <&camcc 77>,
   <&camcc 82>,
   <&camcc 81>,
   <&camcc 80>,
   <&camcc 78>;
  clock-rates =
   <0 300000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe0_csid_clk_src";
  clock-control-debugfs = "true";
  status = "ok";
 };

 cam_tfe0: qcom,tfe0@ac62000 {
  cell-index = <0>;
  compatible = "qcom,tfe770";
  reg-names = "tfe0";
  reg = <0xac62000 0xD000>;
  reg-cam-base = <0x62000>;
  rt-wrapper-base = <0x62000>;
  interrupt-names = "tfe0";
  interrupts = <0 602 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe0_ahb_clk",
   "tfe0_clk_src",
   "tfe0_clk";
  clocks =
   <&camcc 77>,
   <&camcc 79>,
   <&camcc 78>;
  clock-rates =
   <0 350000000 0>,
   <0 570000000 0>,
   <0 600000000 0>,
   <0 725000000 0>,
   <0 725000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe0_clk_src";
  clock-control-debugfs = "true";
  cam_hw_pid = <4 8>;
  status = "ok";
 };

 cam_tfe_csid1: qcom,tfe_csid1@ac71000 {
  cell-index = <1>;
  compatible = "qcom,csid770";
  reg-names = "csid1", "cam_cpas_top";
  reg = <0xac71000 0x1000>,
   <0xac13000 0x1000>;
  reg-cam-base = <0x71000 0x13000>;
  interrupt-names = "csid1";
  interrupts = <0 466 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe1_ahb_clk",
   "tfe1_csid_clk_src",
   "tfe1_csid_clk",
   "tfe1_cphy_rx_clk",
   "tfe1_clk";
  clocks =
   <&camcc 83>,
   <&camcc 88>,
   <&camcc 87>,
   <&camcc 86>,
   <&camcc 84>;
  clock-rates =
   <0 300000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe1_csid_clk_src";
  clock-control-debugfs = "true";
  status = "ok";
 };

 cam_tfe1: qcom,tfe1@ac71000 {
  cell-index = <1>;
  compatible = "qcom,tfe770";
  reg-names = "tfe1";
  reg = <0xac71000 0xD000>;
  reg-cam-base = <0x71000>;
  rt-wrapper-base = <0x62000>;
  interrupt-names = "tfe1";
  interrupts = <0 604 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe1_ahb_clk",
   "tfe1_clk_src",
   "tfe1_clk";
  clocks =
   <&camcc 83>,
   <&camcc 85>,
   <&camcc 84>;
  clock-rates =
   <0 350000000 0>,
   <0 570000000 0>,
   <0 600000000 0>,
   <0 725000000 0>,
   <0 725000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe1_clk_src";
  clock-control-debugfs = "true";
  cam_hw_pid = <5 9>;
  status = "ok";
 };

 cam_tfe_csid2: qcom,tfe_csid2@ac80000 {
  cell-index = <2>;
  compatible = "qcom,csid770";
  reg-names = "csid2", "cam_cpas_top";
  reg = <0xac80000 0x1000>,
   <0xac13000 0x1000>;
  reg-cam-base = <0x80000 0x13000>;
  interrupt-names = "csid2";
  interrupts = <0 203 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe2_ahb_clk",
   "tfe2_csid_clk_src",
   "tfe2_csid_clk",
   "tfe2_cphy_rx_clk",
   "tfe2_clk";
  clocks =
   <&camcc 89>,
   <&camcc 94>,
   <&camcc 93>,
   <&camcc 92>,
   <&camcc 90>;
  clock-rates =
   <0 300000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe2_csid_clk_src";
  clock-control-debugfs = "true";
  status = "ok";
 };

 cam_tfe2: qcom,tfe2@ac80000 {
  cell-index = <2>;
  compatible = "qcom,tfe770";
  reg-names = "tfe2";
  reg = <0xac80000 0xD000>;
  reg-cam-base = <0x80000>;
  rt-wrapper-base = <0x62000>;
  interrupt-names = "tfe2";
  interrupts = <0 688 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe2_ahb_clk",
   "tfe2_clk_src",
   "tfe2_clk";
  clocks =
   <&camcc 89>,
   <&camcc 91>,
   <&camcc 90>;
  clock-rates =
   <0 350000000 0>,
   <0 570000000 0>,
   <0 600000000 0>,
   <0 725000000 0>,
   <0 725000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe2_clk_src";
  clock-control-debugfs = "true";
  cam_hw_pid = <6 10>;
  status = "ok";
 };

 cam_tfe_csid_lite0: qcom,tfe_csid-lite0@ac8F000 {
  cell-index = <3>;
  compatible = "qcom,csid-lite770";
  reg-names = "csid-lite0", "cam_cpas_top";
  reg = <0xac8F000 0x1000>,
   <0xac13000 0x1000>;
  reg-cam-base = <0x8F000 0x13000>;
  interrupt-names = "csid-lite0";
  interrupts = <0 139 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe3_ahb_clk",
   "tfe3_csid_clk_src",
   "tfe3_csid_clk",
   "tfe3_cphy_rx_clk",
   "tfe3_clk";
  clocks =
   <&camcc 95>,
   <&camcc 100>,
   <&camcc 99>,
   <&camcc 98>,
   <&camcc 96>;
  clock-rates =
   <0 300000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>,
   <0 400000000 0 0 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe3_csid_clk_src";
  clock-control-debugfs = "true";
  status = "ok";
 };

 cam_tfe_lite0: qcom,tfe-lite0@ac8F000 {
  cell-index = <3>;
  compatible = "qcom,tfe-lite770";
  reg-names = "tfe-lite0";
  reg = <0xac8F000 0xD000>;
  reg-cam-base = <0x8F000>;
  rt-wrapper-base = <0x62000>;
  interrupt-names = "tfe-lite0";
  interrupts = <0 156 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "tfe3_ahb_clk",
   "tfe3_clk_src",
   "tfe3_clk";
  clocks =
   <&camcc 95>,
   <&camcc 97>,
   <&camcc 96>;
  clock-rates =
   <0 350000000 0>,
   <0 570000000 0>,
   <0 600000000 0>,
   <0 725000000 0>,
   <0 725000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo";
  src-clock-name = "tfe3_clk_src";
  clock-control-debugfs = "true";
  cam_hw_pid = <11>;
  status = "ok";
 };

 cam_csiphy_tpg13: qcom,tpg13@acf6000 {
  cell-index = <13>;
  phy-id = <2>;
  compatible = "qcom,cam-tpg1031";
  reg-names = "tpg0", "cam_cpas_top";
  reg = <0xacf6000 0x400>,
   <0xac13000 0x1000>;
  reg-cam-base = <0xf6000 0x13000>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  interrupt-names = "tpg0";
  interrupts = <0 413 1>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy2_clk",
   "csi2phytimer_clk_src",
   "csi2phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 47>,
   <&camcc 42>,
   <&camcc 41>;
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  src-clock-name = "cphy_rx_clk_src";
  status = "ok";
 };

 cam_csiphy_tpg14: qcom,tpg14@acf7000 {
  cell-index = <14>;
  phy-id = <3>;
  compatible = "qcom,cam-tpg1031";
  reg-names = "tpg1", "cam_cpas_top";
  reg = <0xacf7000 0x400>,
   <0xac13000 0x1000>;
  reg-cam-base = <0xf7000 0x13000>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  interrupt-names = "tpg1";
  interrupts = <0 416 1>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy3_clk",
   "csi3phytimer_clk_src",
   "csi3phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 48>,
   <&camcc 44>,
   <&camcc 43>;
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  src-clock-name = "cphy_rx_clk_src";
  status = "ok";
 };

 cam_csiphy_tpg15: qcom,tpg15@acf6000 {
  cell-index = <15>;
  phy-id = <2>;
  hw-no-ops;
  compatible = "qcom,cam-tpg1031";
  reg-names = "tpg0", "cam_cpas_top";
  reg = <0xacf6000 0x400>,
   <0xac13000 0x1000>;
  reg-cam-base = <0xf6000 0x13000>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  interrupt-names = "tpg0";
  interrupts = <0 413 1>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy2_clk",
   "csi2phytimer_clk_src",
   "csi2phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 47>,
   <&camcc 42>,
   <&camcc 41>;
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  src-clock-name = "cphy_rx_clk_src";
  status = "ok";
 };

 cam_csiphy_tpg16: qcom,tpg16@acf6000 {
  cell-index = <16>;
  phy-id = <2>;
  hw-no-ops;
  compatible = "qcom,cam-tpg1031";
  reg-names = "tpg0", "cam_cpas_top";
  reg = <0xacf6000 0x400>,
   <0xac13000 0x1000>;
  reg-cam-base = <0xf6000 0x13000>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  interrupt-names = "tpg0";
  interrupts = <0 413 1>;
  shared-clks = <1 0 0 0>;
  clock-names = "cphy_rx_clk_src",
   "csiphy2_clk",
   "csi2phytimer_clk_src",
   "csi2phytimer_clk";
  clocks = <&camcc 33>,
   <&camcc 47>,
   <&camcc 42>,
   <&camcc 41>;
  clock-rates =
   <300000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>,
   <400000000 0 300000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
  src-clock-name = "cphy_rx_clk_src";
  status = "ok";
 };

 qcom,cam-icp {
  compatible = "qcom,cam-icp";
  compat-hw-name = "qcom,icp",
   "qcom,ipe0",
   "qcom,bps";
  num-icp = <1>;
  num-ipe = <1>;
  num-bps = <1>;
  status = "ok";
  icp_pc_en;
  icp_use_pil;
 };

 cam_icp: qcom,icp {
  cell-index = <0>;
  compatible = "qcom,cam-icp_v2";
  icp-version = <0x0200>;
  reg = <0xac01000 0x400>,
   <0xac01800 0x400>,
   <0xac04000 0x1000>;
  reg-names = "icp_csr", "icp_cirq", "icp_wd0";
  reg-cam-base = <0x1000 0x1800 0x4000>;
  interrupt-names = "icp";
  interrupts = <0 463 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  memory-region = <&camera_mem>;
  clock-names =
   "icp_clk_src",
   "icp_clk";
  clocks =
   <&camcc 53>,
   <&camcc 52>;
  clock-rates =
   <400000000 0>,
   <480000000 0>,
   <600000000 0>,
   <600000000 0>,
   <600000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
   "turbo";
  nrt-device;
  src-clock-name = "icp_clk_src";
  clock-control-debugfs = "true";
  fw_name = "CAMERA_ICP";
  ubwc-ipe-fetch-cfg = <0x7173 0x717b>;
  ubwc-ipe-write-cfg = <0x161cf 0x161ef>;
  ubwc-bps-fetch-cfg = <0x707b 0x7083>;
  ubwc-bps-write-cfg = <0x161ef 0x1620f>;
  qos-val = <0x00000A0A>;
  cam_hw_pid = <14>;
  status = "ok";
 };

 cam_ipe0: qcom,ipe0@ac42000 {
  cell-index = <0>;
  compatible = "qcom,cam-ipe680";
  reg = <0xac42000 0xC000>;
  reg-names = "ipe0_top";
  reg-cam-base = <0x42000>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "ope0_ahb_clk",
   "ope0_areg_clk",
   "ope0_clk",
   "ope0_clk_src";
  clocks =
   <&camcc 68>,
   <&camcc 69>,
   <&camcc 70>,
   <&camcc 71>;

  clock-rates =
   <0 100000000 0 300000000>,
   <0 150000000 0 410000000>,
   <0 200000000 0 460000000>,
   <0 240000000 0 600000000>,
   <0 240000000 0 700000000>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
   "turbo";
  nrt-device;
  src-clock-name = "ope0_clk_src";
  clock-control-debugfs = "true";
  cam_hw_pid = <16 2>;
  status = "ok";
 };

 cam_bps: qcom,bps@ac2c000 {
  cell-index = <0>;
  compatible = "qcom,cam-bps680";
  reg = <0xac2c000 0x8000>;
  reg-names = "bps_top";
  reg-cam-base = <0x2c000>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "bps_ahb_clk",
   "bps_areg_clk",
   "bps_clk",
   "bps_clk_src";
  clocks =
   <&camcc 17>,
   <&camcc 18>,
   <&camcc 19>,
   <&camcc 20>;

  clock-rates =
   <0 100000000 0 300000000>,
   <0 150000000 0 410000000>,
   <0 200000000 0 460000000>,
   <0 240000000 0 600000000>,
   <0 240000000 0 700000000>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
   "turbo";
  nrt-device;
  src-clock-name = "bps_clk_src";
  clock-control-debugfs = "true";
  cam_hw_pid = <17 3>;
  status = "ok";
 };

 qcom,cam-cre {
  compatible = "qcom,cam-cre";
  compat-hw-name = "qcom,cre";
  num-cre = <1>;
  status = "ok";
 };

 cre: qcom,cre@acfa000 {
  cell-index = <0>;
  compatible = "qcom,cre";
  reg = <0xacfa000 0x200>,
   <0xacfa400 0xB0>,
   <0xacfa700 0x300>;
  reg-names =
   "cre_top",
   "cre_bus_rd",
   "cre_bus_wr";
  reg-cam-base = <0xFA000 0xFA400 0xFA700>;
  interrupts = <0 469 1>;
  interrupt-names = "cre";
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  clock-names =
   "cre_ahb_clk",
   "cre_clk_src",
   "cre_clk";
  clocks =
   <&camcc 34>,
   <&camcc 36>,
   <&camcc 35>;
  clock-rates =
   <0 300000000 0>,
   <0 400000000 0>,
   <0 400000000 0>,
   <0 600000000 0>,
   <0 600000000 0>;
  clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
   "turbo";
  src-clock-name = "cre_clk_src";
  clock-control-debugfs = "true";
  cam_hw_pid = <13 12>;
  status = "ok";
 };

 qcom,cam-jpeg {
  compatible = "qcom,cam-jpeg";
  compat-hw-name = "qcom,jpegenc",
   "qcom,jpegdma";
  num-jpeg-enc = <1>;
  num-jpeg-dma = <1>;
  status = "ok";
 };

 cam_jpeg_enc: qcom,jpegenc@ac2a000 {
  cell-index = <0>;
  compatible = "qcom,cam_jpeg_enc_770";
  reg-names = "jpege_hw", "cam_camnoc";
  reg = <0xac2a000 0x1000>,
   <0xac19000 0xB000>;
  reg-cam-base = <0x2a000 0x19000>;
  interrupt-names = "jpeg";
  interrupts = <0 137 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  shared-clks = <1 0>;
  clock-names =
   "jpegenc_clk_src",
   "jpegenc_clk";
  clocks =
   <&camcc 57>,
   <&camcc 56>;
  clock-rates = <600000000 0>;
  src-clock-name = "jpegenc_clk_src";
  clock-cntl-level = "nominal";
  nrt-device;
  cam_hw_pid = <21 22>;
  cam_hw_rd_mid = <0>;
  cam_hw_wr_mid = <1>;
  status = "ok";
 };

 cam_jpeg_dma: qcom,jpegdma@ac2b000 {
  cell-index = <0>;
  compatible = "qcom,cam_jpeg_dma_770";
  reg-names = "jpegdma_hw", "cam_camnoc";
  reg = <0xac2b000 0x1000>,
   <0xac19000 0xB000>;
  reg-cam-base = <0x2b000 0x19000>;
  interrupt-names = "jpegdma";
  interrupts = <0 138 1>;
  regulator-names = "camss";
  camss-supply = <&cam_cc_camss_top_gdsc>;
  shared-clks = <1 0>;
  clock-names =
   "jpegdma_clk_src",
   "jpegdma_clk";
  clocks =
   <&camcc 57>,
   <&camcc 56>;
  clock-rates = <600000000 0>;
  src-clock-name = "jpegdma_clk_src";
  clock-cntl-level = "nominal";
  nrt-device;
  cam_hw_pid = <20 23>;
  cam_hw_rd_mid = <0>;
  cam_hw_wr_mid = <1>;
  status = "ok";
 };
};
# 11 "/home/luuxis/evo/kernel/motorola/sm8550/arch/arm64/boot/dts/vendor/qcom/camera/crow-camera.dts" 2
/ {
 model = "Qualcomm Technologies, Inc. Crow";
 compatible = "qcom,crow";
 qcom,msm-id = <608 0x10000>;
 qcom,board-id = <0 0>;
};