* CoreSight Components: CoreSight components are compliant with the ARM CoreSight architecture specification and can be connected in various topologies to suit a particular SoCs tracing needs. These trace components can generally be classified as sinks, links and sources. Trace data produced by one or more sources flows through the intermediate links connecting the source to the currently selected sink. Each CoreSight component device should use these properties to describe its hardware characteristcs. * Required properties for all components *except* non-configurable replicators and non-configurable funnels: * compatible: These have to be supplemented with "arm,primecell" as drivers are using the AMBA bus interface. Possible values include: - Embedded Trace Buffer (version 1.0): "arm,coresight-etb10", "arm,primecell"; - Trace Port Interface Unit: "arm,coresight-tpiu", "arm,primecell"; - Trace Memory Controller, used for Embedded Trace Buffer(ETB), Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configuration. The configuration mode (ETB, ETF, ETR) is discovered at boot time when the device is probed. "arm,coresight-tmc", "arm,primecell"; - Trace Programmable Funnel: "arm,coresight-dynamic-funnel", "arm,primecell"; "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For backward compatibility and will be removed) - Embedded Trace Macrocell (version 3.x) and Program Flow Trace Macrocell: "arm,coresight-etm3x", "arm,primecell"; - Embedded Trace Macrocell (version 4.x), with memory mapped access. "arm,coresight-etm4x", "arm,primecell"; - Embedded Trace Macrocell (version 4.x), with system register access only. "arm,coresight-etm4x-sysreg"; - Coresight programmable Replicator : "arm,coresight-dynamic-replicator", "arm,primecell"; - System Trace Macrocell: "arm,coresight-stm", "arm,primecell"; [1] - Coresight Address Translation Unit (CATU) "arm,coresight-catu", "arm,primecell"; - Coresight Cross Trigger Interface (CTI): "arm,coresight-cti", "arm,primecell"; See coresight-cti.yaml for full CTI definitions. * reg: physical base address and length of the register set(s) of the component. * clocks: the clocks associated to this component. * clock-names: the name of the clocks referenced by the code. Since we are using the AMBA framework, the name of the clock providing the interconnect should be "apb_pclk", and some coresight blocks also have an additional clock "atclk", which clocks the core of that coresight component. The latter clock is optional. * port or ports: see "Graph bindings for Coresight" below. * Additional required property for Embedded Trace Macrocell (version 3.x and version 4.x): * cpu: the cpu phandle this ETM/PTM is affined to. Do not assume it to default to CPU0 if omitted. * Additional required properties for System Trace Macrocells (STM): * reg: along with the physical base address and length of the register set as described above, another entry is required to describe the mapping of the extended stimulus port area. * reg-names: the only acceptable values are "stm-base" and "stm-stimulus-base", each corresponding to the areas defined in "reg". * Required properties for Coresight Cross Trigger Interface (CTI) See coresight-cti.yaml for full CTI definitions. * Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators and non-configurable funnels: * compatible: Currently supported value is (note the absence of the AMBA markee): - Coresight Non-configurable Replicator: "arm,coresight-static-replicator"; "arm,coresight-replicator"; (OBSOLETE. For backward compatibility and will be removed) - Coresight Non-configurable Funnel: "arm,coresight-static-funnel"; * port or ports: see "Graph bindings for Coresight" below. * Optional properties for all components: * arm,coresight-loses-context-with-cpu : boolean. Indicates that the hardware will lose register context on CPU power down (e.g. CPUIdle). An example of where this may be needed are systems which contain a coresight component and CPU in the same power domain. When the CPU powers down the coresight component also powers down and loses its context. This property is currently only used for the ETM 4.x driver. - Coresight Trace, Profiling & Diagnostic module: "qcom,coresight-tpda" "qcom,coresight-tpdm" - Coresight control register: "qcom,coresight-csr" - Coresight Hardware Event "qcom,coresight-hwevent" - Coresight dummy device: "qcom,coresight-dummy" - Coresight remote ETM: "qcom,coresight-remote-etm" * port or ports: see "Graph bindings for Coresight" below. * Additional required property for coresight-tgu devices: * tgu-steps: must be present. Indicates number of steps supported by the TGU. * tgu-conditions: must be present. Indicates the number of conditions supported by the TGU. * tgu-regs: must be present. Indicates the number of regs supported by the TGU. * tgu-timer-counters: must be present. Indicates the number of timers and counters available in the TGU to do a comparision. * Optional properties for all components: * reg-names: names corresponding to each reg property value. * qcom,proxy-regs: List of regulators required. * qcom,proxy-clks: List of additional clocks required. * Optional properties for ETM/PTMs: * arm,cp14: must be present if the system accesses ETM/PTM management registers via co-processor 14. * qcom,tupwr-disable: For ETM, don't keep trace unit powered across power collapse. * qcom,skip-power-up: boolean. Indicates that an implementation can skip powering up the trace unit. TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems since ETMs are in the same power domain as their CPU cores. This property is required to identify such systems with hardware errata where the CPU watchdog counter is stopped when TRCPDCR.PU is set. * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR (embedded trace router). This property is obsolete. The buffer size can be configured dynamically via buffer_size property in sysfs. * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely use the SG mode on this system. * usb_bam_support: boolean. Indicates that the TMC-ETR supports usb bam connection. * csr-atid-offset: When there are two ETRs, each of the ETR has its own ATID config csr registers. It is the ETR_ATID0 register offset to the CSR base address. * csr-irqctrl-offset: When there are two ETRs, each of the ETR has its own ETRIRQCTRL register. It is the IRQCTRL register offset to the CSR base address. * byte-cntr-name: The name of the byte-cntr * byte-cntr-class-name: The name for class_create in byte-cntr driver. * qcom,mem_support: boolean. Indicates that TMC-ETR supports memory mode. * qcom,eth_support: boolean. Indicates that TMC-ETR supports QDSS over ethernet function. * Optional property for CATU and APSS : * interrupts : Exactly one SPI may be listed for reporting the address error for CATU and four interrupts for TGU to get trigger from four type of events. * Required property for TPDAs: * qcom,tpda-atid: must be present. Specifies the ATID for TPDA. * Optional properties for TPDAs: * qcom,bc-elem-size: specifies the BC element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, bc element size). * qcom,tc-elem-size: specifies the TC element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, tc element size). * qcom,dsb-elem-size: specifies the DSB element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, dsb element size). * qcom,cmb-elem-size: specifies the CMB element size supported by each monitor connected to the aggregator on each port. Should be specified in pairs (port, cmb element size). * Optional properties for TPDM: * qcom,clk-enable: specifies whether additional clock bit needs to be set for M4M TPDM. * qcom,msr-fix-req: boolean, indicating if MSRs need to be programmed after enabling the subunit. * qcom,cmb-msr-skip: boolean, indicating cmb MSR don't need to be programmed. * qcom,hw-enable-check: Check if the tpdm need to be probed as some tpdms are not enabled in secure device. * Optional properties for CSRs: * qcom,usb-bam-support: boolean, indicates CSR has the ability to operate on usb bam, include enable,disable and flush. * qcom,hwctrl-set-support: boolean, indicates CSR has the ability to operate on to "HWCTRL" register. * qcom,set-byte-cntr-support:boolean, indicates CSR has the ability to operate on to "BYTECNT" register. * qcom,timestamp-support:boolean, indicates CSR support sys interface to read timestamp value. * qcom,perflsheot-set-support: boolean, indicates PERFLSHEOT bit of USBFLSHCTRL register will be set to 1 when usb sink is enabled. * qcom,msr-support: boolean, indicates that CSR supports configure msr config for tpdm. * Required property for Remote ETMs: * qcom,inst-id: must be present. QMI instance id for remote ETMs. * Optional properties for funnels: * source: specifies the source that binds to this output port. Only trace from that source routes to this output port. * qcom,duplicate-funnel: boolean, indicates its a duplicate of an existing funnel. Funnel devices are now capable of supporting multiple-input and multiple-output configuration with in built hardware filtering for TPDM devices. Each set of input-output combination is treated as independent funnel device. funnel-base-dummy and funnel-base-real reg-names must be specified when this property is enabled. * reg-names: funnel-base-dummy: dummy register space used by a duplicate funnel. Should be a valid register address space that no other device is using. * reg-names: funnel-base-real: actual register space for the duplicate funnel. * Optional property for configurable replicators: * qcom,replicator-loses-context: boolean. Indicates that the replicator will lose register context when AMBA clock is removed which is observed in some replicator designs. * Optional property for CTIs: * qcom,extended_cti: boolean. Indicates that cti is an extended cti. * Optional property for all source components: * atid: atid for the trace data of the source. If the data has two atids, configure two ids for the source. This is for multi ETR sink. Graph bindings for Coresight ------------------------------- Coresight components are interconnected to create a data path for the flow of trace data generated from the "sources" to their collection points "sink". Each coresight component must describe the "input" and "output" connections. The connections must be described via generic DT graph bindings as described by the "bindings/graph.txt", where each "port" along with an "endpoint" component represents a hardware port and the connection. * All output ports must be listed inside a child node named "out-ports" * All input ports must be listed inside a child node named "in-ports". * Port address must match the hardware port number. Example: 1. Sinks etb@20010000 { compatible = "arm,coresight-etb10", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; in-ports { port { etb_in_port: endpoint@0 { remote-endpoint = <&replicator_out_port0>; }; }; }; }; tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; in-ports { port { tpiu_in_port: endpoint@0 { remote-endpoint = <&replicator_out_port1>; }; }; }; }; etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20070000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; in-ports { port { etr_in_port: endpoint { remote-endpoint = <&replicator2_out_port0>; }; }; }; out-ports { port { etr_out_port: endpoint { remote-endpoint = <&catu_in_port>; }; }; }; }; 2. Links replicator { /* non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell". */ compatible = "arm,coresight-static-replicator"; out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ port@0 { reg = <0>; replicator_out_port0: endpoint { remote-endpoint = <&etb_in_port>; }; }; port@1 { reg = <1>; replicator_out_port1: endpoint { remote-endpoint = <&tpiu_in_port>; }; }; }; in-ports { port { replicator_in_port0: endpoint { remote-endpoint = <&funnel_out_port0>; }; }; }; }; funnel { /* * non-configurable funnel don't show up on the AMBA * bus. As such no need to add "arm,primecell". */ compatible = "arm,coresight-static-funnel"; clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; out-ports { port { combo_funnel_out: endpoint { remote-endpoint = <&top_funnel_in>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; combo_funnel_in0: endpoint { remote-endpoint = <&cluster0_etf_out>; }; }; port@1 { reg = <1>; combo_funnel_in1: endpoint { remote-endpoint = <&cluster1_etf_out>; }; }; }; }; funnel@20040000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x20040000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; out-ports { port { funnel_out_port0: endpoint { remote-endpoint = <&replicator_in_port0>; }; }; }; in-ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; funnel_in_port0: endpoint { remote-endpoint = <&ptm0_out_port>; }; }; port@1 { reg = <1>; funnel_in_port1: endpoint { remote-endpoint = <&ptm1_out_port>; }; }; port@2 { reg = <2>; funnel_in_port2: endpoint { remote-endpoint = <&etm0_out_port>; }; }; }; }; 3. Sources ptm@2201c000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0 0x2201c000 0 0x1000>; cpu = <&cpu0>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; out-ports { port { ptm0_out_port: endpoint { remote-endpoint = <&funnel_in_port0>; }; }; }; }; ptm@2201d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0 0x2201d000 0 0x1000>; cpu = <&cpu1>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; out-ports { port { ptm1_out_port: endpoint { remote-endpoint = <&funnel_in_port1>; }; }; }; }; 4. STM stm@20100000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x180000>; reg-names = "stm-base", "stm-stimulus-base"; clocks = <&soc_smc50mhz>; clock-names = "apb_pclk"; out-ports { port { stm_out_port: endpoint { remote-endpoint = <&main_funnel_in_port2>; }; }; }; }; 5. CATU catu@207e0000 { compatible = "arm,coresight-catu", "arm,primecell"; reg = <0 0x207e0000 0 0x1000>; clocks = <&oscclk6a>; clock-names = "apb_pclk"; interrupts = ; in-ports { port { catu_in_port: endpoint { remote-endpoint = <&etr_out_port>; }; }; }; }; 6. TGUs ipcb_tgu: tgu@6b0c000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b999>; reg = <0x06B0C000 0x1000>; reg-names = "tgu-base"; tgu-steps = <3>; tgu-conditions = <4>; tgu-regs = <4>; tgu-timer-counters = <8>; interrupts = , , , ; coresight-name = "coresight-tgu-ipcb"; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; }; [1]. There is currently two version of STM: STM32 and STM500. Both have the same HW interface and as such don't need an explicit binding name.