# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings

description: |
  These bindings describe the DMA engine included in the Xilinx ZynqMP
  DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
  channels for a video stream, 1 channel for a graphics stream, and 2 channels
  for an audio stream).

maintainers:
  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>

allOf:
  - $ref: "../dma-controller.yaml#"

properties:
  "#dma-cells":
    const: 1
    description: |
      The cell is the DMA channel ID (see dt-bindings/dma/xlnx-zynqmp-dpdma.h
      for a list of channel IDs).

  compatible:
    const: xlnx,zynqmp-dpdma

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    description: The AXI clock
    maxItems: 1

  clock-names:
    const: axi_clk

required:
  - "#dma-cells"
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dma: dma-controller@fd4c0000 {
      compatible = "xlnx,zynqmp-dpdma";
      reg = <0xfd4c0000 0x1000>;
      interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
      interrupt-parent = <&gic>;
      clocks = <&dpdma_clk>;
      clock-names = "axi_clk";
      #dma-cells = <1>;
    };

...
