#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,camcc-lemans.h>
#include <dt-bindings/clock/qcom,dispcc-monaco_auto.h>
#include <dt-bindings/clock/qcom,gcc-monaco_auto.h>
#include <dt-bindings/clock/qcom,gpucc-lemans.h>
#include <dt-bindings/clock/qcom,videocc-lemans.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,monaco_auto.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	model = "Qualcomm Technologies, Inc. Monaco AUTO";
	compatible = "qcom,monaco_auto";
	qcom,msm-id = <532 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	memory { device_type = "memory"; reg = <0 0 0 0>; };

	reserved_memory: reserved-memory { };

	chosen: chosen {
		bootargs = "cpufreq.default_governor=performance";
	};

	soc: soc { };

	firmware: firmware { };

	aliases {
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			next-level-cache = <&L2_2>;
			#cooling-cells = <2>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			next-level-cache = <&L2_3>;
			#cooling-cells = <2>;
			L2_3: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@10000 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10000>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 2>;
			next-level-cache = <&L2_4>;
			#cooling-cells = <2>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_1>;
				L3_1: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-level = <3>;
				};

			};
		};

		CPU5: cpu@10100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10100>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 2>;
			next-level-cache = <&L2_5>;
			#cooling-cells = <2>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_1>;
			};
		};

		CPU6: cpu@10200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10200>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 2>;
			next-level-cache = <&L2_6>;
			#cooling-cells = <2>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_1>;
			};
		};

		CPU7: cpu@10300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x10300>;
			enable-method = "psci";
			cpu-idle-states = <&SILVER_OFF &SILVER_RAIL_OFF>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			cpu-release-addr = <0x0 0xc0000000>;
			qcom,freq-domain = <&cpufreq_hw 2>;
			next-level-cache = <&L2_7>;
			#cooling-cells = <2>;
			L2_7: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_1>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	idle-states {
		entry-method = "psci";

		SILVER_OFF: silver-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <449>;
			exit-latency-us = <801>;
			min-residency-us = <1574>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		SILVER_RAIL_OFF: silver-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <602>;
			exit-latency-us = <961>;
			min-residency-us = <4288>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_OFF: gold-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <549>;
			exit-latency-us = <901>;
			min-residency-us = <1774>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_RAIL_OFF: gold-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <702>;
			exit-latency-us = <1061>;
			min-residency-us = <4488>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_CLUSTER_D4: gold-cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			entry-latency-us = <2752>;
			exit-latency-us = <3048>;
			min-residency-us = <6118>;
			arm,psci-suspend-param = <0x41000044>;
		};

		SILVER_CLUSTER_D4: silver-cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			entry-latency-us = <2552>;
			exit-latency-us = <2848>;
			min-residency-us = <5908>;
			arm,psci-suspend-param = <0x41000044>;
		};

		APSS_OFF: cluster-e3 { /* E3 */
			compatible = "domain-idle-state";
			entry-latency-us = <3263>;
			exit-latency-us = <6562>;
			min-residency-us = <9987>;
			arm,psci-suspend-param = <0x42000144>;
		};
	};
};

&firmware {
};

&reserved_memory {

	smem_region: smem@90900000 {
		no-map;
		reg = <0x0 0x90900000 0x0 0x200000>;
	};

	aop_cmd_db_mem: aop_cmd_db_region@90860000 {
		compatible = "qcom,cmd-db";
		no-map;
		reg = <0x0 0x90860000 0x0 0x20000>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	tlmm: pinctrl@f000000 {
		compatible = "qcom,monaco_auto-pinctrl";
		reg = <0xf000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,pdc";
		reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
		qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
				  <55 306 4>, <59 312 3>, <62 374 2>,
				  <64 434 2>, <66 438 2>, <70 520 1>,
				  <73 523 1>, <118 568 6>, <124 609 3>,
				  <159 638 1>, <160 720 3>, <169 728 30>,
				  <199 416 2>, <201 449 1>, <202 89 1>,
				  <203 451 1>, <204 462 1>, <205 264 1>,
				  <206 579 1>, <207 653 1>, <208 656 1>,
				  <209 659 1>, <210 122 1>, <211 699 1>,
				  <212 705 1>, <213 450 1>, <214 643 2>,
				  <216 646 5>, <221 390 5>, <226 700 2>,
				  <228 440 1>, <229 663 1>, <230 524 2>,
				  <232 612 3>, <235 723 5>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	apps_rsc: rsc@18200000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x18200000 0x10000>,
		      <0x18210000 0x10000>,
		      <0x18220000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		qcom,drv-count = <3>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&CLUSTER_PD2>;

		apps_rsc_drv2: drv@2 {
			qcom,drv-id = <2>;
			qcom,tcs-offset = <0xd00>;
			channel@0 {
				qcom,tcs-config = <ACTIVE_TCS    2>,
						  <SLEEP_TCS     3>,
						  <WAKE_TCS      3>,
						  <CONTROL_TCS   0>,
						  <FAST_PATH_TCS 0>;
			};

			apps_bcm_voter: bcm_voter {
				compatible = "qcom,bcm-voter";
			};

			rpmhcc: qcom,rpmhcc {
				compatible = "qcom,lemans-rpmh-clk";
				#clock-cells = <1>;
			};
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD0>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD0>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD0>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD0>;
		};

		CPU_PD4: cpu-pd4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD1>;
		};

		CPU_PD5: cpu-pd5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD1>;
		};

		CPU_PD6: cpu-pd6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD1>;
		};

		CPU_PD7: cpu-pd7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD1>;
		};

		CLUSTER_PD0: cluster-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD2>;
			domain-idle-states = <&GOLD_CLUSTER_D4>;
		};

		CLUSTER_PD1: cluster-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD2>;
			domain-idle-states = <&SILVER_CLUSTER_D4>;
		};

		CLUSTER_PD2: cluster-pd2 {
			#power-domain-cells = <0>;
			domain-idle-states = <&APSS_OFF>;
		};
	};

	wdog: qcom,wdt@17c10000 {
		compatible = "qcom,msm-watchdog";
		reg = <0x17c10000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	cluster-device0 {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD0>;
	};

	cluster-device1 {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD1>;
	};

	cluster-device2 {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD2>;
	};

	sys-pm-vx@c320000 {
		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-monaco-auto";
		reg = <0xc320000 0x0400>;
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";
	};

	soc-sleep-stats@c3f0000 {
		compatible = "qcom,rpmh-sleep-stats";
		reg = <0xc3f0000 0x400>;
		qcom,drv-max = <0x14>;
		ss-name = "adsp", "cdsp", "apss";
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";
		ddr-freq-update;
	};

	subsystem-sleep-stats@c3f0000 {
		compatible = "qcom,subsystem-sleep-stats";
		reg = <0xc3f0000 0x400>;
		ddr-freq-update;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	memtimer: timer@17c20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@17c21000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c21000 0x1000>,
			      <0x17c22000 0x1000>;
		};

		frame@17c23000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c23000 0x1000>;
			status = "disabled";
		};

		frame@17c25000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c25000 0x1000>;
			status = "disabled";
		};

		frame@17c27000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c27000 0x1000>;
			status = "disabled";
		};

		frame@17c29000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c29000 0x1000>;
			status = "disabled";
		};

		frame@17c2b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2b000 0x1000>;
			status = "disabled";
		};

		frame@17c2d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c2d000 0x1000>;
			status = "disabled";
		};
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		hwlocks = <&tcsr_mutex 3>;
	};

	ipcc_mproc: qcom,ipcc@408000 {
		compatible = "qcom,ipcc";
		reg = <0x408000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	aoss_qmp: power-controller@c300000 {

		compatible = "qcom,sm8150-aoss-qmp";
		reg = <0xc300000 0x400>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
		mbox-names = "aop_qmp";
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_AOP
			      IPCC_MPROC_SIGNAL_GLINK_QMP
			      IRQ_TYPE_EDGE_RISING>;

		#clock-cells = <0>;
		#power-domain-cells = <1>;
	};

	qmp_aop: qcom,qmp-aop@c300000 {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-cdsp@1799000c {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-gpdsp0 {
		compatible = "qcom,smp2p";
		qcom,smem = <617>, <616>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP0
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <17>;

		gpdsp0_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		gpdsp0_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	thermal_zones: thermal-zones {
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_1_pipe_clk: pcie_1_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_phy_aux_clk: pcie_phy_aux_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_phy_aux_clk";
			#clock-cells = <0>;
		};

		rxc0_ref_clk: rxc0_ref_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "rxc0_ref_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_0_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_1_clk";
			#clock-cells = <0>;
		};

		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_tx_symbol_0_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_prim_pipe_clk: usb3_phy_wrapper_gcc_usb30_prim_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_prim_pipe_clk";
			#clock-cells = <0>;
		};
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,monaco_auto-camcc", "syscon";
		reg = <0xade0000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
			<&gcc GCC_CAMERA_AHB_CLK>, <&sleep_clk>;
		clock-names = "bi_tcxo", "bi_tcxo_ao", "iface", "sleep_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,monaco_auto-dispcc", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
			 <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,monaco_auto-gcc", "syscon";
		reg = <0x100000 0xc7018>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie_0_pipe_clk>,
			 <&pcie_1_pipe_clk>, <&pcie_phy_aux_clk>,
			 <&rxc0_ref_clk>, <&sleep_clk>, <&ufs_phy_rx_symbol_0_clk>,
			 <&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
			 <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;
		clock-names = "bi_tcxo", "pcie_0_pipe_clk",
			      "pcie_1_pipe_clk", "pcie_phy_aux_clk",
			      "rxc0_ref_clk", "sleep_clk", "ufs_phy_rx_symbol_0_clk",
			      "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
			      "usb3_phy_wrapper_gcc_usb30_prim_pipe_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,monaco_auto-gpucc", "syscon";
		reg = <0x3d90000 0xa000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_CFG_AHB_CLK>,
			 <&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
		clock-names = "bi_tcxo", "iface", "gpll0_out_main", "gpll0_out_main_div";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@abf0000 {
		compatible =  "qcom,lemans-videocc", "syscon";
		reg = <0xabf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mx-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
			 <&gcc GCC_VIDEO_AHB_CLK>, <&sleep_clk>;
		clock-names = "bi_tcxo", "bi_tcxo_ao", "iface", "sleep_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cpufreq_hw: qcom,cpufreq-hw@18591000 {
		compatible = "qcom,cpufreq-epss";
		reg = <0x18591000 0x1000>, <0x18594000 0x1000>, <0x18593000 0x1000>;
		reg-names = "freq-domain0", "freq-domain1", "freq-domain2";

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
		clock-names = "xo", "alternate";

		#freq-domain-cells = <1>;
	};

	qcom,cpufreq-hw-debug@18591000 {
		compatible = "qcom,cpufreq-hw-epss-debug";
		qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, <&cpufreq_hw 2>;
	};

	apsscc: syscon@182a0000 {
		compatible = "syscon";
		reg = <0x182a0000 0x1c>;
	};

	mccc: syscon@90ba000 {
		compatible = "syscon";
		reg = <0x90ba000 0x54>;
	};

	debugcc: debug-clock-controller@0 {
		compatible = "qcom,monaco_auto-debugcc";
		qcom,gcc = <&gcc>;
		qcom,camcc = <&camcc>;
		qcom,dispcc = <&dispcc>;
		qcom,gpucc = <&gpucc>;
		qcom,videocc = <&videocc>;
		qcom,apsscc = <&apsscc>;
		qcom,mccc = <&mccc>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			 <&camcc 0>,
			 <&dispcc 0>,
			 <&gcc 0>,
			 <&gpucc 0>,
			 <&videocc 0>;
		clock-names = "xo_clk_src",
			      "camcc",
			      "dispcc",
			      "gcc",
			      "gpucc",
			      "videocc";
		#clock-cells = <1>;
	};

	clk_virt: interconnect@0 {
		compatible = "qcom,monaco_auto-clk_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect@1 {
		compatible = "qcom,monaco_auto-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	config_noc: interconnect@014C0000 {
		compatible = "qcom,monaco_auto-config_noc";
		reg = <0x014C0000 0x13080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	system_noc: interconnect@01680000 {
		compatible = "qcom,monaco_auto-system_noc";
		reg = <0x01680000 0x15080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	aggre1_noc:interconnect@016C0000 {
		compatible = "qcom,monaco_auto-aggre1_noc";
		reg = <0x016C0000 0x17080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	aggre2_noc: interconnect@01700000 {
		compatible = "qcom,monaco_auto-aggre2_noc";
		reg = <0x01700000 0x1A080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	pcie_anoc: interconnect@01760000 {
		compatible = "qcom,monaco_auto-pcie_anoc";
		reg = <0x01760000 0xC080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	gpdsp_anoc: interconnect@01780000 {
		compatible = "qcom,monaco_auto-gpdsp_anoc";
		reg = <0x01780000 0xD080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	mmss_noc: interconnect@017A0000 {
		compatible = "qcom,monaco_auto-mmss_noc";
		reg = <0x017A0000 0x40000>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	lpass_ag_noc: interconnect@03C40000 {
		compatible = "qcom,monaco_auto-lpass_ag_noc";
		reg = <0x3C40000 0x17200>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	dc_noc: interconnect@090E0000 {
		compatible = "qcom,monaco_auto-dc_noc";
		reg = <0x090E0000 0x5080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	gem_noc: interconnect@09100000 {
		compatible = "qcom,monaco_auto-gem_noc";
		reg = <0x09100000 0xF7080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};

	nspa_noc: interconnect@260C0000 {
		compatible = "qcom,monaco_auto-nspa_noc";
		reg = <0x260C0000 0x16080>;
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		qcom,skip-qos;
	};
};

#include "monaco_auto-pinctrl.dtsi"
#include "monaco_auto-regulators.dtsi"
#include "msm-arm-smmu-monaco_auto.dtsi"
#include "monaco_auto-thermal.dtsi"
#include "lemans-gdsc.dtsi"

/* CAM_CC GDSCs */
&cam_cc_titan_top_gdsc {
	reg = <0xadf31a0 0x4>;
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

/* DISP_CC GDSCs */
&disp_cc_mdss_core_gdsc {
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&disp_cc_mdss_core_int2_gdsc {
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

/* GCC GDSCs */
&gcc_emac0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&gcc_pcie_0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&gcc_pcie_1_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&gcc_ufs_phy_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_usb20_prim_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_usb30_prim_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

/* GPU_CC GDSCs */
&gpu_cc_cx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_cc_gx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
	status = "ok";
};

/* VIDEO_CC GDSCs */
&video_cc_mvs0_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&video_cc_mvs0c_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	status = "ok";
};

&video_cc_mvs1_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&video_cc_mvs1c_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	status = "ok";
};