// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * */ #include #include #include #include #include #include #include #include #include #include "icc-rpmh.h" #include "qnoc-qos.h" static const struct regmap_config icc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, }; static struct qcom_icc_node qpic_core_master = { .name = "qpic_core_master", .id = MASTER_QPIC_CORE, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_QPIC_CORE }, }; static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", .id = MASTER_QUP_CORE_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_QUP_CORE_0 }, }; static struct qcom_icc_node qnm_cnoc = { .name = "qnm_cnoc", .id = MASTER_CNOC_DC_NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 4, .links = { SLAVE_LAGG_CFG, SLAVE_MCCC_MASTER, SLAVE_GEM_NOC_CFG, SLAVE_SNOOP_BWMON }, }; static struct qcom_icc_qosbox alm_sys_tcu_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x30000 }, .config = &(struct qos_config) { .prio = 6, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", .id = MASTER_SYS_TCU, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &alm_sys_tcu_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_node chm_apps = { .name = "chm_apps", .id = MASTER_APPSS_PROC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 3, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC, SLAVE_MEM_NOC_PCIE_SNOC }, }; static struct qcom_icc_node qnm_gemnoc_cfg = { .name = "qnm_gemnoc_cfg", .id = MASTER_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_GEM_NOC }, }; static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", .id = MASTER_MSS_PROC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 3, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC, SLAVE_MEM_NOC_PCIE_SNOC }, }; static struct qcom_icc_qosbox qnm_pcie_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x31000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, }; static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", .id = MASTER_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_pcie_qos, .num_links = 2, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC }, }; static struct qcom_icc_qosbox qnm_snoc_sf_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x32000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, }; static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .id = MASTER_SNOC_SF_MEM_NOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qnm_snoc_sf_qos, .num_links = 3, .links = { SLAVE_GEM_NOC_CNOC, SLAVE_LLCC, SLAVE_MEM_NOC_PCIE_SNOC }, }; static struct qcom_icc_qosbox xm_gic_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x33000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_gic = { .name = "xm_gic", .id = MASTER_GIC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_gic_qos, .num_links = 1, .links = { SLAVE_LLCC }, }; static struct qcom_icc_qosbox xm_ipa2pcie_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x34000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_ipa2pcie = { .name = "xm_ipa2pcie", .id = MASTER_IPA_PCIE, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_ipa2pcie_qos, .num_links = 1, .links = { SLAVE_MEM_NOC_PCIE_SNOC }, }; static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", .id = MASTER_LLCC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_EBI1 }, }; static struct qcom_icc_qosbox xm_pcie3_0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xa000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_pcie3_0 = { .name = "xm_pcie3_0", .id = MASTER_PCIE_0, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_pcie3_0_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_qosbox xm_pcie3_1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xb000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_pcie3_1 = { .name = "xm_pcie3_1", .id = MASTER_PCIE_1, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_pcie3_1_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_qosbox xm_pcie3_2_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0xc000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_pcie3_2 = { .name = "xm_pcie3_2", .id = MASTER_PCIE_2, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_pcie3_2_qos, .num_links = 1, .links = { SLAVE_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_qosbox qhm_audio_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x3b000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_audio = { .name = "qhm_audio", .id = MASTER_AUDIO, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_audio_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox qhm_gic_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x38000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_gic = { .name = "qhm_gic", .id = MASTER_GIC_AHB, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_gic_qos, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_SF }, }; static struct qcom_icc_node qhm_pcie_rscc = { .name = "qhm_pcie_rscc", .id = MASTER_PCIE_RSCC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 31, .links = { SLAVE_ETH0_CFG, SLAVE_ETH1_CFG, SLAVE_AUDIO, SLAVE_CLK_CTL, SLAVE_CRYPTO_0_CFG, SLAVE_IMEM_CFG, SLAVE_IPA_CFG, SLAVE_IPC_ROUTER_CFG, SLAVE_CNOC_MSS, ICBDI_SLAVE_MVMSS_CFG, SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG, SLAVE_PCIE_2_CFG, SLAVE_PDM, SLAVE_PRNG, SLAVE_QDSS_CFG, SLAVE_QPIC, SLAVE_QUP_0, SLAVE_SDCC_1, SLAVE_SDCC_4, SLAVE_SPMI_VGI_COEX, SLAVE_TCSR, SLAVE_TLMM, SLAVE_USB3, SLAVE_USB3_PHY_CFG, SLAVE_DDRSS_CFG, SLAVE_SNOC_CFG, SLAVE_PCIE_ANOC_CFG, SLAVE_IMEM, SLAVE_QDSS_STM, SLAVE_TCU }, }; static struct qcom_icc_qosbox qhm_qdss_bam_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x37000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_qdss_bam = { .name = "qhm_qdss_bam", .id = MASTER_QDSS_BAM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_qdss_bam_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox qhm_qpic_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x36000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_qpic = { .name = "qhm_qpic", .id = MASTER_QPIC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_qpic_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox qhm_qup0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x35000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qhm_qup0 = { .name = "qhm_qup0", .id = MASTER_QUP_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qhm_qup0_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", .id = MASTER_ANOC_SNOC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_SF }, }; static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", .id = MASTER_GEM_NOC_CNOC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 32, .links = { SLAVE_ETH0_CFG, SLAVE_ETH1_CFG, SLAVE_AUDIO, SLAVE_CLK_CTL, SLAVE_CRYPTO_0_CFG, SLAVE_IMEM_CFG, SLAVE_IPA_CFG, SLAVE_IPC_ROUTER_CFG, SLAVE_CNOC_MSS, ICBDI_SLAVE_MVMSS_CFG, SLAVE_PCIE_0_CFG, SLAVE_PCIE_1_CFG, SLAVE_PCIE_2_CFG, SLAVE_PCIE_RSC_CFG, SLAVE_PDM, SLAVE_PRNG, SLAVE_QDSS_CFG, SLAVE_QPIC, SLAVE_QUP_0, SLAVE_SDCC_1, SLAVE_SDCC_4, SLAVE_SPMI_VGI_COEX, SLAVE_TCSR, SLAVE_TLMM, SLAVE_USB3, SLAVE_USB3_PHY_CFG, SLAVE_DDRSS_CFG, SLAVE_SNOC_CFG, SLAVE_PCIE_ANOC_CFG, SLAVE_IMEM, SLAVE_QDSS_STM, SLAVE_TCU }, }; static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", .id = MASTER_GEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 3, .links = { SLAVE_PCIE_0, SLAVE_PCIE_1, SLAVE_PCIE_2 }, }; static struct qcom_icc_node qnm_system_noc_cfg = { .name = "qnm_system_noc_cfg", .id = MASTER_SNOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_SNOC }, }; static struct qcom_icc_node qnm_system_noc_pcie_cfg = { .name = "qnm_system_noc_pcie_cfg", .id = MASTER_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { SLAVE_SERVICE_PCIE_ANOC }, }; static struct qcom_icc_qosbox qxm_crypto_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x34000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", .id = MASTER_CRYPTO, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qxm_crypto_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox qxm_ipa_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x39000 }, .config = &(struct qos_config) { .prio = 1, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .id = MASTER_IPA, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qxm_ipa_qos, .num_links = 1, .links = { SLAVE_SNOC_GEM_NOC_SF }, }; static struct qcom_icc_qosbox qxm_mvmss_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x3e000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node qxm_mvmss = { .name = "qxm_mvmss", .id = MASTER_MVMSS, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &qxm_mvmss_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox xm_emac_0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x3c000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_emac_0 = { .name = "xm_emac_0", .id = MASTER_EMAC_0, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_emac_0_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox xm_emac_1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x3d000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_emac_1 = { .name = "xm_emac_1", .id = MASTER_EMAC_1, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_emac_1_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox xm_qdss_etr0_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x33000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_qdss_etr0 = { .name = "xm_qdss_etr0", .id = MASTER_QDSS_ETR, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_qdss_etr0_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox xm_qdss_etr1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x32000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_qdss_etr1 = { .name = "xm_qdss_etr1", .id = MASTER_QDSS_ETR_1, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_qdss_etr1_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox xm_sdc1_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x31000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_sdc1 = { .name = "xm_sdc1", .id = MASTER_SDCC_1, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_sdc1_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox xm_sdc4_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x3a000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", .id = MASTER_SDCC_4, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_sdc4_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_qosbox xm_usb3_qos = { .regs = icc_qnoc_qos_regs[ICC_QNOC_QOSGEN_TYPE_RPMH], .num_ports = 1, .offsets = { 0x30000 }, .config = &(struct qos_config) { .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, }; static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", .id = MASTER_USB3_0, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .qosbox = &xm_usb3_qos, .num_links = 1, .links = { SLAVE_A1NOC_CFG }, }; static struct qcom_icc_node qpic_core_slave = { .name = "qpic_core_slave", .id = SLAVE_QPIC_CORE, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", .id = SLAVE_QUP_CORE_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_lagg = { .name = "qhs_lagg", .id = SLAVE_LAGG_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_mccc_master = { .name = "qhs_mccc_master", .id = SLAVE_MCCC_MASTER, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_gemnoc = { .name = "qns_gemnoc", .id = SLAVE_GEM_NOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qss_snoop_bwmon = { .name = "qss_snoop_bwmon", .id = SLAVE_SNOOP_BWMON, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_gemnoc_cnoc = { .name = "qns_gemnoc_cnoc", .id = SLAVE_GEM_NOC_CNOC, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_GEM_NOC_CNOC }, }; static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", .id = SLAVE_LLCC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_LLCC }, }; static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", .id = SLAVE_MEM_NOC_PCIE_SNOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_GEM_NOC_PCIE_SNOC }, }; static struct qcom_icc_node srvc_gemnoc = { .name = "srvc_gemnoc", .id = SLAVE_SERVICE_GEM_NOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node ebi = { .name = "ebi", .id = SLAVE_EBI1, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", .id = SLAVE_ANOC_PCIE_GEM_NOC, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_ANOC_PCIE_GEM_NOC }, }; static struct qcom_icc_node ps_eth0_cfg = { .name = "ps_eth0_cfg", .id = SLAVE_ETH0_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node ps_eth1_cfg = { .name = "ps_eth1_cfg", .id = SLAVE_ETH1_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_audio = { .name = "qhs_audio", .id = SLAVE_AUDIO, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", .id = SLAVE_CLK_CTL, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_crypto_cfg = { .name = "qhs_crypto_cfg", .id = SLAVE_CRYPTO_0_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", .id = SLAVE_IMEM_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", .id = SLAVE_IPA_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", .id = SLAVE_IPC_ROUTER_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", .id = SLAVE_CNOC_MSS, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_mvmss_cfg = { .name = "qhs_mvmss_cfg", .id = ICBDI_SLAVE_MVMSS_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_pcie0_cfg = { .name = "qhs_pcie0_cfg", .id = SLAVE_PCIE_0_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_pcie1_cfg = { .name = "qhs_pcie1_cfg", .id = SLAVE_PCIE_1_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_pcie2_cfg = { .name = "qhs_pcie2_cfg", .id = SLAVE_PCIE_2_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_pcie_rscc = { .name = "qhs_pcie_rscc", .id = SLAVE_PCIE_RSC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_pdm = { .name = "qhs_pdm", .id = SLAVE_PDM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", .id = SLAVE_PRNG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_qdss_cfg = { .name = "qhs_qdss_cfg", .id = SLAVE_QDSS_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_qpic = { .name = "qhs_qpic", .id = SLAVE_QPIC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_qup0 = { .name = "qhs_qup0", .id = SLAVE_QUP_0, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_sdc1 = { .name = "qhs_sdc1", .id = SLAVE_SDCC_1, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", .id = SLAVE_SDCC_4, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_spmi_vgi_coex = { .name = "qhs_spmi_vgi_coex", .id = SLAVE_SPMI_VGI_COEX, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_tcsr = { .name = "qhs_tcsr", .id = SLAVE_TCSR, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", .id = SLAVE_TLMM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", .id = SLAVE_USB3, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qhs_usb3_phy = { .name = "qhs_usb3_phy", .id = SLAVE_USB3_PHY_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node qns_a1noc = { .name = "qns_a1noc", .id = SLAVE_A1NOC_CFG, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_ANOC_SNOC }, }; static struct qcom_icc_node qns_ddrss_cfg = { .name = "qns_ddrss_cfg", .id = SLAVE_DDRSS_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_CNOC_DC_NOC }, }; static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", .id = SLAVE_SNOC_GEM_NOC_SF, .channels = 1, .buswidth = 16, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_SF_MEM_NOC }, }; static struct qcom_icc_node qns_system_noc_cfg = { .name = "qns_system_noc_cfg", .id = SLAVE_SNOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_SNOC_CFG }, }; static struct qcom_icc_node qns_system_noc_pcie_cfg = { .name = "qns_system_noc_pcie_cfg", .id = SLAVE_PCIE_ANOC_CFG, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 1, .links = { MASTER_PCIE_ANOC_CFG }, }; static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", .id = SLAVE_IMEM, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node srvc_pcie_system_noc = { .name = "srvc_pcie_system_noc", .id = SLAVE_SERVICE_PCIE_ANOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node srvc_system_noc = { .name = "srvc_system_noc", .id = SLAVE_SERVICE_SNOC, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node xs_pcie_0 = { .name = "xs_pcie_0", .id = SLAVE_PCIE_0, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node xs_pcie_1 = { .name = "xs_pcie_1", .id = SLAVE_PCIE_1, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node xs_pcie_2 = { .name = "xs_pcie_2", .id = SLAVE_PCIE_2, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node xs_qdss_stm = { .name = "xs_qdss_stm", .id = SLAVE_QDSS_STM, .channels = 1, .buswidth = 4, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", .id = SLAVE_TCU, .channels = 1, .buswidth = 8, .noc_ops = &qcom_qnoc4_ops, .num_links = 0, }; static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", .voter_idx = 0, .num_nodes = 1, .nodes = { &qxm_crypto }, }; static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .voter_idx = 0, .keepalive = true, .enable_mask = 0x1, .num_nodes = 39, .nodes = { &qhm_pcie_rscc, &qnm_gemnoc_cnoc, &ps_eth0_cfg, &ps_eth1_cfg, &qhs_audio, &qhs_clk_ctl, &qhs_crypto_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_mss_cfg, &qhs_mvmss_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie2_cfg, &qhs_pcie_rscc, &qhs_pdm, &qhs_prng, &qhs_qdss_cfg, &qhs_qpic, &qhs_qup0, &qhs_sdc1, &qhs_sdc4, &qhs_spmi_vgi_coex, &qhs_tcsr, &qhs_tlmm, &qhs_usb3, &qhs_usb3_phy, &qns_ddrss_cfg, &qns_system_noc_cfg, &qns_system_noc_pcie_cfg, &qxs_imem, &srvc_pcie_system_noc, &srvc_system_noc, &xs_pcie_0, &xs_pcie_1, &xs_pcie_2, &xs_qdss_stm, &xs_sys_tcu_cfg }, }; static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .voter_idx = 0, .keepalive = true, .num_nodes = 1, .nodes = { &ebi }, }; static struct qcom_icc_bcm bcm_qp0 = { .name = "QP0", .voter_idx = 0, .num_nodes = 1, .nodes = { &qpic_core_slave }, }; static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .voter_idx = 0, .keepalive = true, .vote_scale = 1, .num_nodes = 1, .nodes = { &qup0_core_slave }, }; static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .voter_idx = 0, .keepalive = true, .num_nodes = 1, .nodes = { &qns_llcc }, }; static struct qcom_icc_bcm bcm_sh1 = { .name = "SH1", .voter_idx = 0, .enable_mask = 0x1, .num_nodes = 10, .nodes = { &alm_sys_tcu, &chm_apps, &qnm_gemnoc_cfg, &qnm_mdsp, &qnm_snoc_sf, &xm_gic, &xm_ipa2pcie, &qns_gemnoc_cnoc, &qns_pcie, &srvc_gemnoc }, }; static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .voter_idx = 0, .keepalive = true, .num_nodes = 1, .nodes = { &qns_gemnoc_sf }, }; static struct qcom_icc_bcm bcm_sn1 = { .name = "SN1", .voter_idx = 0, .enable_mask = 0x1, .num_nodes = 21, .nodes = { &xm_pcie3_0, &xm_pcie3_1, &xm_pcie3_2, &qhm_audio, &qhm_gic, &qhm_qdss_bam, &qhm_qpic, &qhm_qup0, &qnm_gemnoc_pcie, &qnm_system_noc_cfg, &qnm_system_noc_pcie_cfg, &qxm_crypto, &qxm_ipa, &qxm_mvmss, &xm_emac_0, &xm_emac_1, &xm_qdss_etr0, &xm_qdss_etr1, &xm_sdc1, &xm_sdc4, &xm_usb3 }, }; static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", .voter_idx = 0, .num_nodes = 2, .nodes = { &qnm_aggre_noc, &qns_a1noc }, }; static struct qcom_icc_bcm bcm_sn4 = { .name = "SN4", .voter_idx = 0, .num_nodes = 2, .nodes = { &qnm_pcie, &qns_pcie_gemnoc }, }; static struct qcom_icc_bcm *clk_virt_bcms[] = { &bcm_qp0, &bcm_qup0, }; static struct qcom_icc_node *clk_virt_nodes[] = { [MASTER_QPIC_CORE] = &qpic_core_master, [MASTER_QUP_CORE_0] = &qup0_core_master, [SLAVE_QPIC_CORE] = &qpic_core_slave, [SLAVE_QUP_CORE_0] = &qup0_core_slave, }; static char *clk_virt_voters[] = { "hlos", }; static struct qcom_icc_desc sdxpinn_clk_virt = { .config = &icc_regmap_config, .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms), .voters = clk_virt_voters, .num_voters = ARRAY_SIZE(clk_virt_voters), }; static struct qcom_icc_bcm *dc_noc_bcms[] = { }; static struct qcom_icc_node *dc_noc_nodes[] = { [MASTER_CNOC_DC_NOC] = &qnm_cnoc, [SLAVE_LAGG_CFG] = &qhs_lagg, [SLAVE_MCCC_MASTER] = &qhs_mccc_master, [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, [SLAVE_SNOOP_BWMON] = &qss_snoop_bwmon, }; static char *dc_noc_voters[] = { "hlos", }; static struct qcom_icc_desc sdxpinn_dc_noc = { .config = &icc_regmap_config, .nodes = dc_noc_nodes, .num_nodes = ARRAY_SIZE(dc_noc_nodes), .bcms = dc_noc_bcms, .num_bcms = ARRAY_SIZE(dc_noc_bcms), .voters = dc_noc_voters, .num_voters = ARRAY_SIZE(dc_noc_voters), }; static struct qcom_icc_bcm *gem_noc_bcms[] = { &bcm_sh0, &bcm_sh1, &bcm_sn4, }; static struct qcom_icc_node *gem_noc_nodes[] = { [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, [MASTER_MSS_PROC] = &qnm_mdsp, [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, [MASTER_GIC] = &xm_gic, [MASTER_IPA_PCIE] = &xm_ipa2pcie, [SLAVE_GEM_NOC_CNOC] = &qns_gemnoc_cnoc, [SLAVE_LLCC] = &qns_llcc, [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, }; static char *gem_noc_voters[] = { "hlos", }; static struct qcom_icc_desc sdxpinn_gem_noc = { .config = &icc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms), .voters = gem_noc_voters, .num_voters = ARRAY_SIZE(gem_noc_voters), }; static struct qcom_icc_bcm *mc_virt_bcms[] = { &bcm_mc0, }; static struct qcom_icc_node *mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, }; static char *mc_virt_voters[] = { "hlos", }; static struct qcom_icc_desc sdxpinn_mc_virt = { .config = &icc_regmap_config, .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms), .voters = mc_virt_voters, .num_voters = ARRAY_SIZE(mc_virt_voters), }; static struct qcom_icc_bcm *pcie_anoc_bcms[] = { &bcm_sn1, &bcm_sn4, }; static struct qcom_icc_node *pcie_anoc_nodes[] = { [MASTER_PCIE_0] = &xm_pcie3_0, [MASTER_PCIE_1] = &xm_pcie3_1, [MASTER_PCIE_2] = &xm_pcie3_2, [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, }; static char *pcie_anoc_voters[] = { "hlos", }; static struct qcom_icc_desc sdxpinn_pcie_anoc = { .config = &icc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), .voters = pcie_anoc_voters, .num_voters = ARRAY_SIZE(pcie_anoc_voters), }; static struct qcom_icc_bcm *system_noc_bcms[] = { &bcm_ce0, &bcm_cn0, &bcm_sn0, &bcm_sn1, &bcm_sn2, }; static struct qcom_icc_node *system_noc_nodes[] = { [MASTER_AUDIO] = &qhm_audio, [MASTER_GIC_AHB] = &qhm_gic, [MASTER_PCIE_RSCC] = &qhm_pcie_rscc, [MASTER_QDSS_BAM] = &qhm_qdss_bam, [MASTER_QPIC] = &qhm_qpic, [MASTER_QUP_0] = &qhm_qup0, [MASTER_ANOC_SNOC] = &qnm_aggre_noc, [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, [MASTER_SNOC_CFG] = &qnm_system_noc_cfg, [MASTER_PCIE_ANOC_CFG] = &qnm_system_noc_pcie_cfg, [MASTER_CRYPTO] = &qxm_crypto, [MASTER_IPA] = &qxm_ipa, [MASTER_MVMSS] = &qxm_mvmss, [MASTER_EMAC_0] = &xm_emac_0, [MASTER_EMAC_1] = &xm_emac_1, [MASTER_QDSS_ETR] = &xm_qdss_etr0, [MASTER_QDSS_ETR_1] = &xm_qdss_etr1, [MASTER_SDCC_1] = &xm_sdc1, [MASTER_SDCC_4] = &xm_sdc4, [MASTER_USB3_0] = &xm_usb3, [SLAVE_ETH0_CFG] = &ps_eth0_cfg, [SLAVE_ETH1_CFG] = &ps_eth1_cfg, [SLAVE_AUDIO] = &qhs_audio, [SLAVE_CLK_CTL] = &qhs_clk_ctl, [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg, [SLAVE_IMEM_CFG] = &qhs_imem_cfg, [SLAVE_IPA_CFG] = &qhs_ipa, [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, [SLAVE_CNOC_MSS] = &qhs_mss_cfg, [ICBDI_SLAVE_MVMSS_CFG] = &qhs_mvmss_cfg, [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rscc, [SLAVE_PDM] = &qhs_pdm, [SLAVE_PRNG] = &qhs_prng, [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, [SLAVE_QPIC] = &qhs_qpic, [SLAVE_QUP_0] = &qhs_qup0, [SLAVE_SDCC_1] = &qhs_sdc1, [SLAVE_SDCC_4] = &qhs_sdc4, [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, [SLAVE_TCSR] = &qhs_tcsr, [SLAVE_TLMM] = &qhs_tlmm, [SLAVE_USB3] = &qhs_usb3, [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, [SLAVE_A1NOC_CFG] = &qns_a1noc, [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, [SLAVE_SNOC_CFG] = &qns_system_noc_cfg, [SLAVE_PCIE_ANOC_CFG] = &qns_system_noc_pcie_cfg, [SLAVE_IMEM] = &qxs_imem, [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_system_noc, [SLAVE_SERVICE_SNOC] = &srvc_system_noc, [SLAVE_PCIE_0] = &xs_pcie_0, [SLAVE_PCIE_1] = &xs_pcie_1, [SLAVE_PCIE_2] = &xs_pcie_2, [SLAVE_QDSS_STM] = &xs_qdss_stm, [SLAVE_TCU] = &xs_sys_tcu_cfg, }; static char *system_noc_voters[] = { "hlos", }; static struct qcom_icc_desc sdxpinn_system_noc = { .config = &icc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, .num_bcms = ARRAY_SIZE(system_noc_bcms), .voters = system_noc_voters, .num_voters = ARRAY_SIZE(system_noc_voters), }; static int qnoc_probe(struct platform_device *pdev) { int ret; ret = qcom_icc_rpmh_probe(pdev); if (ret) dev_err(&pdev->dev, "failed to register ICC provider\n"); else dev_info(&pdev->dev, "Registered SDXPINN ICC\n"); return ret; } static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,sdxpinn-clk_virt", .data = &sdxpinn_clk_virt}, { .compatible = "qcom,sdxpinn-dc_noc", .data = &sdxpinn_dc_noc}, { .compatible = "qcom,sdxpinn-gem_noc", .data = &sdxpinn_gem_noc}, { .compatible = "qcom,sdxpinn-mc_virt", .data = &sdxpinn_mc_virt}, { .compatible = "qcom,sdxpinn-pcie_anoc", .data = &sdxpinn_pcie_anoc}, { .compatible = "qcom,sdxpinn-system_noc", .data = &sdxpinn_system_noc}, { } }; MODULE_DEVICE_TABLE(of, qnoc_of_match); static struct platform_driver qnoc_driver = { .probe = qnoc_probe, .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-sdxpinn", .of_match_table = qnoc_of_match, .sync_state = qcom_icc_rpmh_sync_state, }, }; static int __init qnoc_driver_init(void) { return platform_driver_register(&qnoc_driver); } core_initcall(qnoc_driver_init); MODULE_DESCRIPTION("SDXPINN NoC driver"); MODULE_LICENSE("GPL v2");