/*
 * Copyright (c) 2022, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&tlmm {
	sar_int_default: sar_int_default {
			mux {
				pins = "gpio127";
				function =  "gpio";
			};
			config {
				pins = "gpio127";
				num-grp-pins = <1>;
				drive-strength = <2>;
				bias-pull-up;
			};
	};

	sar_int_sleep: sar_int_sleep {
			mux {
				pins = "gpio127";
				function =  "gpio";
			};
			config {
				pins = "gpio127";
				num-grp-pins = <1>;
				drive-strength = <2>;
				bias-pull-up;
			};
	};
};

&qupv3_se8_i2c {
	status = "ok";
	sx937x@2c { /* SAR sensor */
		compatible = "Semtech,sx937x";
		reg = <0x2c>;
		Semtech,power-supply-type = <0>;
		cap_vdd-supply = <&pm7550_l7>;
		pinctrl-names = "default","sleep";
		pinctrl-0 = <&sar_int_default>;
		pinctrl-1 = <&sar_int_sleep>;
		interrupt-parent = <&tlmm>;
		interrupts = <127 0x02>;
		interrupt-names = "capsense0_irq";
		Semtech,nirq-gpio= <&tlmm 127 0x02>;
		/*use PH4/5/6 as the reference sensor
		set it to 0xff if the ref-phases-x is not used*/
		Semtech,ref-phases-a = <4>;
		Semtech,ref-phases-b = <5>;
		Semtech,ref-phases-c = <6>;
		Semtech,button-flag = <0x1f>;
		Semtech,reg-num = <63>;
		Semtech,reg-init = <
			0x4004 0x74
			0x8020 0x32
			0x8028 0x46E
			0x8034 0x46E
			0x8040 0x46E
			0x804C 0x46E
			0x8058 0x46E
			0x8064 0x46E
			0x8070 0x46E
			0x807C 0x85C
			0x8030 0x924925
			0x803C 0x92C924
			0x8048 0x964924
			0x8054 0xB24924
			0x8060 0x92492C
			0x806C 0x924964
			0x8078 0x925924
			0x8084 0x0
			0x8098 0x7739
			0x80B8 0x7840
			0x80D8 0x824D
			0x80F8 0x2B2B
			0x8118 0x6540
			0x8138 0x0
			0x8158 0x0
			0x8178 0x0
			0x80A0 0x22220001
			0x80C0 0x14140002
			0x80E0 0x20200002
			0x8100 0x1B210003
			0x8120 0x1D1D0003
			0x8140 0x0
			0x8160 0x0
			0x8180 0x0
			0x8188 0x8000014
			0x818C 0x8000015
			0x8190 0x8000016
			0x8194 0x0
			0x8090 0x2AD67000
			0x80B0 0x2DD67000
			0x80D0 0x2DD67000
			0x80F0 0x1CD67000
			0x8110 0x2DD67000
			0x8130 0x2AD67000
			0x8150 0x0
			0x8170 0x0
			0x8088 0x300000
			0x80A8 0x300000
			0x80C8 0x300000
			0x80E8 0x300000
			0x8108 0x300000
			0x8128 0x300000
			0x8148 0x300000
			0x8168 0x0
			0x808C 0xE0600080
			0x80AC 0xE0600080
			0x80CC 0xE0600080
			0x80EC 0xE0600080
			0x810C 0xE06000C0
			0x812C 0xE06000C0
			0x814C 0xE0600018
			0x816C 0x0
			0x8024 0x7F00
		>;
		status = "ok";
	};
	awinic_sar@12 {
		/* common node */
		compatible = "awinic,aw_sar";
		reg = < 0x12 >;
		//aw_sar,regulator-power-supply = <1>;
		sar-num = < 0 >;
		interrupt-parent = < &tlmm >;
		interrupts = <127 0x02>;
		interrupt-names = "awinic_irq";
		irq-gpio = <&tlmm 127 0x02>;
		//vcc0-supply = <&L12A>;
		channel_use_flag = <0x1f>;
		aw_sar,use_plug_cail;
		aw_sar,update_fw;
		/* private node belongs to aw963xx */
		start-mode = < 1 >; // 0: start in rom  1: start in ram
		irq-mux = < 2 >; // set csx as irq pin. config this field when connect to aw96308/aw96310
		status = "okay";
	};
};