#include #include &soc { /* Primary USB port related controller */ usb0: ssusb@4e00000 { compatible = "qcom,dwc-usb3-msm"; reg = <0x4e00000 0x100000>; reg-names = "core_base"; #address-cells = <1>; #size-cells = <1>; ranges; interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, <&mpm 12 IRQ_TYPE_LEVEL_HIGH>, <&mpm 91 IRQ_TYPE_EDGE_RISING>, <&mpm 90 IRQ_TYPE_EDGE_RISING>; interrupt-names = "pwr_event_irq", "ss_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq"; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&gcc GCC_USB30_PRIM_SLEEP_CLK>, <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "sleep_clk", "utmi_clk"; resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; dpdm-supply = <&usb2_phy0>; qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ 0x120 /* GSI_DBL_ADDR_H */ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, <&system_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>, <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; qcom,interconnect-values-nom = /* NOMINAL Votes */ <240000 700000>, <0 2400>, <0 40000>; qcom,interconnect-values-svs = /* SVS Votes */ <240000 700000>, <0 2400>, <0 40000>; dwc3@4e00000 { compatible = "snps,dwc3"; reg = <0x4e00000 0xe000>; iommus = <&apps_smmu 0x120 0x0>; qcom,iommu-dma = "atomic"; qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>; interrupt-parent = <&intc>; interrupts = ; usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; tx-fifo-resize; snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3-u1u2-disable; snps,usb3_lpm_capable; usb-core-id = <0>; maximum-speed = "super-speed"; dr_mode = "otg"; usb-role-switch; }; qcom,usbbam@0x04f04000 { compatible = "qcom,usb-bam-msm"; reg = <0x04f04000 0x17000>; interrupts = ; qcom,usb-bam-fifo-baseaddr = <0xc121000>; qcom,usb-bam-num-pipes = <4>; qcom,disable-clk-gating; qcom,usb-bam-override-threshold = <0x4001>; qcom,usb-bam-max-mbps-highspeed = <400>; qcom,usb-bam-max-mbps-superspeed = <3600>; qcom,reset-bam-on-connect; qcom,pipe0 { label = "ssusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; qcom,dir = <1>; qcom,pipe-num = <0>; qcom,peer-bam = <0>; qcom,peer-bam-physical-address = <0x08064000>; qcom,src-bam-pipe-index = <0>; qcom,dst-bam-pipe-index = <0>; qcom,data-fifo-offset = <0x0>; qcom,data-fifo-size = <0x1800>; qcom,descriptor-fifo-offset = <0x1800>; qcom,descriptor-fifo-size = <0x800>; }; }; }; /* Primary USB port related High Speed PHY */ usb2_phy0: hsphy@1613000 { compatible = "qcom,usb-hsphy-snps-femto"; reg = <0x1613000 0x110>, <0x1612000 0x4>; reg-names = "hsusb_phy_base", "eud_enable_reg"; vdd-supply = <&L4A>; vdda18-supply = <&L12A>; vdda33-supply = <&L15A>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, <&gcc GCC_AHB2PHY_USB_CLK>; clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; qcom,param-override-seq = <0xa6 0x6c>, /* override_x0 */ <0x85 0x70>, /* override_x1 */ <0x16 0x74>; /* override_x2 */ }; /* Primary USB port related QMP USB PHY */ usb_qmp_dp_phy: ssphy@1615000 { compatible = "qcom,usb-ssphy-qmp-dp-combo"; reg = <0x01615000 0x3000>; reg-names = "qmp_phy_base"; core-supply = <&L18A>; qcom,vdd-voltage-level = <0 880000 880000>; clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_USB3_PRIM_CLKREF_CLK>, <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, <&gcc GCC_AHB2PHY_USB_CLK>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", "ref_clk", "com_aux_clk","cfg_ahb_clk"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; reset-names = "global_phy_reset", "phy_reset"; qcom,qmp-phy-reg-offset = ; qcom,qmp-phy-init-seq = /* */ ; }; usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; usb_audio_qmi_dev { compatible = "qcom,usb-audio-qmi-dev"; iommus = <&apps_smmu 0x1cf 0x0>; qcom,iommu-dma = "disabled"; qcom,usb-audio-stream-id = <0xf>; qcom,usb-audio-intr-num = <2>; }; };