#include <dt-bindings/clock/qcom,gcc-sa410m.h>
#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h>

&soc {
	/* Primary USB port related controller */
	usb0: ssusb@4e00000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0x4e00000 0x100000>;
		reg-names = "core_base";

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pwr_event_irq", "ss_phy_irq",
				"hs_phy_irq";

		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
		clocks = <&gcc  GCC_USB30_PRIM_MASTER_CLK>,
			<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_USB3_PRIM_CLKREF_EN>,
			<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
				"xo", "sleep_clk", "utmi_clk";

		resets = <&gcc GCC_USB30_PRIM_BCR>;
		reset-names = "core_reset";

		qcom,core-clk-rate = <133333333>;
		qcom,core-clk-rate-hs = <66666667>;

		qcom,gsi-reg-offset =
			 <0x0fc /* GSI_GENERAL_CFG */
			 0x110 /* GSI_DBL_ADDR_L */
			 0x120 /* GSI_DBL_ADDR_H */
			 0x130 /* GSI_RING_BASE_ADDR_L */
			 0x144 /* GSI_RING_BASE_ADDR_H */
			 0x1a4>; /* GSI_IF_STS */

		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
		interconnects = <&sys_noc MASTER_USB3 &bimc_noc SLAVE_EBI_CH0>,
				<&sys_noc MASTER_USB3 &config_noc SLAVE_IPA_CFG>,
				<&bimc_noc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;

		dwc3@4e00000 {
			compatible = "snps,dwc3";
			reg = <0x4e00000 0xe000>;

			iommus = <&apps_smmu 0x120 0x0>;
			qcom,iommu-dma = "bypass";
			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;

			usb-phy = <&qusb_phy0>, <&usb_qmp_phy>;
			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
			tx-fifo-resize;
			snps,disable-clk-gating;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x0>;
			snps,is-utmi-l1-suspend;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis_u2_susphy_quirk;
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
	};

	/* Primary USB port related High Speed PHY */
	qusb_phy0: qusb@1613000 {
		compatible = "qcom,qusb2phy";
		reg = <0x01613000 0x180>,
			<0x003cb250 0x4>,
			<0x01b40258 0x4>,
			<0x01612000 0x4>;
		reg-names = "qusb_phy_base",
			"tcsr_clamp_dig_n_1p8",
			"tune2_efuse_addr",
			"eud_enable_reg";

		vdd-supply = <&pm2250_l12>;
		vdda18-supply = <&pm2250_l13>;
		vdda33-supply = <&pm2250_l21>;
		qcom,vdd-voltage-level = <0 925000 970000>;
		qcom,tune2-efuse-bit-pos = <25>;
		qcom,tune2-efuse-num-bits = <4>;
		qcom,qusb-phy-init-seq = <0xc8 0x80
					0xb3 0x84
					0x83 0x88
					0xc0 0x8c
					0x30 0x08
					0x79 0x0c
					0x21 0x10
					0x14 0x9c
					0x80 0x04
					0x9f 0x1c
					0x00 0x18>;
		phy_type = "utmi";
		qcom,phy-clk-scheme = "cmos";
		qcom,major-rev = <1>;

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
			<&gcc GCC_AHB2PHY_USB_CLK>;
		clock-names =  "ref_clk_src", "cfg_ahb_clk";

		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		reset-names = "phy_reset";
	};

	usb_qmp_phy: ssphy@1615000 {
		compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
		reg = <0x01615000 0x1000>,
			<0x03cb244 0x4>;
		reg-names = "qmp_phy_base",
			"vls_clamp_reg";

		vdd-supply = <&pm2250_l12>;
		core-supply = <&pm2250_l13>;
		qcom,vdd-voltage-level = <0 925000 970000>;
		qcom,core-voltage-level = <0 1800000 1800000>;
		qcom,qmp-phy-init-seq =
			/* <reg_offset, value, delay> */
				<USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x14
				 USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08
				 USB3PHY_QSERDES_COM_CLK_SELECT 0x30
				 USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x06
				 USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00
				 USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x08
				 USB3PHY_QSERDES_COM_BG_TRIM 0x0f
				 USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x01
				 USB3PHY_QSERDES_COM_HSCLK_SEL 0x00
				 USB3PHY_QSERDES_COM_DEC_START_MODE0 0x82
				 USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55
				 USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x55
				 USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x03
				 USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0b
				 USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x16
				 USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x28
				 USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x80
				 USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00
				 USB3PHY_QSERDES_COM_CORECLK_DIV 0x0a
				 USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x15
				 USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x34
				 USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00
				 USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00
				 USB3PHY_QSERDES_COM_CORE_CLK_EN 0x00
				 USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00
				 USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x00
				 USB3PHY_QSERDES_COM_BG_TIMER 0x0a
				 USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x01
				 USB3PHY_QSERDES_COM_SSC_PER1 0x31
				 USB3PHY_QSERDES_COM_SSC_PER2 0x01
				 USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x00
				 USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x00
				 USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0xde
				 USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07
				 USB3PHY_QSERDES_COM_PLL_IVCO 0x0f
				 USB3PHY_QSERDES_COM_CMN_CONFIG 0x06
				 USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x80
				 USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x01
				 USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b
				 USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b
				 USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x00
				 USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x00
				 USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x00
				 USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x00
				 USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x00
				 USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x00
				 USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0a
				 USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0a
				 USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x06
				 USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x06
				 USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75
				 USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75
				 USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x02
				 USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x02
				 USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e
				 USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e
				 USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18
				 USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18
				 USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
				 USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
				 USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80
				 USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80
				 USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x0a
				 USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x0a
				 USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x03
				 USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x03
				 USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16
				 USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16
				 USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x00
				 USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x00
				 USB3PHY_QSERDES_RXA_RX_MODE_00 0x00
				 USB3PHY_QSERDES_RXB_RX_MODE_00 0x00
				 USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x10
				 USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x10
				 USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
				 USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
				 USB3PHY_QSERDES_TXA_LANE_MODE_1 0xc6
				 USB3PHY_QSERDES_TXB_LANE_MODE_1 0xc6
				 USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x00
				 USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x00
				 USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x00
				 USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x00
				 USB3PHY_PCS_TXMGN_V0 0x9f
				 USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x17
				 USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0f
				 USB3PHY_PCS_FLL_CNTRL2 0x83
				 USB3PHY_PCS_FLL_CNTRL1 0x02
				 USB3PHY_PCS_FLL_CNT_VAL_L 0x09
				 USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0xa2
				 USB3PHY_PCS_FLL_MAN_CODE 0x85
				 USB3PHY_PCS_LOCK_DETECT_CONFIG1 0xd1
				 USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x1f
				 USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x47
				 USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x75
				 USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x13
				 USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86
				 USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04
				 USB3PHY_PCS_TSYNC_RSYNC_TIME 0x44
				 USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7
				 USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
				 USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x40
				 USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x00
				 USB3PHY_PCS_RX_SIGDET_LVL 0x88>;

		qcom,qmp-phy-reg-offset =
				<0xd74 /* USB3_PHY_PCS_STATUS */
				 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
				 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
				 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
				 0xc00 /* USB3_PHY_SW_RESET */
				 0xc08 /* USB3_PHY_START */
				 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */

		clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
			<&rpmcc RPM_SMD_XO_CLK_SRC>,
			<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
			<&gcc GCC_AHB2PHY_USB_CLK>;

		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
				"ref_clk", "cfg_ahb_clk";

		resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
			<&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
		reset-names = "phy_reset", "phy_phy_reset";
	};

};