#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))

&msm_gpu {
	compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
	status = "ok";
	reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
		<0x3de0000 0x10000>, <0x3d8b000 0x2000>,
		<0x06900000 0x80000>;
	reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
			"isense_cntl", "qdss_gfx";
	interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "kgsl_3d0_irq";

	qcom,chipid = <0x06050000>;

	qcom,initial-pwrlevel = <2>;

	qcom,no-nap;

	qcom,min-access-length = <32>;

	qcom,ubwc-mode = <4>;

	qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */

	#cooling-cells = <2>;

	qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";

	clocks = <&gpucc GPU_CC_CXO_CLK>,
		<&gcc GCC_DDRSS_GPU_AXI_CLK>,
		<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
		<&gpucc GPU_CC_CX_GMU_CLK>,
		<&gpucc GPU_CC_AHB_CLK>,
		<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
		<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;

	clock-names = "rbbmtimer_clk",
			"mem_clk",
			"mem_iface_clk",
			"gmu_clk",
			"gpu_cc_ahb",
			"gcc_gpu_memnoc_gfx",
			"gcc_gpu_snoc_dvm_gfx";

	qcom,isense-clk-on-level = <1>;

	/* GDSC regulator names */
	regulator-names = "vddcx", "vdd";
	/* GDSC oxili regulators */
	vddcx-supply = <&gpu_cx_gdsc>;
	vdd-supply = <&gpu_gx_gdsc>;

	nvmem-cells = <&gpu_lm_efuse>, <&gpu_speed_bin>;
	nvmem-cell-names = "isense_slope", "speed_bin";

	interconnect-names = "gpu_icc_path";
	interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;

	/* bus table */
	qcom,bus-table-ddr =
		<MHZ_TO_KBPS(0, 4)>,    /* index=0  */
		<MHZ_TO_KBPS(200, 4)>,  /* index=1  */
		<MHZ_TO_KBPS(300, 4)>,  /* index=2  */
		<MHZ_TO_KBPS(451, 4)>,  /* index=3  */
		<MHZ_TO_KBPS(547, 4)>,  /* index=4  */
		<MHZ_TO_KBPS(681, 4)>,  /* index=5  */
		<MHZ_TO_KBPS(768, 4)>,  /* index=6  */
		<MHZ_TO_KBPS(1017, 4)>, /* index=7  */
		<MHZ_TO_KBPS(1555, 4)>, /* index=8  */
		<MHZ_TO_KBPS(1804, 4)>, /* index=9  */
		<MHZ_TO_KBPS(2092, 4)>, /* index=10 */
		<MHZ_TO_KBPS(2736, 4)>; /* index=11 */

	qcom,bus-table-cnoc =
		<0>,   /* Off */
		<100>; /* On */

	qcom,l3-pwrlevels {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,l3-pwrlevels";

		qcom,l3-pwrlevel@0 {
			reg = <0>;
			qcom,l3-freq = <0>;
		};

		qcom,l3-pwrlevel@1 {
			reg = <1>;
			qcom,l3-freq = <864000000>;
		};

		qcom,l3-pwrlevel@2 {
			reg = <2>;
			qcom,l3-freq = <1344000000>;
		};
	};

	/* ZAP Shader memory */
	zap-shader {
		memory-region = <&pil_gpu_mem>;
	};

	/* GPU Mempools */
	qcom,gpu-mempools {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,gpu-mempools";

		/* 4K Page Pool configuration */
		qcom,gpu-mempool@0 {
			reg = <0>;
			qcom,mempool-page-size = <4096>;
			qcom,mempool-reserved = <2048>;
			qcom,mempool-allocate;
		};
		/* 8K Page Pool configuration */
		qcom,gpu-mempool@1 {
			reg = <1>;
			qcom,mempool-page-size = <8192>;
			qcom,mempool-reserved = <1024>;
			qcom,mempool-allocate;
		};
		/* 64K Page Pool configuration */
		qcom,gpu-mempool@2 {
			reg = <2>;
			qcom,mempool-page-size = <65536>;
			qcom,mempool-reserved = <256>;
		};
		/* 1M Page Pool configuration */
		qcom,gpu-mempool@3 {
			reg = <3>;
			qcom,mempool-page-size = <1048576>;
			qcom,mempool-reserved = <32>;
		};
	};

	/* Power levels */
	qcom,gpu-pwrlevels {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,gpu-pwrlevels";

		qcom,gpu-pwrlevel@0 {
			reg = <0>;
			qcom,gpu-freq = <480000000>;
			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
			qcom,bus-freq = <11>;
			qcom,bus-min = <11>;
			qcom,bus-max = <11>;
		};

		qcom,gpu-pwrlevel@1 {
			reg = <1>;
			qcom,gpu-freq = <381000000>;
			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
			qcom,bus-freq = <8>;
			qcom,bus-min = <7>;
			qcom,bus-max = <11>;
		};

		qcom,gpu-pwrlevel@2 {
			reg = <2>;
			qcom,gpu-freq = <290000000>;
			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
			qcom,bus-freq = <2>;
			qcom,bus-min = <1>;
			qcom,bus-max = <8>;
		};

		qcom,gpu-pwrlevel@3 {
			reg = <3>;
			qcom,gpu-freq = <0>;
			qcom,bus-freq = <0>;
			qcom,bus-min = <0>;
			qcom,bus-max = <0>;
		};
	};
};

&soc {
	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x03da0000 0x10000>;

		vddcx-supply = <&gpu_cx_gdsc>;

		gfx3d_user: gfx3d_user {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 0x0 0x401>;
			qcom,iommu-dma = "disabled";
		};

		gfx3d_secure: gfx3d_secure {
			compatible = "qcom,smmu-kgsl-cb";
			iommus = <&kgsl_smmu 0x2 0x400>;
			qcom,iommu-dma = "disabled";
		};

	};

	gmu: qcom,gmu@3d6a000 {
		compatible = "qcom,gpu-gmu";

		reg = <0x3d6a000 0x30000>,
			<0xb290000 0x10000>,
			<0xb490000 0x10000>;
		reg-names = "kgsl_gmu_reg",
			"kgsl_gmu_pdc_cfg",
			"kgsl_gmu_pdc_seq";

		interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
						<0 305 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";

		iommus = <&kgsl_smmu 0x5 0x400>;
		qcom,iommu-dma = "disabled";

		regulator-names = "vddcx", "vdd";
		vddcx-supply = <&gpu_cx_gdsc>;
		vdd-supply = <&gpu_gx_gdsc>;

		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
				<&gpucc GPU_CC_CXO_CLK>,
				<&gcc GCC_DDRSS_GPU_AXI_CLK>,
				<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				<&gpucc GPU_CC_AHB_CLK>;

		clock-names = "gmu_clk", "cxo_clk", "axi_clk",
				"memnoc_clk", "gpu_cc_ahb";

		/* AOP mailbox for sending ACD enable and disable messages */
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";
	};
};