#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {
	kgsl_smmu: kgsl-smmu@2ca0000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x2ca0000 0x10000>,
			<0x2cc2000 0x20>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		qcom,disable-atos;
		#global-interrupts = <1>;
		qcom,regulator-names = "vdd";
		vdd-supply = <&gpu_cx_gdsc>;

		clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
			 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
			 <&gpucc GPU_CC_AHB_CLK>;
		clock-names = "gcc_gpu_memnoc_gfx_clk",
			      "gcc_gpu_snoc_dvm_gfx_clk",
			      "gpu_cc_ahb_clk";
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;
		interrupts =	<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;

		gfx_0_tbu: gfx_0_tbu@2cc5000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x2cc5000 0x1000>,
				<0x2cc2200 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x0 0x400>;
			qcom,iova-width = <49>;
		};

		gfx_1_tbu: gfx_1_tbu@2cc9000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x2cc9000 0x1000>,
				<0x2cc2208 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x400 0x400>;
			qcom,iova-width = <49>;
		};
	};

	apps_smmu: apps-smmu@15000000 {
		compatible = "qcom,qsmmu-v500";
		reg = <0x15000000 0x100000>,
			<0x15182000 0x20>;
		reg-names = "base", "tcu-base";
		#iommu-cells = <2>;
		qcom,skip-init;
		qcom,use-3-lvl-tables;
		qcom,disable-atos;
		qcom,min-iova-align;
		#global-interrupts = <1>;
		#size-cells = <1>;
		#address-cells = <1>;
		ranges;
		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;

		interconnects = <&system_noc MASTER_GEM_NOC_SNOC
				&config_noc SLAVE_IMEM_CFG>;
		qcom,active-only;

		anoc_1_tbu: anoc_1_tbu@15185000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15185000 0x1000>,
				<0x15182200 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x0 0x400>;
			qcom,regulator-names = "vdd";
			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu1_gdsc>;
			qcom,active-only;
			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
					&config_noc SLAVE_IMEM_CFG>;
			qcom,iova-width = <36>;
		};

		anoc_2_tbu: anoc_2_tbu@15189000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15189000 0x1000>,
				<0x15182208 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x400 0x400>;
			qcom,regulator-names = "vdd";
			vdd-supply = <&hlos1_vote_aggre_noc_mmu_tbu2_gdsc>;
			qcom,active-only;
			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
					&config_noc SLAVE_IMEM_CFG>;
			qcom,iova-width = <36>;

		};

		mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518D000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x1518d000 0x1000>,
				<0x15182210 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x800 0x400>;
			qcom,regulator-names = "vdd";
			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
			qcom,active-only;
			interconnects = <&mmss_noc MASTER_MDP0
					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
			qcom,iova-width = <32>;
		};

		mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15191000 0x1000>,
				<0x15182218 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0xc00 0x400>;
			qcom,regulator-names = "vdd";
			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
			qcom,active-only;
			interconnects = <&mmss_noc MASTER_MDP0
					 &mmss_noc SLAVE_MNOC_HF_MEM_NOC>;
			qcom,iova-width = <32>;
		};

		mnoc_sf_0_tbu: mnoc_sf_0_tbu@15195000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15195000 0x1000>,
				<0x15182220 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1000 0x400>;
			qcom,regulator-names = "vdd";
			vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
			qcom,active-only;
			interconnects = <&mmss_noc MASTER_CAMNOC_SF
					 &mmss_noc SLAVE_MNOC_SF_MEM_NOC>;
			qcom,iova-width = <32>;
		};

		compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x15199000 0x1000>,
				<0x15182228 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1400 0x400>;
			/* No GDSC */
			interconnects = <&compute_noc MASTER_NPU
					 &compute_noc SLAVE_CDSP_MEM_NOC>;
			qcom,iova-width = <32>;
		};

		adsp_tbu: adsp_tbu@1519D000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x1519d000 0x1000>,
				<0x15182230 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1800 0x400>;
			qcom,regulator-names = "vdd";
			vdd-supply = <&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc>;
			qcom,active-only;
			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
					&config_noc SLAVE_IMEM_CFG>;
			qcom,iova-width = <32>;
		};

		anoc_1_pcie_tbu: anoc_1_pcie_tbu@151A1000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151a1000 0x1000>,
				<0x15182238 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x1c00 0x400>;
			qcom,opt-out-tbu-halting;
			qcom,regulator-names = "vdd";
			vdd-supply = <&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc>;
			clock-names = "gcc_aggre_noc_pcie_tbu_clk";
			clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
			qcom,active-only;
			interconnects = <&system_noc MASTER_GEM_NOC_SNOC
					&config_noc SLAVE_IMEM_CFG>;
			qcom,iova-width = <36>;
		};

		compute_dsp_1_tbu: compute_dsp_1_tbu@151A5000 {
			compatible = "qcom,qsmmuv500-tbu";
			reg = <0x151a5000 0x1000>,
				<0x15182240 0x8>;
			reg-names = "base", "status-reg";
			qcom,stream-id-range = <0x2000 0x400>;
			/* No GDSC */
			qcom,active-only;
			interconnects = <&compute_noc MASTER_NPU
					 &compute_noc SLAVE_CDSP_MEM_NOC>;
			qcom,iova-width = <32>;
		};
	};

	dma_dev@0x0 {
		compatible = "qcom,iommu-dma";
		memory-region = <&system_cma>;
	};

	iommu_test_device {
		compatible = "qcom,iommu-debug-test";

		kgsl_iommu_test_device {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&kgsl_smmu 0x7 0>;
		};

		kgsl_iommu_coherent_test_device {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&kgsl_smmu 0x9 0>;
			dma-coherent;
		};

		apps_iommu_test_device {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x21 0>;
		};

		apps_iommu_coherent_test_device {
			compatible = "qcom,iommu-debug-usecase";
			iommus = <&apps_smmu 0x23 0>;
			dma-coherent;
		};
	};

};

&kgsl_smmu {
	qcom,actlr =
		/* All CBs of GFX: +15 deep PF */
		<0x0 0x407 0x303>;
};

&apps_smmu {
	qcom,actlr =
		/* SIDs 0x1460 - 0x1463 of NPU: +3 deep PF */
		<0x1460 0x3 0x103>,

		/* SIDs 0x1464 - 0x1465 of NPU: +3 deep PF */
		<0x1464 0x1 0x103>,

		/* SIDs 0x2060 - 0x2063 of NPU: +3 deep PF */
		<0x2060 0x3 0x103>,

		/* SIDs 0x2064 - 0x2065 of NPU: +3 deep PF */
		<0x2064 0x1 0x103>,

		/* Display SIDs: +3 deep PF */
		<0x0800 0x0420 0x103>,
		<0x0801 0x0420 0x103>,
		<0x1040 0x0001 0x103>,

		/* Video SIDs: +3 deep PF */
		<0x1300 0x0060 0x103>,
		<0x1301 0x0004 0x103>,
		<0x1303 0x0020 0x103>,
		<0x1304 0x0060 0x103>,
		<0x1342 0x0000 0x103>;
};