/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_MONACO_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_MONACO_H

/* GPU_CC clocks */
#define GPU_CC_PLL0			0
#define GPU_CC_AHB_CLK			1
#define GPU_CC_CRC_AHB_CLK		2
#define GPU_CC_CX_APB_CLK		3
#define GPU_CC_CX_GFX3D_CLK		4
#define GPU_CC_CX_GFX3D_SLV_CLK		5
#define GPU_CC_CX_GMU_CLK		6
#define GPU_CC_CX_SNOC_DVM_CLK		7
#define GPU_CC_CXO_AON_CLK		8
#define GPU_CC_CXO_AON_CLK_SRC		9
#define GPU_CC_CXO_CLK			10
#define GPU_CC_GMU_CLK_SRC		11
#define GPU_CC_GX_CXO_CLK		12
#define GPU_CC_GX_GFX3D_CLK		13
#define GPU_CC_GX_GFX3D_CLK_SRC		14
#define GPU_CC_SLEEP_CLK		15
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK	16

#endif