/* SPDX-License-Identifier: GPL-2.0-only */


#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMX75_H

#ifndef PMX75_SID
#define PMX75_SID       1
#endif


#define PMX75_ADC5_GEN3_OFFSET_REF		(PMX75_SID << 8 | 0x00)
#define PMX75_ADC5_GEN3_1P25VREF		(PMX75_SID << 8 | 0X01)
#define PMX75_ADC5_GEN3_VREF_VADC		(PMX75_SID << 8 | 0x02)
#define PMX75_ADC5_GEN3_DIE_TEMP		(PMX75_SID << 8 | 0x03)

#define PMX75_ADC5_GEN3_AMUX_THM1		(PMX75_SID << 8 | 0x04)
#define PMX75_ADC5_GEN3_AMUX_THM2		(PMX75_SID << 8 | 0x05)
#define PMX75_ADC5_GEN3_AMUX_THM3		(PMX75_SID << 8 | 0x06)
#define PMX75_ADC5_GEN3_AMUX_THM4		(PMX75_SID << 8 | 0x07)
#define PMX75_ADC5_GEN3_AMUX_THM5		(PMX75_SID << 8 | 0x08)
#define PMX75_ADC5_GEN3_AMUX_THM6		(PMX75_SID << 8 | 0x09)
#define PMX75_ADC5_GEN3_AMUX1_GPIO5		(PMX75_SID << 8 | 0x0a)
#define PMX75_ADC5_GEN3_AMUX2_GPIO12		(PMX75_SID << 8 | 0x0b)
#define PMX75_ADC5_GEN3_AMUX3_GPIO15		(PMX75_SID << 8 | 0x0c)
#define PMX75_ADC5_GEN3_AMUX4_GPIO1		(PMX75_SID << 8 | 0x0d)


#define PMX75_ADC5_GEN3_AMUX_THM1_100K_PU	(PMX75_SID << 8 | 0x44)
#define PMX75_ADC5_GEN3_AMUX_THM2_100K_PU	(PMX75_SID << 8 | 0x45)
#define PMX75_ADC5_GEN3_AMUX_THM3_100K_PU	(PMX75_SID << 8 | 0x46)
#define PMX75_ADC5_GEN3_AMUX_THM4_100K_PU	(PMX75_SID << 8 | 0x47)
#define PMX75_ADC5_GEN3_AMUX_THM5_100K_PU	(PMX75_SID << 8 | 0x48)
#define PMX75_ADC5_GEN3_AMUX_THM6_100K_PU	(PMX75_SID << 8 | 0x49)
#define PMX75_ADC5_GEN3_AMUX1_GPIO5_100K_PU	(PMX75_SID << 8 | 0x4a)
#define PMX75_ADC5_GEN3_AMUX2_GPIO12_100K_PU	(PMX75_SID << 8 | 0x4b)
#define PMX75_ADC5_GEN3_AMUX3_GPIO15_100K_PU	(PMX75_SID << 8 | 0x4c)
#define PMX75_ADC5_GEN3_AMUX4_GPIO1_100K_PU	(PMX75_SID << 8 | 0x4d)


#define PMX75_ADC5_GEN3_AMUX2_GPIO12_DIV3	(PMX75_SID << 8 | 0x8b)
#define PMX75_ADC5_GEN3_AMUX3_GPIO15_DIV3	(PMX75_SID << 8 | 0x8c)

#define PMX75_ADC5_GEN3_VPH_PWR		(PMX75_SID << 8 | 0x8e)

#endif 
