/* SPDX-License-Identifier: GPL-2.0-only */


#ifndef __DT_BINDINGS_QCOM_SPMI_VADC_PM7550BA_H
#define __DT_BINDINGS_QCOM_SPMI_VADC_PM7550BA_H

#ifndef PM7550BA_SID
#define PM7550BA_SID		7
#endif

#define PM7550BA_ADC5_GEN3_OFFSET_REF				(PM7550BA_SID << 8 | 0x00)
#define PM7550BA_ADC5_GEN3_1P25VREF				(PM7550BA_SID << 8 | 0x01)
#define PM7550BA_ADC5_GEN3_VREF_VADC				(PM7550BA_SID << 8 | 0x02)
#define PM7550BA_ADC5_GEN3_DIE_TEMP				(PM7550BA_SID << 8 | 0x03)

#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM		(PM7550BA_SID << 8 | 0x04)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID			(PM7550BA_SID << 8 | 0x05)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V		(PM7550BA_SID << 8 | 0x06)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM			(PM7550BA_SID << 8 | 0x07)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION			(PM7550BA_SID << 8 | 0x08)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6			(PM7550BA_SID << 8 | 0x09)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1				(PM7550BA_SID << 8 | 0x0a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2				(PM7550BA_SID << 8 | 0x0b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3				(PM7550BA_SID << 8 | 0x0c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4				(PM7550BA_SID << 8 | 0x0d)

#define PM7550BA_ADC5_GEN3_CHG_TEMP_V				(PM7550BA_SID << 8 | 0x10)
#define PM7550BA_ADC5_GEN3_USB_SNS_V_16			(PM7550BA_SID << 8 | 0x11)
#define PM7550BA_ADC5_GEN3_VIN_DIV16_MUX			(PM7550BA_SID << 8 | 0x12)
#define PM7550BA_ADC5_GEN3_USBC_MUX				(PM7550BA_SID << 8 | 0x13)
#define PM7550BA_ADC5_GEN3_VREF_BAT_THERM			(PM7550BA_SID << 8 | 0x15)
#define PM7550BA_ADC5_GEN3_IIN_FB				(PM7550BA_SID << 8 | 0x17)
#define PM7550BA_ADC5_GEN3_SMB_IIN				(PM7550BA_SID << 8 | 0x19)
#define PM7550BA_ADC5_GEN3_SMB_ICHG				(PM7550BA_SID << 8 | 0x1b)
#define PM7550BA_ADC5_GEN3_SMB_TEMP_I				(PM7550BA_SID << 8 | 0x1e)
#define PM7550BA_ADC5_GEN3_CHG_TEMP_I				(PM7550BA_SID << 8 | 0x1f)
#define PM7550BA_ADC5_GEN3_ICHG_FB				(PM7550BA_SID << 8 | 0xa1)


#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_30K_PU		(PM7550BA_SID << 8 | 0x24)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID_30K_PU		(PM7550BA_SID << 8 | 0x25)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_30K_PU		(PM7550BA_SID << 8 | 0x26)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_30K_PU		(PM7550BA_SID << 8 | 0x27)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION_30K_PU		(PM7550BA_SID << 8 | 0x28)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_30K_PU		(PM7550BA_SID << 8 | 0x29)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_30K_PU			(PM7550BA_SID << 8 | 0x2a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_30K_PU			(PM7550BA_SID << 8 | 0x2b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_30K_PU			(PM7550BA_SID << 8 | 0x2c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_30K_PU			(PM7550BA_SID << 8 | 0x2d)

#define PM7550BA_ADC5_GEN3_USBC_MUX_30K_PU			(PM7550BA_SID << 8 | 0x33)


#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_100K_PU	(PM7550BA_SID << 8 | 0x44)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID_100K_PU		(PM7550BA_SID << 8 | 0x45)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_THEMP_100K_PU		(PM7550BA_SID << 8 | 0x46)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_100K_PU		(PM7550BA_SID << 8 | 0x47)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION_100K_PU		(PM7550BA_SID << 8 | 0x48)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_100K_PU		(PM7550BA_SID << 8 | 0x49)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_100K_PU			(PM7550BA_SID << 8 | 0x4a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_100K_PU			(PM7550BA_SID << 8 | 0x4b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_100K_PU			(PM7550BA_SID << 8 | 0x4c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_100K_PU			(PM7550BA_SID << 8 | 0x4d)

#define PM7550_ADC5_GEN3_USBC_MUX_100K_PU			(PM7550BA_SID << 8 | 0x53)


#define PM7550BA_ADC5_GEN3_AMUX_THM1_BATT_THERM_400K_PU	(PM7550BA_SID << 8 | 0x64)
#define PM7550BA_ADC5_GEN3_AMUX_THM2_BATT_ID_400K_PU		(PM7550BA_SID << 8 | 0x65)
#define PM7550BA_ADC5_GEN3_AMUX_THM3_SMB_TEMP_V_400K_PU	(PM7550BA_SID << 8 | 0x66)
#define PM7550BA_ADC5_GEN3_AMUX_THM4_USB_THERM_400K_PU		(PM7550BA_SID << 8 | 0x67)
#define PM7550BA_ADC5_GEN3_AMUX_THM5_OPTION_400K_PU		(PM7550BA_SID << 8 | 0x68)
#define PM7550BA_ADC5_GEN3_AMUX_THM6_GPIO6_400K_PU		(PM7550BA_SID << 8 | 0x69)
#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_400K_PU			(PM7550BA_SID << 8 | 0x6a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_400K_PU			(PM7550BA_SID << 8 | 0x6b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_400K_PU			(PM7550BA_SID << 8 | 0x6c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_400K_PU			(PM7550BA_SID << 8 | 0x6d)

#define PM7550BA_ADC5_GEN3_USBC_MUX_400K_PU			(PM7550BA_SID << 8 | 0x73)


#define PM7550BA_ADC5_GEN3_AMUX1_GPIO1_DIV3			(PM7550BA_SID << 8 | 0x8a)
#define PM7550BA_ADC5_GEN3_AMUX2_GPIO2_DIV3			(PM7550BA_SID << 8 | 0x8b)
#define PM7550BA_ADC5_GEN3_AMUX3_GPIO3_DIV3			(PM7550BA_SID << 8 | 0x8c)
#define PM7550BA_ADC5_GEN3_AMUX4_GPIO4_DIV3			(PM7550BA_SID << 8 | 0x8d)

#define PM7550BA_ADC5_GEN3_VPH_PWR				(PM7550BA_SID << 8 | 0x8e)
#define PM7550BA_ADC5_GEN3_VBAT_SNS_QBG			(PM7550BA_SID << 8 | 0x8f)
#define PM7550BA_ADC5_GEN3_VBAT_SNS_CHGR			(PM7550BA_SID << 8 | 0x94)

#endif 
