# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SC7280 CAMSS ISP

maintainers:
  - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com>
  - Hariram Purushothaman <hariramp@quicinc.com>

description:
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.

properties:
  compatible:
    const: qcom,sc7280-camss

  reg:
    maxItems: 15

  reg-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid_lite0
      - const: csid_lite1
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: vfe0
      - const: vfe1
      - const: vfe2
      - const: vfe_lite0
      - const: vfe_lite1

  clocks:
    maxItems: 33

  clock-names:
    items:
      - const: camnoc_axi
      - const: cpas_ahb
      - const: csiphy0
      - const: csiphy0_timer
      - const: csiphy1
      - const: csiphy1_timer
      - const: csiphy2
      - const: csiphy2_timer
      - const: csiphy3
      - const: csiphy3_timer
      - const: csiphy4
      - const: csiphy4_timer
      - const: gcc_camera_ahb
      - const: gcc_cam_hf_axi
      - const: icp_ahb
      - const: vfe0
      - const: vfe0_axi
      - const: vfe0_cphy_rx
      - const: vfe0_csid
      - const: vfe1
      - const: vfe1_axi
      - const: vfe1_cphy_rx
      - const: vfe1_csid
      - const: vfe2
      - const: vfe2_axi
      - const: vfe2_cphy_rx
      - const: vfe2_csid
      - const: vfe_lite0
      - const: vfe_lite0_cphy_rx
      - const: vfe_lite0_csid
      - const: vfe_lite1
      - const: vfe_lite1_cphy_rx
      - const: vfe_lite1_csid

  interrupts:
    maxItems: 15

  interrupt-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid_lite0
      - const: csid_lite1
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: vfe0
      - const: vfe1
      - const: vfe2
      - const: vfe_lite0
      - const: vfe_lite1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: ahb
      - const: hf_0

  iommus:
    maxItems: 1

  power-domains:
    items:
      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.

  power-domain-names:
    items:
      - const: ife0
      - const: ife1
      - const: ife2
      - const: top

  vdda-phy-supply:
    description:
      Phandle to a regulator supply to PHY core block.

  vdda-pll-supply:
    description:
      Phandle to 1.8V regulator supply to PHY refclk pll block.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSIPHY 0.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSIPHY 1.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSIPHY 2.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@3:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSIPHY 3.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

      port@4:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSIPHY 4.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              data-lanes:
                minItems: 1
                maxItems: 4

            required:
              - data-lanes

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - interconnects
  - interconnect-names
  - iommus
  - power-domains
  - power-domain-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,camcc-sc7280.h>
    #include <dt-bindings/clock/qcom,gcc-sc7280.h>
    #include <dt-bindings/interconnect/qcom,sc7280.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        isp@acb3000 {
            compatible = "qcom,sc7280-camss";

            reg = <0x0 0x0acb3000 0x0 0x1000>,
                  <0x0 0x0acba000 0x0 0x1000>,
                  <0x0 0x0acc1000 0x0 0x1000>,
                  <0x0 0x0acc8000 0x0 0x1000>,
                  <0x0 0x0accf000 0x0 0x1000>,
                  <0x0 0x0ace0000 0x0 0x2000>,
                  <0x0 0x0ace2000 0x0 0x2000>,
                  <0x0 0x0ace4000 0x0 0x2000>,
                  <0x0 0x0ace6000 0x0 0x2000>,
                  <0x0 0x0ace8000 0x0 0x2000>,
                  <0x0 0x0acaf000 0x0 0x4000>,
                  <0x0 0x0acb6000 0x0 0x4000>,
                  <0x0 0x0acbd000 0x0 0x4000>,
                  <0x0 0x0acc4000 0x0 0x4000>,
                  <0x0 0x0accb000 0x0 0x4000>;
            reg-names = "csid0",
                        "csid1",
                        "csid2",
                        "csid_lite0",
                        "csid_lite1",
                        "csiphy0",
                        "csiphy1",
                        "csiphy2",
                        "csiphy3",
                        "csiphy4",
                        "vfe0",
                        "vfe1",
                        "vfe2",
                        "vfe_lite0",
                        "vfe_lite1";

            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
                     <&camcc CAM_CC_CPAS_AHB_CLK>,
                     <&camcc CAM_CC_CSIPHY0_CLK>,
                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY1_CLK>,
                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY2_CLK>,
                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY3_CLK>,
                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY4_CLK>,
                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
                     <&gcc GCC_CAMERA_AHB_CLK>,
                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
                     <&camcc CAM_CC_ICP_AHB_CLK>,
                     <&camcc CAM_CC_IFE_0_CLK>,
                     <&camcc CAM_CC_IFE_0_AXI_CLK>,
                     <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_0_CSID_CLK>,
                     <&camcc CAM_CC_IFE_1_CLK>,
                     <&camcc CAM_CC_IFE_1_AXI_CLK>,
                     <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_1_CSID_CLK>,
                     <&camcc CAM_CC_IFE_2_CLK>,
                     <&camcc CAM_CC_IFE_2_AXI_CLK>,
                     <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_2_CSID_CLK>,
                     <&camcc CAM_CC_IFE_LITE_0_CLK>,
                     <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
                     <&camcc CAM_CC_IFE_LITE_1_CLK>,
                     <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
            clock-names = "camnoc_axi",
                          "cpas_ahb",
                          "csiphy0",
                          "csiphy0_timer",
                          "csiphy1",
                          "csiphy1_timer",
                          "csiphy2",
                          "csiphy2_timer",
                          "csiphy3",
                          "csiphy3_timer",
                          "csiphy4",
                          "csiphy4_timer",
                          "gcc_camera_ahb",
                          "gcc_cam_hf_axi",
                          "icp_ahb",
                          "vfe0",
                          "vfe0_axi",
                          "vfe0_cphy_rx",
                          "vfe0_csid",
                          "vfe1",
                          "vfe1_axi",
                          "vfe1_cphy_rx",
                          "vfe1_csid",
                          "vfe2",
                          "vfe2_axi",
                          "vfe2_cphy_rx",
                          "vfe2_csid",
                          "vfe_lite0",
                          "vfe_lite0_cphy_rx",
                          "vfe_lite0_csid",
                          "vfe_lite1",
                          "vfe_lite1_cphy_rx",
                          "vfe_lite1_csid";

            interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
            interrupt-names = "csid0",
                              "csid1",
                              "csid2",
                              "csid_lite0",
                              "csid_lite1",
                              "csiphy0",
                              "csiphy1",
                              "csiphy2",
                              "csiphy3",
                              "csiphy4",
                              "vfe0",
                              "vfe1",
                              "vfe2",
                              "vfe_lite0",
                              "vfe_lite1";

            interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
                             &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
                            <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
            interconnect-names = "ahb",
                                 "hf_0";

            iommus = <&apps_smmu 0x800 0x4e0>;

            power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
                            <&camcc CAM_CC_IFE_1_GDSC>,
                            <&camcc CAM_CC_IFE_2_GDSC>,
                            <&camcc CAM_CC_TITAN_TOP_GDSC>;
            power-domain-names = "ife0",
                                 "ife1",
                                 "ife2",
                                 "top";

            vdda-phy-supply = <&vreg_l10c_0p88>;
            vdda-pll-supply = <&vreg_l6b_1p2>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;
            };
        };
    };
