# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM8550 Camera Subsystem (CAMSS)

maintainers:
  - Depeng Shao <quic_depengs@quicinc.com>

description:
  The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.

properties:
  compatible:
    const: qcom,sm8550-camss
    const: qcom,sm8550-camss-gen2

  reg:
    maxItems: 19

  reg-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid_lite0
      - const: csid_lite1
      - const: csid_wrapper
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: csiphy5
      - const: csiphy6
      - const: csiphy7
      - const: vfe0
      - const: vfe1
      - const: vfe2
      - const: vfe_lite0
      - const: vfe_lite1

  clocks:
    maxItems: 36

  clock-names:
    items:
      - const: camnoc_axi
      - const: cpas_ahb
      - const: cpas_fast_ahb_clk
      - const: cpas_ife_lite
      - const: cpas_vfe0
      - const: cpas_vfe1
      - const: cpas_vfe2
      - const: csid
      - const: csiphy0
      - const: csiphy0_timer
      - const: csiphy1
      - const: csiphy1_timer
      - const: csiphy2
      - const: csiphy2_timer
      - const: csiphy3
      - const: csiphy3_timer
      - const: csiphy4
      - const: csiphy4_timer
      - const: csiphy5
      - const: csiphy5_timer
      - const: csiphy6
      - const: csiphy6_timer
      - const: csiphy7
      - const: csiphy7_timer
      - const: csiphy_rx
      - const: gcc_axi_hf
      - const: vfe0
      - const: vfe0_fast_ahb
      - const: vfe1
      - const: vfe1_fast_ahb
      - const: vfe2
      - const: vfe2_fast_ahb
      - const: vfe_lite
      - const: vfe_lite_ahb
      - const: vfe_lite_cphy_rx
      - const: vfe_lite_csid

  interrupts:
    maxItems: 18

  interrupt-names:
    items:
      - const: csid0
      - const: csid1
      - const: csid2
      - const: csid_lite0
      - const: csid_lite1
      - const: csiphy0
      - const: csiphy1
      - const: csiphy2
      - const: csiphy3
      - const: csiphy4
      - const: csiphy5
      - const: csiphy6
      - const: csiphy7
      - const: vfe0
      - const: vfe1
      - const: vfe2
      - const: vfe_lite0
      - const: vfe_lite1

  interconnects:
    maxItems: 2

  interconnect-names:
    items:
      - const: ahb
      - const: hf_0_mnoc

  iommus:
    maxItems: 1

  power-domains:
    items:
      - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
      - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.

  power-domain-names:
    items:
      - const: ife0
      - const: ife1
      - const: ife2
      - const: top

  vdda-phy-supply:
    description:
      Phandle to a regulator supply to PHY core block.

  vdda-pll-supply:
    description:
      Phandle to 1.2V regulator supply to PHY refclk pll block.

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    description:
      CSI input ports.

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI0.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

      port@1:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI1.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

      port@2:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI2.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

      port@3:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI3.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

      port@4:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI4.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

      port@5:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI5.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

      port@6:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI6.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

      port@7:
        $ref: /schemas/graph.yaml#/$defs/port-base
        unevaluatedProperties: false
        description:
          Input port for receiving CSI data on CSI7.

        properties:
          endpoint:
            $ref: video-interfaces.yaml#
            unevaluatedProperties: false

            properties:
              clock-lanes:
                maxItems: 1

              data-lanes:
                minItems: 1
                maxItems: 4

              bus-type:
                enum:
                  - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
                  - 4 # MEDIA_BUS_TYPE_CSI2_DPHY

            required:
              - clock-lanes
              - data-lanes

required:
  - compatible
  - reg
  - reg-names
  - clocks
  - clock-names
  - interrupts
  - interrupt-names
  - interconnects
  - interconnect-names
  - iommus
  - power-domains
  - power-domain-names
  - vdda-phy-supply
  - vdda-pll-supply

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,sm8550-camcc.h>
    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
    #include <dt-bindings/interconnect/qcom,icc.h>
    #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        isp@acb7000 {
            compatible = "qcom,sm8550-camss";

            reg = <0 0x0acb7000 0 0xd00>,
                  <0 0x0acb9000 0 0xd00>,
                  <0 0x0acbb000 0 0xd00>,
                  <0 0x0acca000 0 0xa00>,
                  <0 0x0acce000 0 0xa00>,
                  <0 0x0acb6000 0 0x1000>,
                  <0 0x0ace4000 0 0x2000>,
                  <0 0x0ace6000 0 0x2000>,
                  <0 0x0ace8000 0 0x2000>,
                  <0 0x0acea000 0 0x2000>,
                  <0 0x0acec000 0 0x2000>,
                  <0 0x0acee000 0 0x2000>,
                  <0 0x0acf0000 0 0x2000>,
                  <0 0x0acf2000 0 0x2000>,
                  <0 0x0ac62000 0 0xf000>,
                  <0 0x0ac71000 0 0xf000>,
                  <0 0x0ac80000 0 0xf000>,
                  <0 0x0accb000 0 0x1800>,
                  <0 0x0accf000 0 0x1800>;
            reg-names = "csid0",
                        "csid1",
                        "csid2",
                        "csid_lite0",
                        "csid_lite1",
                        "csid_wrapper",
                        "csiphy0",
                        "csiphy1",
                        "csiphy2",
                        "csiphy3",
                        "csiphy4",
                        "csiphy5",
                        "csiphy6",
                        "csiphy7",
                        "vfe0",
                        "vfe1",
                        "vfe2",
                        "vfe_lite0",
                        "vfe_lite1";

            clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
                     <&camcc CAM_CC_CPAS_AHB_CLK>,
                     <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_0_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_1_CLK>,
                     <&camcc CAM_CC_CPAS_IFE_2_CLK>,
                     <&camcc CAM_CC_CSID_CLK>,
                     <&camcc CAM_CC_CSIPHY0_CLK>,
                     <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY1_CLK>,
                     <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY2_CLK>,
                     <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY3_CLK>,
                     <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY4_CLK>,
                     <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY5_CLK>,
                     <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY6_CLK>,
                     <&camcc CAM_CC_CSI6PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSIPHY7_CLK>,
                     <&camcc CAM_CC_CSI7PHYTIMER_CLK>,
                     <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
                     <&gcc GCC_CAMERA_HF_AXI_CLK>,
                     <&camcc CAM_CC_IFE_0_CLK>,
                     <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
                     <&camcc CAM_CC_IFE_1_CLK>,
                     <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
                     <&camcc CAM_CC_IFE_2_CLK>,
                     <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CLK>,
                     <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
                     <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
            clock-names = "camnoc_axi",
                          "cpas_ahb",
                          "cpas_fast_ahb_clk",
                          "cpas_ife_lite",
                          "cpas_vfe0",
                          "cpas_vfe1",
                          "cpas_vfe2",
                          "csid",
                          "csiphy0",
                          "csiphy0_timer",
                          "csiphy1",
                          "csiphy1_timer",
                          "csiphy2",
                          "csiphy2_timer",
                          "csiphy3",
                          "csiphy3_timer",
                          "csiphy4",
                          "csiphy4_timer",
                          "csiphy5",
                          "csiphy5_timer",
                          "csiphy6",
                          "csiphy6_timer",
                          "csiphy7",
                          "csiphy7_timer",
                          "csiphy_rx",
                          "gcc_axi_hf",
                          "vfe0",
                          "vfe0_fast_ahb",
                          "vfe1",
                          "vfe1_fast_ahb",
                          "vfe2",
                          "vfe2_fast_ahb",
                          "vfe_lite",
                          "vfe_lite_ahb",
                          "vfe_lite_cphy_rx",
                          "vfe_lite_csid";

            interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
                         <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
            interrupt-names = "csid0",
                              "csid1",
                              "csid2",
                              "csid_lite0",
                              "csid_lite1",
                              "csiphy0",
                              "csiphy1",
                              "csiphy2",
                              "csiphy3",
                              "csiphy4",
                              "csiphy5",
                              "csiphy6",
                              "csiphy7",
                              "vfe0",
                              "vfe1",
                              "vfe2",
                              "vfe_lite0",
                              "vfe_lite1";

            interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
                             &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
                            <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
            interconnect-names = "ahb",
                                 "hf_0_mnoc";

            iommus = <&apps_smmu 0x800 0x20>;

            power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
                            <&camcc CAM_CC_IFE_1_GDSC>,
                            <&camcc CAM_CC_IFE_2_GDSC>,
                            <&camcc CAM_CC_TITAN_TOP_GDSC>;
            power-domain-names = "ife0",
                                 "ife1",
                                 "ife2",
                                 "top";

            vdda-phy-supply = <&vreg_l1e_0p88>;
            vdda-pll-supply = <&vreg_l3e_1p2>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    #address-cells = <1>;
                    #size-cells = <0>;

                    csiphy_ep0: endpoint@0 {
                        reg = <0>;
                        clock-lanes = <7>;
                        data-lanes = <0 1>;
                        remote-endpoint = <&sensor_ep>;
                    };
                };
            };
        };
    };
