// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include #include #include #include #include #include #include #include #include #include "clk-alpha-pll.h" #include "clk-branch.h" #include "clk-pll.h" #include "clk-pm.h" #include "clk-rcg.h" #include "clk-regmap.h" #include "clk-regmap-divider.h" #include "clk-regmap-mux.h" #include "common.h" #include "reset.h" #include "vdd-level.h" static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NOMINAL + 1, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mxa, VDD_LOW + 1, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mxc, VDD_NOMINAL + 1, 1, vdd_corner); static struct clk_vdd_class *cam_cc_kalama_regulators[] = { &vdd_mm, &vdd_mxa, &vdd_mxc, }; static struct clk_vdd_class *cam_cc_kalama_regulators_1[] = { &vdd_mm, &vdd_mxc, }; enum { P_BI_TCXO, P_CAM_CC_PLL0_OUT_EVEN, P_CAM_CC_PLL0_OUT_MAIN, P_CAM_CC_PLL0_OUT_ODD, P_CAM_CC_PLL10_OUT_EVEN, P_CAM_CC_PLL11_OUT_EVEN, P_CAM_CC_PLL12_OUT_EVEN, P_CAM_CC_PLL1_OUT_EVEN, P_CAM_CC_PLL2_OUT_EVEN, P_CAM_CC_PLL2_OUT_MAIN, P_CAM_CC_PLL3_OUT_EVEN, P_CAM_CC_PLL4_OUT_EVEN, P_CAM_CC_PLL5_OUT_EVEN, P_CAM_CC_PLL6_OUT_EVEN, P_CAM_CC_PLL7_OUT_EVEN, P_CAM_CC_PLL8_OUT_EVEN, P_CAM_CC_PLL9_OUT_EVEN, P_CAM_CC_PLL9_OUT_ODD, P_SLEEP_CLK, }; static struct pll_vco lucid_ole_vco[] = { { 249600000, 2000000000, 0 }, }; static struct pll_vco rivian_ole_vco[] = { { 777000000, 1285000000, 0 }, }; static struct alpha_pll_config cam_cc_pll0_config = { .l = 0x3E, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8000, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00008400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll0 = { .offset = 0x0, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll0_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { .offset = 0x0, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll0_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { { 0x2, 3 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { .offset = 0x0, .post_div_shift = 14, .post_div_table = post_div_table_cam_cc_pll0_out_odd, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll0_out_odd", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll0.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll1_config = { .l = 0x2F, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x6555, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll1 = { .offset = 0x1000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll1_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { .offset = 0x1000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll1_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll1_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll1.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll10_config = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll10 = { .offset = 0xa000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll10_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll10", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = { .offset = 0xa000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll10_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll10_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll10.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll11_config = { .l = 0x2C, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x4555, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct alpha_pll_config cam_cc_pll11_config_kalama_v2 = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll11 = { .offset = 0xb000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll11_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll11", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll11_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll11_out_even = { .offset = 0xb000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll11_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll11_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll11_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll11.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll12_config = { .l = 0x2C, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x4555, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct alpha_pll_config cam_cc_pll12_config_kalama_v2 = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll12 = { .offset = 0xc000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll12_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll12", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll12_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll12_out_even = { .offset = 0xc000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll12_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll12_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll12_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll12.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll2_config = { .l = 0x32, .cal_l = 0x32, .alpha = 0x0, .config_ctl_val = 0x10000030, .config_ctl_hi_val = 0x80890263, .config_ctl_hi1_val = 0x00000217, .user_ctl_val = 0x00000000, .user_ctl_hi_val = 0x00100000, }; static struct clk_alpha_pll cam_cc_pll2 = { .offset = 0x2000, .vco_table = rivian_ole_vco, .num_vco = ARRAY_SIZE(rivian_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_OLE], .config = &cam_cc_pll2_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll2", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_rivian_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOW] = 1285000000}, }, }, }; static struct alpha_pll_config cam_cc_pll3_config = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll3 = { .offset = 0x3000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll3_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll3", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { .offset = 0x3000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll3_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll3_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll3.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll4_config = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll4 = { .offset = 0x4000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll4_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll4", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { .offset = 0x4000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll4_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll4_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll4.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll5_config = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll5 = { .offset = 0x5000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll5_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll5", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { .offset = 0x5000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll5_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll5_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll5.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll6_config = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll6 = { .offset = 0x6000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll6_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll6", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { .offset = 0x6000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll6_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll6_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll6.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll7_config = { .l = 0x30, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x8AAA, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll7 = { .offset = 0x7000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll7_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll7", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { .offset = 0x7000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll7_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll7_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll7.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll8_config = { .l = 0x14, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0xD555, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll8 = { .offset = 0x8000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll8_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll8", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { .offset = 0x8000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll8_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll8_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll8.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static struct alpha_pll_config cam_cc_pll9_config = { .l = 0x32, .cal_l = 0x44, .cal_l_ringosc = 0x44, .alpha = 0x0, .config_ctl_val = 0x20485699, .config_ctl_hi_val = 0x00182261, .config_ctl_hi1_val = 0x82AA299C, .test_ctl_val = 0x00000000, .test_ctl_hi_val = 0x00000003, .test_ctl_hi1_val = 0x00009000, .test_ctl_hi2_val = 0x00000034, .user_ctl_val = 0x00000400, .user_ctl_hi_val = 0x00000005, }; static struct clk_alpha_pll cam_cc_pll9 = { .offset = 0x9000, .vco_table = lucid_ole_vco, .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .config = &cam_cc_pll9_config, .clkr = { .hw.init = &(struct clk_init_data){ .name = "cam_cc_pll9", .parent_data = &(const struct clk_parent_data){ .fw_name = "bi_tcxo", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_ole_ops, }, .vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER_D1] = 615000000, [VDD_LOW] = 1100000000, [VDD_LOW_L1] = 1600000000, [VDD_NOMINAL] = 2000000000}, }, }, }; static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = { { 0x1, 2 }, { } }; static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = { .offset = 0x9000, .post_div_shift = 10, .post_div_table = post_div_table_cam_cc_pll9_out_even, .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even), .width = 4, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_pll9_out_even", .parent_hws = (const struct clk_hw*[]){ &cam_cc_pll9.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, }, }; static const struct parent_map cam_cc_parent_map_0[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL0_OUT_MAIN, 1 }, { P_CAM_CC_PLL0_OUT_EVEN, 2 }, { P_CAM_CC_PLL0_OUT_ODD, 3 }, { P_CAM_CC_PLL9_OUT_ODD, 4 }, { P_CAM_CC_PLL9_OUT_EVEN, 5 }, }; static const struct clk_parent_data cam_cc_parent_data_0[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll0.clkr.hw }, { .hw = &cam_cc_pll0_out_even.clkr.hw }, { .hw = &cam_cc_pll0_out_odd.clkr.hw }, { .hw = &cam_cc_pll9.clkr.hw }, { .hw = &cam_cc_pll9_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_1[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_EVEN, 3 }, { P_CAM_CC_PLL2_OUT_MAIN, 5 }, }; static const struct clk_parent_data cam_cc_parent_data_1[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll2.clkr.hw }, { .hw = &cam_cc_pll2.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL8_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_2[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll8_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_3[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL3_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_3[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll3_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL10_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll10_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_5[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL4_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_5[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll4_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_6[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL11_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_6[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll11_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_7[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL5_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_7[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll5_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_8[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL12_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_8[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll12_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_9[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL1_OUT_EVEN, 4 }, }; static const struct clk_parent_data cam_cc_parent_data_9[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll1_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_10[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL6_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_10[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll6_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_11[] = { { P_BI_TCXO, 0 }, { P_CAM_CC_PLL7_OUT_EVEN, 6 }, }; static const struct clk_parent_data cam_cc_parent_data_11[] = { { .fw_name = "bi_tcxo" }, { .hw = &cam_cc_pll7_out_even.clkr.hw }, }; static const struct parent_map cam_cc_parent_map_12[] = { { P_SLEEP_CLK, 0 }, }; static const struct clk_parent_data cam_cc_parent_data_12[] = { { .fw_name = "sleep_clk" }, }; static const struct parent_map cam_cc_parent_map_13[] = { { P_BI_TCXO, 0 }, }; static const struct clk_parent_data cam_cc_parent_data_13_ao[] = { { .fw_name = "bi_tcxo_ao" }, }; static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_bps_clk_src = { .cmd_rcgr = 0x10278, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_bps_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk_src", .parent_data = cam_cc_parent_data_2, .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 400000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { .cmd_rcgr = 0x13de0, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_camnoc_axi_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_LOW] = 400000000}, }, }; static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), { } }; static struct clk_rcg2 cam_cc_cci_0_clk_src = { .cmd_rcgr = 0x13900, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 37500000}, }, }; static struct clk_rcg2 cam_cc_cci_1_clk_src = { .cmd_rcgr = 0x13a30, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 37500000}, }, }; static struct clk_rcg2 cam_cc_cci_2_clk_src = { .cmd_rcgr = 0x13b60, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_2_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 37500000}, }, }; static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), { } }; static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .cmd_rcgr = 0x11290, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000, [VDD_LOW] = 480000000}, }, }; static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_cre_clk_src = { .cmd_rcgr = 0x1353c, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cre_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cre_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 400000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), { } }; static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .cmd_rcgr = 0x15980, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .cmd_rcgr = 0x15ab8, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .cmd_rcgr = 0x15bec, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .cmd_rcgr = 0x15d20, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static const struct freq_tbl ftbl_cam_cc_csi4phytimer_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { .cmd_rcgr = 0x15e54, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi4phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi4phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = { .cmd_rcgr = 0x15f88, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi5phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = { .cmd_rcgr = 0x160bc, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi6phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = { .cmd_rcgr = 0x161f0, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi7phytimer_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxc, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000}, }, }; static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), { } }; static struct clk_rcg2 cam_cc_csid_clk_src = { .cmd_rcgr = 0x13ca8, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csid_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csid_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000, [VDD_LOW] = 480000000}, }, }; static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), { } }; static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .cmd_rcgr = 0x10018, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 300000000, [VDD_NOMINAL] = 400000000}, }, }; static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), { } }; static struct clk_rcg2 cam_cc_icp_clk_src = { .cmd_rcgr = 0x137c4, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_icp_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000, [VDD_LOW] = 480000000, [VDD_LOW_L1] = 600000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_0_clk_src = { .cmd_rcgr = 0x11018, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_3, .freq_tbl = ftbl_cam_cc_ife_0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk_src", .parent_data = cam_cc_parent_data_3, .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 466000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_0_dsp_clk_src[] = { F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_0_dsp_clk_src = { .cmd_rcgr = 0x11154, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_4, .freq_tbl = ftbl_cam_cc_ife_0_dsp_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk_src", .parent_data = cam_cc_parent_data_4, .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 466000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_1_clk_src = { .cmd_rcgr = 0x12018, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_5, .freq_tbl = ftbl_cam_cc_ife_1_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk_src", .parent_data = cam_cc_parent_data_5, .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 466000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_1_dsp_clk_src[] = { F(425000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), { } }; static const struct freq_tbl ftbl_cam_cc_ife_1_dsp_clk_src_kalama_v2[] = { F(466000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_1_dsp_clk_src = { .cmd_rcgr = 0x12154, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_6, .freq_tbl = ftbl_cam_cc_ife_1_dsp_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk_src", .parent_data = cam_cc_parent_data_6, .num_parents = ARRAY_SIZE(cam_cc_parent_data_6), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 425000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = { F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_2_clk_src = { .cmd_rcgr = 0x122a8, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_7, .freq_tbl = ftbl_cam_cc_ife_2_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_clk_src", .parent_data = cam_cc_parent_data_7, .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 466000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ife_2_dsp_clk_src[] = { F(425000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), { } }; static const struct freq_tbl ftbl_cam_cc_ife_2_dsp_clk_src_kalama_v2[] = { F(466000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ife_2_dsp_clk_src = { .cmd_rcgr = 0x123e4, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_8, .freq_tbl = ftbl_cam_cc_ife_2_dsp_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_dsp_clk_src", .parent_data = cam_cc_parent_data_8, .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 425000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .cmd_rcgr = 0x13000, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csid_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000, [VDD_LOW] = 480000000}, }, }; static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .cmd_rcgr = 0x1313c, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csid_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 400000000, [VDD_LOW] = 480000000}, }, }; static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = { F(455000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_ipe_nps_clk_src = { .cmd_rcgr = 0x103cc, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_9, .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_nps_clk_src", .parent_data = cam_cc_parent_data_9, .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 455000000, [VDD_LOW] = 575000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 825000000}, }, }; static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0), F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_jpeg_clk_src = { .cmd_rcgr = 0x13674, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_jpeg_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 200000000, [VDD_LOW] = 400000000, [VDD_LOW_L1] = 480000000, [VDD_NOMINAL] = 600000000}, }, }; static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0), { } }; static struct clk_rcg2 cam_cc_mclk0_clk_src = { .cmd_rcgr = 0x15000, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static struct clk_rcg2 cam_cc_mclk1_clk_src = { .cmd_rcgr = 0x15130, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static struct clk_rcg2 cam_cc_mclk2_clk_src = { .cmd_rcgr = 0x15260, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static struct clk_rcg2 cam_cc_mclk3_clk_src = { .cmd_rcgr = 0x15390, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static struct clk_rcg2 cam_cc_mclk4_clk_src = { .cmd_rcgr = 0x154c0, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static struct clk_rcg2 cam_cc_mclk5_clk_src = { .cmd_rcgr = 0x155f0, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk5_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static struct clk_rcg2 cam_cc_mclk6_clk_src = { .cmd_rcgr = 0x15720, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk6_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static struct clk_rcg2 cam_cc_mclk7_clk_src = { .cmd_rcgr = 0x15850, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk7_clk_src", .parent_data = cam_cc_parent_data_1, .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mxa, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 68571429}, }, }; static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), { } }; static struct clk_rcg2 cam_cc_qdss_debug_clk_src = { .cmd_rcgr = 0x13f24, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_qdss_debug_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 75000000, [VDD_LOW] = 150000000, [VDD_LOW_L1] = 300000000}, }, }; static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = { F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_sfe_0_clk_src = { .cmd_rcgr = 0x13294, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_10, .freq_tbl = ftbl_cam_cc_sfe_0_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_sfe_0_clk_src", .parent_data = cam_cc_parent_data_10, .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 466000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = { F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_sfe_1_clk_src = { .cmd_rcgr = 0x133f4, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_11, .freq_tbl = ftbl_cam_cc_sfe_1_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_sfe_1_clk_src", .parent_data = cam_cc_parent_data_11, .num_parents = ARRAY_SIZE(cam_cc_parent_data_11), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 466000000, [VDD_LOW] = 594000000, [VDD_LOW_L1] = 675000000, [VDD_NOMINAL] = 785000000}, }, }; static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { F(32000, P_SLEEP_CLK, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_sleep_clk_src = { .cmd_rcgr = 0x141a0, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_12, .freq_tbl = ftbl_cam_cc_sleep_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_sleep_clk_src", .parent_data = cam_cc_parent_data_12, .num_parents = ARRAY_SIZE(cam_cc_parent_data_12), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_mm, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 32000}, }, }; static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), { } }; static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .cmd_rcgr = 0x10148, .mnd_width = 8, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", .parent_data = cam_cc_parent_data_0, .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, .clkr.vdd_data = { .vdd_classes = cam_cc_kalama_regulators_1, .num_vdd_classes = ARRAY_SIZE(cam_cc_kalama_regulators_1), .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_LOWER] = 80000000}, }, }; static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } }; static struct clk_rcg2 cam_cc_xo_clk_src = { .cmd_rcgr = 0x14070, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_13, .freq_tbl = ftbl_cam_cc_xo_clk_src, .enable_safe_config = true, .flags = HW_CLK_CTRL_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_xo_clk_src", .parent_data = cam_cc_parent_data_13_ao, .num_parents = ARRAY_SIZE(cam_cc_parent_data_13_ao), .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, }, }; static struct clk_branch cam_cc_bps_ahb_clk = { .halt_reg = 0x10274, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10274, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_bps_clk = { .halt_reg = 0x103a4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x103a4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_bps_fast_ahb_clk = { .halt_reg = 0x10144, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10144, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_bps_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_camnoc_axi_clk = { .halt_reg = 0x13f0c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13f0c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_camnoc_axi_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_camnoc_axi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_camnoc_dcd_xo_clk = { .halt_reg = 0x13f18, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13f18, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_camnoc_dcd_xo_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_camnoc_xo_clk = { .halt_reg = 0x13f1c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13f1c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_camnoc_xo_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cci_0_clk = { .halt_reg = 0x13a2c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13a2c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cci_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cci_1_clk = { .halt_reg = 0x13b5c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13b5c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cci_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cci_2_clk = { .halt_reg = 0x13c8c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13c8c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_2_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cci_2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_core_ahb_clk = { .halt_reg = 0x1406c, .halt_check = BRANCH_HALT_DELAY, .clkr = { .enable_reg = 0x1406c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_core_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_ahb_clk = { .halt_reg = 0x13c90, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13c90, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_bps_clk = { .halt_reg = 0x103b0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x103b0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_bps_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_bps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_cre_clk = { .halt_reg = 0x1366c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1366c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_cre_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cre_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_fast_ahb_clk = { .halt_reg = 0x13c9c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13c9c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_ife_0_clk = { .halt_reg = 0x11150, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x11150, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ife_0_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_ife_1_clk = { .halt_reg = 0x12150, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x12150, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ife_1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_ife_2_clk = { .halt_reg = 0x123e0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x123e0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ife_2_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_ife_lite_clk = { .halt_reg = 0x13138, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13138, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ife_lite_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_ipe_nps_clk = { .halt_reg = 0x10504, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10504, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_ipe_nps_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ipe_nps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_sbi_clk = { .halt_reg = 0x1054c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1054c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_sbi_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_sfe_0_clk = { .halt_reg = 0x133cc, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x133cc, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_sfe_0_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_sfe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cpas_sfe_1_clk = { .halt_reg = 0x1352c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1352c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cpas_sfe_1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_sfe_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cre_ahb_clk = { .halt_reg = 0x13670, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13670, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cre_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_cre_clk = { .halt_reg = 0x13668, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13668, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_cre_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cre_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi0phytimer_clk = { .halt_reg = 0x15aac, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15aac, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi0phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi1phytimer_clk = { .halt_reg = 0x15be4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15be4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi1phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi2phytimer_clk = { .halt_reg = 0x15d18, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15d18, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi2phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi3phytimer_clk = { .halt_reg = 0x15e4c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15e4c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi3phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi4phytimer_clk = { .halt_reg = 0x15f80, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15f80, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi4phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi4phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi5phytimer_clk = { .halt_reg = 0x160b4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x160b4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi5phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi5phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi6phytimer_clk = { .halt_reg = 0x161e8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x161e8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi6phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi6phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csi7phytimer_clk = { .halt_reg = 0x1631c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1631c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csi7phytimer_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csi7phytimer_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csid_clk = { .halt_reg = 0x13dd4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13dd4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csid_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csid_csiphy_rx_clk = { .halt_reg = 0x15ab4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15ab4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csid_csiphy_rx_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy0_clk = { .halt_reg = 0x15ab0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15ab0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy0_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy1_clk = { .halt_reg = 0x15be8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15be8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy2_clk = { .halt_reg = 0x15d1c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15d1c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy2_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy3_clk = { .halt_reg = 0x15e50, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15e50, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy3_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy4_clk = { .halt_reg = 0x15f84, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x15f84, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy4_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy5_clk = { .halt_reg = 0x160b8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x160b8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy5_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy6_clk = { .halt_reg = 0x161ec, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x161ec, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy6_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_csiphy7_clk = { .halt_reg = 0x16320, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x16320, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_csiphy7_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_drv_ahb_clk = { .halt_reg = 0x142d8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x142d8, .enable_mask = BIT(0), .flags = QCOM_CLK_BOOT_CRITICAL, .hw.init = &(struct clk_init_data){ .name = "cam_cc_drv_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_drv_xo_clk = { .halt_reg = 0x142d4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x142d4, .enable_mask = BIT(0), .flags = QCOM_CLK_BOOT_CRITICAL, .hw.init = &(struct clk_init_data){ .name = "cam_cc_drv_xo_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_icp_ahb_clk = { .halt_reg = 0x138fc, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x138fc, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_icp_clk = { .halt_reg = 0x138f0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x138f0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_icp_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_icp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_clk = { .halt_reg = 0x11144, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x11144, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_dsp_clk = { .halt_reg = 0x11280, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x11280, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_dsp_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_0_dsp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_0_fast_ahb_clk = { .halt_reg = 0x1128c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1128c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_0_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_clk = { .halt_reg = 0x12144, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x12144, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_dsp_clk = { .halt_reg = 0x12280, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x12280, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_dsp_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_1_dsp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_1_fast_ahb_clk = { .halt_reg = 0x1228c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1228c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_1_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_clk = { .halt_reg = 0x123d4, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x123d4, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_dsp_clk = { .halt_reg = 0x12510, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x12510, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_dsp_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_2_dsp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_2_fast_ahb_clk = { .halt_reg = 0x1251c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1251c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_2_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_lite_ahb_clk = { .halt_reg = 0x13278, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13278, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_lite_clk = { .halt_reg = 0x1312c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1312c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_lite_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = { .halt_reg = 0x13274, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13274, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_cphy_rx_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_cphy_rx_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ife_lite_csid_clk = { .halt_reg = 0x13268, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13268, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_csid_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_lite_csid_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_nps_ahb_clk = { .halt_reg = 0x1051c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1051c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_nps_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_slow_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_nps_clk = { .halt_reg = 0x104f8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x104f8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_nps_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ipe_nps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = { .halt_reg = 0x10520, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10520, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_nps_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_pps_clk = { .halt_reg = 0x10508, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10508, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_pps_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ipe_nps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = { .halt_reg = 0x10524, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10524, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_ipe_pps_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_jpeg_1_clk = { .halt_reg = 0x137ac, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x137ac, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_jpeg_clk = { .halt_reg = 0x137a0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x137a0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_jpeg_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_jpeg_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk0_clk = { .halt_reg = 0x1512c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1512c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk1_clk = { .halt_reg = 0x1525c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1525c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk2_clk = { .halt_reg = 0x1538c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1538c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk3_clk = { .halt_reg = 0x154bc, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x154bc, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk4_clk = { .halt_reg = 0x155ec, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x155ec, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk4_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk5_clk = { .halt_reg = 0x1571c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1571c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk5_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk5_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk6_clk = { .halt_reg = 0x1584c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1584c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk6_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk6_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_mclk7_clk = { .halt_reg = 0x1597c, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x1597c, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk7_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_mclk7_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_qdss_debug_clk = { .halt_reg = 0x14050, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x14050, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_qdss_debug_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_qdss_debug_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_qdss_debug_xo_clk = { .halt_reg = 0x14054, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x14054, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_qdss_debug_xo_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_xo_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sbi_clk = { .halt_reg = 0x10540, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10540, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sbi_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_ife_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sbi_fast_ahb_clk = { .halt_reg = 0x10550, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x10550, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sbi_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sfe_0_clk = { .halt_reg = 0x133c0, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x133c0, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sfe_0_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_sfe_0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = { .halt_reg = 0x133d8, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x133d8, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sfe_0_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sfe_1_clk = { .halt_reg = 0x13520, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13520, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sfe_1_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_sfe_1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = { .halt_reg = 0x13538, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x13538, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sfe_1_fast_ahb_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_fast_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_branch cam_cc_sleep_clk = { .halt_reg = 0x142cc, .halt_check = BRANCH_HALT, .clkr = { .enable_reg = 0x142cc, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "cam_cc_sleep_clk", .parent_hws = (const struct clk_hw*[]){ &cam_cc_sleep_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, }; static struct clk_regmap *cam_cc_kalama_clocks[] = { [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr, [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr, [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr, [CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr, [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, [CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr, [CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr, [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr, [CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr, [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr, [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr, [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr, [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr, [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr, [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr, [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr, [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr, [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr, [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr, [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr, [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr, [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr, [CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr, [CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr, [CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr, [CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr, [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr, [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr, [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr, [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, [CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr, [CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr, [CAM_CC_DRV_AHB_CLK] = &cam_cc_drv_ahb_clk.clkr, [CAM_CC_DRV_XO_CLK] = &cam_cc_drv_xo_clk.clkr, [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr, [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr, [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr, [CAM_CC_IFE_0_DSP_CLK_SRC] = &cam_cc_ife_0_dsp_clk_src.clkr, [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr, [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr, [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr, [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr, [CAM_CC_IFE_1_DSP_CLK_SRC] = &cam_cc_ife_1_dsp_clk_src.clkr, [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr, [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr, [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr, [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr, [CAM_CC_IFE_2_DSP_CLK_SRC] = &cam_cc_ife_2_dsp_clk_src.clkr, [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr, [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr, [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr, [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr, [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr, [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr, [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr, [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr, [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr, [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr, [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr, [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr, [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr, [CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr, [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr, [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr, [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr, [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr, [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr, [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr, [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr, [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr, [CAM_CC_PLL0] = &cam_cc_pll0.clkr, [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, [CAM_CC_PLL1] = &cam_cc_pll1.clkr, [CAM_CC_PLL10] = &cam_cc_pll10.clkr, [CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr, [CAM_CC_PLL11] = &cam_cc_pll11.clkr, [CAM_CC_PLL11_OUT_EVEN] = &cam_cc_pll11_out_even.clkr, [CAM_CC_PLL12] = &cam_cc_pll12.clkr, [CAM_CC_PLL12_OUT_EVEN] = &cam_cc_pll12_out_even.clkr, [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, [CAM_CC_PLL2] = &cam_cc_pll2.clkr, [CAM_CC_PLL3] = &cam_cc_pll3.clkr, [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, [CAM_CC_PLL4] = &cam_cc_pll4.clkr, [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, [CAM_CC_PLL5] = &cam_cc_pll5.clkr, [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, [CAM_CC_PLL6] = &cam_cc_pll6.clkr, [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, [CAM_CC_PLL7] = &cam_cc_pll7.clkr, [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr, [CAM_CC_PLL8] = &cam_cc_pll8.clkr, [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr, [CAM_CC_PLL9] = &cam_cc_pll9.clkr, [CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr, [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr, [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr, [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr, [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr, [CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr, [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr, [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr, [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr, [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr, [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr, [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr, [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr, [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, }; static const struct qcom_reset_map cam_cc_kalama_resets[] = { [CAM_CC_BPS_BCR] = { 0x10000 }, [CAM_CC_DRV_BCR] = { 0x142d0 }, [CAM_CC_ICP_BCR] = { 0x137c0 }, [CAM_CC_IFE_0_BCR] = { 0x11000 }, [CAM_CC_IFE_1_BCR] = { 0x12000 }, [CAM_CC_IFE_2_BCR] = { 0x12290 }, [CAM_CC_IPE_0_BCR] = { 0x103b4 }, [CAM_CC_QDSS_DEBUG_BCR] = { 0x13f20 }, [CAM_CC_SBI_BCR] = { 0x10528 }, [CAM_CC_SFE_0_BCR] = { 0x1327c }, [CAM_CC_SFE_1_BCR] = { 0x133dc }, }; static const struct regmap_config cam_cc_kalama_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x16320, .fast_io = true, }; /* * cam_cc_gdsc_clk */ static struct critical_clk_offset critical_clk_list[] = { { .offset = 0x1419c, .mask = BIT(0) }, }; static struct qcom_cc_desc cam_cc_kalama_desc = { .config = &cam_cc_kalama_regmap_config, .clks = cam_cc_kalama_clocks, .num_clks = ARRAY_SIZE(cam_cc_kalama_clocks), .resets = cam_cc_kalama_resets, .num_resets = ARRAY_SIZE(cam_cc_kalama_resets), .clk_regulators = cam_cc_kalama_regulators, .num_clk_regulators = ARRAY_SIZE(cam_cc_kalama_regulators), .critical_clk_en = critical_clk_list, .num_critical_clk = ARRAY_SIZE(critical_clk_list), }; static const struct of_device_id cam_cc_kalama_match_table[] = { { .compatible = "qcom,kalama-camcc" }, { .compatible = "qcom,kalama-camcc-v2" }, { } }; MODULE_DEVICE_TABLE(of, cam_cc_kalama_match_table); static void cam_cc_kalama_fixup_kalamav2(struct regmap *regmap) { clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config_kalama_v2); cam_cc_pll11.config = &cam_cc_pll11_config_kalama_v2; clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config_kalama_v2); cam_cc_pll12.config = &cam_cc_pll12_config_kalama_v2; cam_cc_ife_1_dsp_clk_src.freq_tbl = ftbl_cam_cc_ife_1_dsp_clk_src_kalama_v2; cam_cc_ife_1_dsp_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] = 466000000; cam_cc_ife_2_dsp_clk_src.freq_tbl = ftbl_cam_cc_ife_2_dsp_clk_src_kalama_v2; cam_cc_ife_2_dsp_clk_src.clkr.vdd_data.rate_max[VDD_LOWER] = 466000000; } static int cam_cc_kalama_fixup(struct platform_device *pdev, struct regmap *regmap) { const char *compat = NULL; int compatlen = 0; compat = of_get_property(pdev->dev.of_node, "compatible", &compatlen); if (!compat || compatlen <= 0) return -EINVAL; if (!strcmp(compat, "qcom,kalama-camcc-v2")) cam_cc_kalama_fixup_kalamav2(regmap); return 0; } static int cam_cc_kalama_probe(struct platform_device *pdev) { struct regmap *regmap; int ret; regmap = qcom_cc_map(pdev, &cam_cc_kalama_desc); if (IS_ERR(regmap)) return PTR_ERR(regmap); ret = register_qcom_clks_pm(pdev, true, &cam_cc_kalama_desc); if (ret) dev_err(&pdev->dev, "Failed to register for pm ops\n"); clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); clk_rivian_ole_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); ret = cam_cc_kalama_fixup(pdev, regmap); if (ret) return ret; /* Enabling always ON clocks */ clk_restore_critical_clocks(&pdev->dev); ret = qcom_cc_really_probe(pdev, &cam_cc_kalama_desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register CAM CC clocks\n"); return ret; } pm_runtime_put_sync(&pdev->dev); dev_info(&pdev->dev, "Registered CAM CC clocks\n"); return ret; } static void cam_cc_kalama_sync_state(struct device *dev) { qcom_cc_sync_state(dev, &cam_cc_kalama_desc); } static struct platform_driver cam_cc_kalama_driver = { .probe = cam_cc_kalama_probe, .driver = { .name = "cam_cc-kalama", .of_match_table = cam_cc_kalama_match_table, .sync_state = cam_cc_kalama_sync_state, }, }; static int __init cam_cc_kalama_init(void) { return platform_driver_register(&cam_cc_kalama_driver); } subsys_initcall(cam_cc_kalama_init); static void __exit cam_cc_kalama_exit(void) { platform_driver_unregister(&cam_cc_kalama_driver); } module_exit(cam_cc_kalama_exit); MODULE_DESCRIPTION("QTI CAM_CC KALAMA Driver"); MODULE_LICENSE("GPL v2");