/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_ECPRI_CC_CINDER_H #define _DT_BINDINGS_CLK_QCOM_ECPRI_CC_CINDER_H /* ECPRI_CC clocks */ #define ECPRI_CC_ECPRI_CG_CLK 0 #define ECPRI_CC_ECPRI_CLK_SRC 1 #define ECPRI_CC_ECPRI_DMA_CLK 2 #define ECPRI_CC_ECPRI_DMA_CLK_SRC 3 #define ECPRI_CC_ECPRI_DMA_NOC_CLK 4 #define ECPRI_CC_ECPRI_FAST_CLK 5 #define ECPRI_CC_ECPRI_FAST_CLK_SRC 6 #define ECPRI_CC_ECPRI_FAST_DIV2_CLK 7 #define ECPRI_CC_ECPRI_FAST_DIV2_CLK_SRC 8 #define ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK 9 #define ECPRI_CC_ECPRI_FR_CLK 10 #define ECPRI_CC_ECPRI_ORAN_CLK_SRC 11 #define ECPRI_CC_ECPRI_ORAN_DIV2_CLK 12 #define ECPRI_CC_ETH_100G_C2C0_HM_FF_CLK_SRC 13 #define ECPRI_CC_ETH_100G_C2C0_UDP_FIFO_CLK 14 #define ECPRI_CC_ETH_100G_C2C1_UDP_FIFO_CLK 15 #define ECPRI_CC_ETH_100G_C2C_0_HM_FF_0_CLK 16 #define ECPRI_CC_ETH_100G_C2C_0_HM_FF_1_CLK 17 #define ECPRI_CC_ETH_100G_C2C_HM_FF_0_DIV_CLK_SRC 18 #define ECPRI_CC_ETH_100G_C2C_HM_FF_1_DIV_CLK_SRC 19 #define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK 20 #define ECPRI_CC_ETH_100G_C2C_HM_MACSEC_CLK_SRC 21 #define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_CLK 22 #define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_0_DIV_CLK_SRC 23 #define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_CLK 24 #define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_1_DIV_CLK_SRC 25 #define ECPRI_CC_ETH_100G_DBG_C2C_HM_FF_CLK_SRC 26 #define ECPRI_CC_ETH_100G_DBG_C2C_UDP_FIFO_CLK 27 #define ECPRI_CC_ETH_100G_FH0_HM_FF_CLK_SRC 28 #define ECPRI_CC_ETH_100G_FH0_MACSEC_CLK_SRC 29 #define ECPRI_CC_ETH_100G_FH1_HM_FF_CLK_SRC 30 #define ECPRI_CC_ETH_100G_FH1_MACSEC_CLK_SRC 31 #define ECPRI_CC_ETH_100G_FH2_HM_FF_CLK_SRC 32 #define ECPRI_CC_ETH_100G_FH2_MACSEC_CLK_SRC 33 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_CLK 34 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_0_DIV_CLK_SRC 35 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_CLK 36 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_1_DIV_CLK_SRC 37 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_CLK 38 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_2_DIV_CLK_SRC 39 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_CLK 40 #define ECPRI_CC_ETH_100G_FH_0_HM_FF_3_DIV_CLK_SRC 41 #define ECPRI_CC_ETH_100G_FH_0_UDP_FIFO_CLK 42 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_CLK 43 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_0_DIV_CLK_SRC 44 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_CLK 45 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_1_DIV_CLK_SRC 46 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_CLK 47 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_2_DIV_CLK_SRC 48 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_CLK 49 #define ECPRI_CC_ETH_100G_FH_1_HM_FF_3_DIV_CLK_SRC 50 #define ECPRI_CC_ETH_100G_FH_1_UDP_FIFO_CLK 51 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_CLK 52 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_0_DIV_CLK_SRC 53 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_CLK 54 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_1_DIV_CLK_SRC 55 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_CLK 56 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_2_DIV_CLK_SRC 57 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_CLK 58 #define ECPRI_CC_ETH_100G_FH_2_HM_FF_3_DIV_CLK_SRC 59 #define ECPRI_CC_ETH_100G_FH_2_UDP_FIFO_CLK 60 #define ECPRI_CC_ETH_100G_FH_MACSEC_0_CLK 61 #define ECPRI_CC_ETH_100G_FH_MACSEC_1_CLK 62 #define ECPRI_CC_ETH_100G_FH_MACSEC_2_CLK 63 #define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK 64 #define ECPRI_CC_ETH_100G_MAC_C2C_HM_REF_CLK_SRC 65 #define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK 66 #define ECPRI_CC_ETH_100G_MAC_DBG_C2C_HM_REF_CLK_SRC 67 #define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK 68 #define ECPRI_CC_ETH_100G_MAC_FH0_HM_REF_CLK_SRC 69 #define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK 70 #define ECPRI_CC_ETH_100G_MAC_FH1_HM_REF_CLK_SRC 71 #define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK 72 #define ECPRI_CC_ETH_100G_MAC_FH2_HM_REF_CLK_SRC 73 #define ECPRI_CC_ETH_DBG_NFAPI_AXI_CLK 74 #define ECPRI_CC_ETH_DBG_NOC_AXI_CLK 75 #define ECPRI_CC_ETH_PHY_0_OCK_SRAM_CLK 76 #define ECPRI_CC_ETH_PHY_0_OCK_SRAM_MUX_CLK_SRC 77 #define ECPRI_CC_ETH_PHY_1_OCK_SRAM_CLK 78 #define ECPRI_CC_ETH_PHY_1_OCK_SRAM_MUX_CLK_SRC 79 #define ECPRI_CC_ETH_PHY_2_OCK_SRAM_CLK 80 #define ECPRI_CC_ETH_PHY_2_OCK_SRAM_MUX_CLK_SRC 81 #define ECPRI_CC_ETH_PHY_3_OCK_SRAM_CLK 82 #define ECPRI_CC_ETH_PHY_3_OCK_SRAM_MUX_CLK_SRC 83 #define ECPRI_CC_ETH_PHY_4_OCK_SRAM_CLK 84 #define ECPRI_CC_ETH_PHY_4_OCK_SRAM_MUX_CLK_SRC 85 #define ECPRI_CC_MSS_EMAC_CLK 86 #define ECPRI_CC_MSS_EMAC_CLK_SRC 87 #define ECPRI_CC_MSS_ORAN_CLK 88 #define ECPRI_CC_PHY0_LANE0_RX_CLK 89 #define ECPRI_CC_PHY0_LANE0_RX_CLK_SRC 90 #define ECPRI_CC_PHY0_LANE0_TX_CLK 91 #define ECPRI_CC_PHY0_LANE0_TX_CLK_SRC 92 #define ECPRI_CC_PHY0_LANE1_RX_CLK 93 #define ECPRI_CC_PHY0_LANE1_RX_CLK_SRC 94 #define ECPRI_CC_PHY0_LANE1_TX_CLK 95 #define ECPRI_CC_PHY0_LANE1_TX_CLK_SRC 96 #define ECPRI_CC_PHY0_LANE2_RX_CLK 97 #define ECPRI_CC_PHY0_LANE2_RX_CLK_SRC 98 #define ECPRI_CC_PHY0_LANE2_TX_CLK 99 #define ECPRI_CC_PHY0_LANE2_TX_CLK_SRC 100 #define ECPRI_CC_PHY0_LANE3_RX_CLK 101 #define ECPRI_CC_PHY0_LANE3_RX_CLK_SRC 102 #define ECPRI_CC_PHY0_LANE3_TX_CLK 103 #define ECPRI_CC_PHY0_LANE3_TX_CLK_SRC 104 #define ECPRI_CC_PHY1_LANE0_RX_CLK 105 #define ECPRI_CC_PHY1_LANE0_RX_CLK_SRC 106 #define ECPRI_CC_PHY1_LANE0_TX_CLK 107 #define ECPRI_CC_PHY1_LANE0_TX_CLK_SRC 108 #define ECPRI_CC_PHY1_LANE1_RX_CLK 109 #define ECPRI_CC_PHY1_LANE1_RX_CLK_SRC 110 #define ECPRI_CC_PHY1_LANE1_TX_CLK 111 #define ECPRI_CC_PHY1_LANE1_TX_CLK_SRC 112 #define ECPRI_CC_PHY1_LANE2_RX_CLK 113 #define ECPRI_CC_PHY1_LANE2_RX_CLK_SRC 114 #define ECPRI_CC_PHY1_LANE2_TX_CLK 115 #define ECPRI_CC_PHY1_LANE2_TX_CLK_SRC 116 #define ECPRI_CC_PHY1_LANE3_RX_CLK 117 #define ECPRI_CC_PHY1_LANE3_RX_CLK_SRC 118 #define ECPRI_CC_PHY1_LANE3_TX_CLK 119 #define ECPRI_CC_PHY1_LANE3_TX_CLK_SRC 120 #define ECPRI_CC_PHY2_LANE0_RX_CLK 121 #define ECPRI_CC_PHY2_LANE0_RX_CLK_SRC 122 #define ECPRI_CC_PHY2_LANE0_TX_CLK 123 #define ECPRI_CC_PHY2_LANE0_TX_CLK_SRC 124 #define ECPRI_CC_PHY2_LANE1_RX_CLK 125 #define ECPRI_CC_PHY2_LANE1_RX_CLK_SRC 126 #define ECPRI_CC_PHY2_LANE1_TX_CLK 127 #define ECPRI_CC_PHY2_LANE1_TX_CLK_SRC 128 #define ECPRI_CC_PHY2_LANE2_RX_CLK 129 #define ECPRI_CC_PHY2_LANE2_RX_CLK_SRC 130 #define ECPRI_CC_PHY2_LANE2_TX_CLK 131 #define ECPRI_CC_PHY2_LANE2_TX_CLK_SRC 132 #define ECPRI_CC_PHY2_LANE3_RX_CLK 133 #define ECPRI_CC_PHY2_LANE3_RX_CLK_SRC 134 #define ECPRI_CC_PHY2_LANE3_TX_CLK 135 #define ECPRI_CC_PHY2_LANE3_TX_CLK_SRC 136 #define ECPRI_CC_PHY3_LANE0_RX_CLK 137 #define ECPRI_CC_PHY3_LANE0_RX_CLK_SRC 138 #define ECPRI_CC_PHY3_LANE0_TX_CLK 139 #define ECPRI_CC_PHY3_LANE0_TX_CLK_SRC 140 #define ECPRI_CC_PHY3_LANE1_RX_CLK 141 #define ECPRI_CC_PHY3_LANE1_RX_CLK_SRC 142 #define ECPRI_CC_PHY3_LANE1_TX_CLK 143 #define ECPRI_CC_PHY3_LANE1_TX_CLK_SRC 144 #define ECPRI_CC_PHY3_LANE2_RX_CLK 145 #define ECPRI_CC_PHY3_LANE2_RX_CLK_SRC 146 #define ECPRI_CC_PHY3_LANE2_TX_CLK 147 #define ECPRI_CC_PHY3_LANE2_TX_CLK_SRC 148 #define ECPRI_CC_PHY3_LANE3_RX_CLK 149 #define ECPRI_CC_PHY3_LANE3_RX_CLK_SRC 150 #define ECPRI_CC_PHY3_LANE3_TX_CLK 151 #define ECPRI_CC_PHY3_LANE3_TX_CLK_SRC 152 #define ECPRI_CC_PHY4_LANE0_RX_CLK 153 #define ECPRI_CC_PHY4_LANE0_RX_CLK_SRC 154 #define ECPRI_CC_PHY4_LANE0_TX_CLK 155 #define ECPRI_CC_PHY4_LANE0_TX_CLK_SRC 156 #define ECPRI_CC_PHY4_LANE1_RX_CLK 157 #define ECPRI_CC_PHY4_LANE1_RX_CLK_SRC 158 #define ECPRI_CC_PHY4_LANE1_TX_CLK 159 #define ECPRI_CC_PHY4_LANE1_TX_CLK_SRC 160 #define ECPRI_CC_PHY4_LANE2_RX_CLK 161 #define ECPRI_CC_PHY4_LANE2_RX_CLK_SRC 162 #define ECPRI_CC_PHY4_LANE2_TX_CLK 163 #define ECPRI_CC_PHY4_LANE2_TX_CLK_SRC 164 #define ECPRI_CC_PHY4_LANE3_RX_CLK 165 #define ECPRI_CC_PHY4_LANE3_RX_CLK_SRC 166 #define ECPRI_CC_PHY4_LANE3_TX_CLK 167 #define ECPRI_CC_PHY4_LANE3_TX_CLK_SRC 168 #define ECPRI_CC_PLL0 169 #define ECPRI_CC_PLL1 170 #define ECPRI_CC_EMAC_SYNCE_CMUX_CLK_SRC 171 #define ECPRI_CC_EMAC_SYNCE_CMUX_CLK 172 #define ECPRI_CC_EMAC_SYNCE_DIV_CLK_SRC 173 /* ECPRI_CC resets */ #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ECPRI_SS_BCR 0 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_C2C_BCR 1 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH0_BCR 2 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH1_BCR 3 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_FH2_BCR 4 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_ETH_WRAPPER_TOP_BCR 5 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_MODEM_BCR 6 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_NOC_BCR 7 #define ECPRI_CC_CLK_CTL_TOP_ECPRI_CC_EMAC_SYNCE_ACGCR 8 #endif