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module found, fpmath accuracy not a positive number!Invoke result does not dominate all uses!Vector GEP must have vector indices!Vector GEP type does not match pointer type!cmpxchg failure ordering cannot include release semanticsType too small for SExtPersonality function doesn't match others in functionisa .cfi_remember_stateNumber of evaluated fixupsEscape bytesGOTClobberType: .phi.trans.insertbbsubgraph cluster_scev-aa.ivqgpu.symbols.const.splitNumber of loops completely unrolledlcmplikely-branch-weightunwindbbnew-gen-selselkillFunc && "kill function is NULL"allowExtractOpenGL Kill Workaround Pass_wrapBBop==Instruction::GetElementPtr && "const expr not used by load"GLNext remove global fencebb36-vectorize-max-vec-sizeSrcI && "SrcI cannot be null"!insaneIntVal(C) && "Insane coefficient"IsFp && BufHasFpVal && "Incorret state"destVal && "destVal is Null"ivislessdivLHSShuffle && "LHSShuffle is NULL!"[0]qgpu_no_base_pointersthread-pre-splitloop-deletionReroll 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section should have a 0 size"NumWaves <= ReqdMaxSubgroups && "Inconsistent number of waves calculation in compiler BE"float The register relative offsetmust be within [-128,128) on A6x- / [0, 256) on A7x+: wrong register class. 0 && "should be virtual regs (post-ra)"pos && pos->getPrevNode() && "invalid position"false && "unrecognized OR opcode" has multiple definitions.res_hifalse && "inst is not an intrinsic!"ptr_to_Intv != NULL && !isa(v) && "Invalid scalarized instruction"eanble-split-longLI_Iter->End <= UnionIter.start() && "Expected non-overlap", basereg: uppf-min-usesAt least one non-casting use to admit Dumplicate Label %s Found LDC: src0 not allowed from a6x LDST: Out of Range Offset with ldp instruction. Allowed Range is 13bits, |0 - 8191| LDST: Out of Range Offset with stthr.a+ instruction. Allowed Range is 9 bits, |0 - 511|the stgb instruction source 2 must be immediate/GPR value STIBBLK: for src mode0/4 src2 should be IMM for a6x and aboveSTIBBLK: for src mode0/1/2, baseid ignored for a6x and aboveLDG.k: for ldg.k instruction allowed only from a7x ALU3 - SHIFT MERGE: Cannot be predicate registersTexture: img sad/ssd s34 should be enabled Texture: src2 should be enabled when src2 is provided for img instr Texture: rbi instr is allowed only in a6x and aboveTexture: .clp options are only allowed for texture fetch instructions(*sam*, conv*, gather*) Texture: (F32) are valid destination data types with DSX/DSYISAM: offset modifier cannot be used for A5x and below archtype with ISAM FLOAT32uint8PATCH14PATCH18PATCH19PATCH22PARTITIONING_FRACTIONAL_ODDATTRIBUTE%s%s%sVERTEXIDMISCINPUTUAVBaseReg Invalid Dimension Type given with dcl_resourceADDUINSTRLOADTHRAU32INSTRSTTHRAS32INSTRSTXAU32INSTRSTLF16INSTRG2LF32INSTRATOMADDGS32INSTRSTLWS8INSTRLOADGBAT1DS32INSTRSTGBA1DTYPEINSTRFENCERINSTRFENCERWINSTRSLEEPSINSTRLOADGBU4DU32INSTRLOADGBU4DF32INSTRLOADGKINSTRGETLASTW8INSTRATOMSUBGENSOCS32INSTRATOMINCGENGPUU32INSTRATOMINCGSOCU32INSTRATOMINCLNGGPUU32INSTRATOMINCLNGGPUS32INSTRATOMMAXGSOCS32INSTRATOMBORGNU322DINSTRATOMBORGNU323DINSTRATOMBADDGS321D1LINSTRATOMBASUBGU322D1LINSTRATOMBASUBGS322D1LINSTRATOMBAANDGU321D1LINSTRATOMBAANDGU323D1LINSTRATOMBAORGS323DINSTRATOMBAXORGU321DINSTRATOMBXORGS323D1LINSTRATOMBINCRGGS321D1LINSTRATOMBAINCRGGS32INSTRATOMBAINCRGGU322D1LINSTRATOMBDECGS321D1LINSTRATOMBADECLNGS323DINSTRATOMBADECLNGU322D1LINSTRNOTBINSTRXORBINSTRMADU24INSTRMOVU16INSTRMOVF32INSTRATOMANDLS32INSTRGETLODINSTRSTIBS322DINSTRSTIBAS321DTINSTRRESLAYOUT2DINSTRSWZU16INSTRATOMCMPXGENU32INSTRLDIBTYPEDS322DRCKINSTRLDIBBLKCF163DINSTRLOADLBLKS16INSTRLDIBAS162DRCKINSTRLDIBAF161DINSTRLDIBAF161DTINSTRLDIBAU162DINSTRGATF16F32INSTRSCTS16U16INSTREMITINSTRSHFLRUPW4U16INSTRDCL_CL_GROUP_SIZE_TOKENDCL_CL_LOCALMEMBASECONSTREGID_TOKENNSHBITTOKENDECLARE_HS_ISCONTROLPOINTBYPASSDCL_INITIAL_TEX_ENTRY_STRUCDCL_UGPR_INDEX_WGSIZESOURCE_ABS_NEGSWIZZLE_IDSTGENINSTRMININSTRMULLOWINSTRALU3_INSTRMOV_SOURCE_OPERAND2TEX_INSTRBRCSTINSTRDCL_IMM_VALUEALU2: Destination Operand can not be relatively addressed.MOV/COV: MOVS with optional Lane ID should have dst of uGPR dst and src0 of sGPRTEX: Destination operand of TEX cannot be mailboxpSymbolsrcInfobindlessBaseUsagecsADRENO_RESUMECOUNTER_INFOADRENO_GATHER_SWIZZLE_PATCHING_READRGB10A2_EXTRACTADRENO_BINDLESS_USAGE_INFOUBOArrayMAX_FRAGMENT_UNIFORM_VECTORSMAX_VERTEX_OUTPUT_VECTORSMIN_PROGRAM_TEXEL_OFFSETOES_SHADER_MS_INTERPOLATIONQCOM_FRAMEBUFFER_CLOCKshaderByteSizeMaxFragmentAtomicCounterBuffers============ Bind Group Info ============ "/>false && "Assert Index:[9] Incorrect symbol type"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/HLC/GlUtils.hppGL_SAMPLER_EXTERNAL_NV21_AMDGL_SAMPLER_2D_ARRAY_SHADOWQGL_INT_TEXTURE_CUBE_ARRAYRGBA8 array, flags = %d strideInBytes = %d(pos2 != llvm::StringRef::npos) && "Assert Index:[48] invalid GV name"0 && !"Unrecognized symbol type"$TessPatchDisableVPrimUint32Force Sample Frequency uint32Constants for texture foveation subsampled layout patching (Normalized coord offset in x, Normalized coord offset in y)vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/include/LA/gl_core/Symbol.hppSupportInitialBarySupportOffsetVertexIDInVFDenableSingleCommandStreamllvm.qgpu.absneg.f16llvm.qgpu.fcreate.map8.v8f16.f16llvm.qgpu.fcombine4.f16llvm.qgpu.fcombine4.f32llvm.qgpu.fcreate.map3.v3f32.f32llvm.qgpu.sign.f32(curSym->getSymbolID() == QGLC_BUILT_IN_INDEX_CLIP_DISTANCE) || (curSym->getSymbolID() == QGLC_BUILT_IN_INDEX_CULL_DISTANCE)gl_PerVertex.gl_Positioncallee != __null && "callee is not defined"dstTy->isArrayTy()qgpu.glsl.link.errorpointerTy && "pointer type is expected"HeadOldTerm && "Terminator inst is expected"internals != __nullgl_SubgroupEqMaskgl_SubgroupLtMaskget_intersection_object_ray_directionIgnoreHitarrayDimensions == __nullqgpu.output.gl.pervertex.sizegvType != NULLGV != NULL && "Global Variable cannot be NULL"(texCoordNumElements > 1 && texCoordNumElements <= 4) && "tex coord must have 2, 3, or 4 elements"Error: Geomery shader didn't specify input primtive typefalse && "Certain Tess load cases not handled yet"$ShareGLobalSizegl_MaxComputeWorkGroupCountgl_ShadingRateFlag2VerticalPixelsEXTutexture1Dtexture2Diimage2DArrayuimage2DMSshadowOfbaseAddr != __null && "indexing a null pointer"img2aimg3d%dpackSnorm2x16gl_ClipDistance compilation errors. No code generated. ++ifdefcan't modify gl_FragInvocationCountEXTcan't modify gl_MaxComputeTextureImageUnitscan't modify gl_MaxTessPatchComponentsGL_AMD_flat_varyinggl_SamplePosition cannot be used with GL_QCOM_shader_framebuffer_fetch_rate extensiondeclarationarray must be declared with a size before using this methodlowpConvert Float to BoolConvert Bool to FloatConvert Float to IntConvert Bool to IntSequence Function Parameters: Construct bvec3Texture2dLodcalcBlockInfoNo loop body Constant Folding cannot be done for matrix times vectortexture3DProjgl_MaxAtomicCounterBufferSizegl_LastFragStencilARMgl_BoundingBoxEXTgl_FragColorlayout 'yuv' can not be combined with other layout qualifiers.GLSL line %d: Error: %s Token is too longGLSL.std.450dstDataType1 && "dstDataType1 is NULL"false && "unsupported image type!"(scopeSubgroup == ScopeSubgroup) && "workgroup scope operations are not supported"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/vulkan/codegen/SPVDecoder.cppOpMemberNameOpTypeReserveIdOpImageQueryFormatOpUModOpUGreaterThanOpControlBarrierOpAtomicStoreOpImageSparseSampleImplicitLodError: Unscoped name checking failed.!shaderStackSizes.empty()curr.stack.offsetgetCommRayTMaxahit.sidremat_beginget.rayidoffsetInBytes % sizeof(int) == 0 && "invalid alignment"addr != NULLasptr.l.l32loadCullMaskunused.iddrop.gascopy.valfalse && "other users than load/store?".ss_i64val (CW) (Pow2) (ChromaSampler) (ITU_601) (Gather4B)]: [ADRENO_DEVICE_ALLOCATION][pointSizeRegID: needsVertexID: regIDs[inputControlPointCount: numStreams: vertexStride: [ADRENO_INFO_LOG] (Ver ConstSwizzleX: [ADRENO_ASTC_PATCHING_STATIC_READ] (Ver instructionOffset: [ADRENO_ASTC_PATCHING_DYNAMIC_READ] (Ver maskBit: [ADRENO_BOOLEAN_CONSTANT_EXPRESSION][bindlessOffset: [ADRENO_BINDLESS_GROUP_EMULATION_DATA] (Ver [ADRENO_BINDLESS_GROUP_EMULATION_DATA][[ADRENO_OBJ_DATA] (Ver [ADRENO_INPUT_TARGET_INFO] (Ver descOffsetInDescTable: virtualRegIDMask: [ADRENO_CONST_COLOR_OUTPUT] (Ver imageAttachmentDataEntries: renderingDescriptorGroups: payloadSize: [ADRENO_MS_OUTPUT_ATTR_STRIDES] (Ver hasCrossWaveCommunication: .metadataName.dynamicallyIndexesConstantBuffers.numVec4Regs[ADRENO_VS_INPUTS][A4X_MERGED_SHADER_INPUTS].forceFragmentFrequency.depthStencilInputAttachmentRead[ADRENO_SO_ELEMENT][ADRENO_CS_INPUTS_V2].isBindlessLoad.patchedTextureSlotIndexBase.dynamicTextureMappings.slotType[ADRENO_SHADER_DEBUG_INFO][GL_SYMBOL_INFO_SAMPLER].namedConstInfo.isCentroid.hasUnsizedArray.location[GL_IRSHADER].virtualRegIndex.constColorValW.maxVertexCount.indexBufferViewStride ======== Shader Stats MeshShader - RND : %8d,%8d (rpt), ratio %5.2f - immoff : %8d - offset : %8d - conv : %8d - ldc : %8d,%8d (rpt), ratio %5.2f - stga : %8d,%8d (rpt), ratio %5.2f - ldgbasize : %8d - memory_ldAllsize : %8d - Flow Instrs : %8d - desc used number : %8d ugpr_footprint - sGPR Registers : %8d move_class_rptmem.stgmem.stg_rptmem.preamble_ldck_rptALU instruction count 32bitFull precision register footprint per shader instanceMemory write instruction countEnableSingleRegisterPoolSpecializationSRefIsAssembleShaderEnableUGPREnableHWStereoRenderingStageAvailableConstLimitsAllowUniformInGlobalInitCompilerOptionStrInitialTextureThresholdFreeSystemMemoryDbgCallbackconst INTERNAL_RESOURCE_SIGNATURE_DESCRIPTOR_TABLEStaticSamplerbufferLocationAUX_BIND_GROUP_ELEMENT ChromaSampler Unable to parse AddInstrumentation value 'Unable to parse DisableMinPrecisionOps value 'Unable to parse FragDataBindingBufferRef value 'Unable to parse Verbose value 'Unable to parse EnableConstColorBypass value 'Unable to parse EnableA6xInstancePacking value 'Unable to parse EnableBindlessCBPreloadViaPreamble value 'Unable to parse EnableBGPR value 'Unable to parse RotationShaderPatching value 'Unable to parse ForceRotationAll value 'Unable to parse DisableVersionCheck value ' SkipGarbageCollect (false): do not garbage collection LLVM objects after compile QCCOptionString (__null): string-based QCC option (debug-only) EnableHWStereoRendering (false): (a6x+) enable HW stereo rendering EnableMultiPositionOutput (false): (a6x+) enable multiple position output in VS (only valid if HW stereo rending is On) EnableSWViewId (false): Enable view id emulation for multi-view EnableScratchBindlessBase (): Whether or not the scratch bindless base is enabled. A618A635 A507 arraySizeName=",CS:0xASICFamilyUnknownpInitialTexturesPtr + pInitialTexturesDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"pImageAttachmentPtr + pImageAttachmentDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"psymbolsTempPtr + psymbolsTempDesc->m_ElementSize * i && "memcpy dest pointer is NULL!" Gives a list of device allocations made during compilation that should be freed by the driver. Version 1.0: Added numAllocations Added deviceAllocations Information about the format of each render target defined in the shader. Version 1.0: Added numRenderTargets Added formats Information about statically indexed textures returned from the shader patching interface. The patched texture index will be used to read the .W component of the texture since hardware will always return 1 for this component for some chips if the texture format is SRGB encoded in a compressed texture format. The driver will be responsible for duplicating the texture into the new slot using a linear RGBA format instead of an SRGB format. Version 1.0: Added sourceTextureSlotIndex: The original texture slot index referenced. Added patchedTextureSlotIndex: The texture slot index referenced in the patching code. Information necessary to patch a static texture read in the bytecode. The instruction immediately after the instruction referenced must be a NOP, which will be replaced by the new texture sampling instruction. Note that this structure should be used for all gather instructions if gather swizzle patching is required, since the component read may change even if initially it is not reading the alpha channel. Version 1.0: Added instructionOffset: The offset of a texture instruction in the bytecode. Added textureIndex: The index of the texture read in the instruction. memID != NULLspacequotation-markequals-signtildeinvalid repetition count(s)b, ' value invalid for integer argument!print-all-optionsnot enough values!OVERVIEW: numberDW_TAG_enumeration_typeDW_TAG_inlined_subroutineDW_TAG_variant_partDW_TAG_GNU_formal_parameter_packDW_LANG_Ctrack-memory%5.1f%c%d%02dv%dSum == Elements + Grow && "Bad distribution sum"NewSize[PosPair.first] && "Too few elements to need Grow"Offset = metadata unoueqne xchg and =TPOFF__constructor__debug_framecoalescedS_COALESCEDNot implemented yet vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/Target/TargetRegisterInfo.hWe do not support this DWARF encoding yet!SS#memset_pattern16powfprecise ===== Alias Analysis Counter Report ===== NoModRef must alias responses vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Analysis/BasicAliasAnalysis.cppD && "Illegal division by zero!"Print postdominance tree of function to 'dot' file (with no function bodies)Number of Sub insts ScalarNumber of ZExt insts ScalarNumber of UserOp1 insts ScalarUnusual: Unnamed function with non-local linkageUndefined result: xor(undef, undef)Number of dirty cached non-local responsesprint regions in detail with element_iteratorRegion Graphstyle = filled; qgpu.scalar.analysis.hintLoop-Closed SSA Form PassNumber of alloca's promoted with a single storeCV && "Not a comparison?"sam0->getMetadata(LLVM_METADATA_NAME_RESOURCE_USAGE) == sam1->getMetadata(LLVM_METADATA_NAME_RESOURCE_USAGE) && "Mismatched resource usage between foldable sams"i < NumContainedTys && "Index out of range!"!attr.textSam.is1Dbb-vectorize-vector-bitsslp-thresholdvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Vectorize/SLPVectorizer.cppI && "bundle member must be an instruction"bb36-vectorize-pow2-len-only.sumsrcPtr && dstPtr && "invalid instruction"for.epilog.memcpyWARNING: While resolving call to function 'sadd.subsubcNumber of memory instructions whose address computations were sunkloopdeletion.remove.infinite.looprevert-opencl-opt-2021Number of allocas promotedEdgeBundlesLower Garbage Collection Instructionsifcvt-limitdisable-ifcvt-triangleI != r2iMap_.end() && "Interval does not exist for register"Number of folded stack accessesj + Count <= N && "Invalid dest range"localstackallocderived from LLVM BB Predecessors according to CFG:size=live-valuesearlyclobber,:[mem mem:machine-licmSize limit for the the MII.Missing slot indexNon-terminator instruction after the first terminatorRegister class Last instruction was at LiveVariables: Block should not be in AliveBlocksDifferent value live out of predecessorDisable Machine Common Subexpression EliminationAfter codegen DCE passNumber of bitcasts eliminatedpost-RA-schedulerran out of registers during register allocation!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned"split-spill-modeBefore qgpu greedy register allocatorpbqpJoin physical register copiesgc_mapgc_stackentryexception_gepstrongphielimTail DuplicationCan't handle live physical register dependency!sched-high-latency-cyclesValueTypeTargetFrameIndexfexp2sign_extendcvt_fubr_ccbswapsetgeVector LegalizationGraphRoot__modhi3__fixxfdi__fixunsdfhi__sync_val_compare_and_swap_1__sync_fetch_and_xor_4Error at end of PARAMATTR blockInvalid TYPE_CODE_NUMENTRY recordinvalid TYPE tableInvalid METADATA_KIND recordInvalid CST_STRING recordInvalid UseList reader!Invalid METADATA_ATTACHMENT reader!Invalid FUNC_CODE_DEBUG_LOC recordInvalid INSERTVAL recordInvalid LOADATOMIC recordCould not find Function in streamNumber of functions removeduse-gvn-after-vectorizationQGPUSortFunctionsPassmIsCLKernelmoduleugpr_subgroup_ballotVebose message for pre-RA SSA destructionqgpu.enable.shared.constant Enable Pre-RA SSA Destrcution Select the a7v_64 processorHR11_bHR17_bHR17_dHR26_cHR34_aHR40_cHUR3_cHUR4_cIR2IR15IR43IR46IR88R12_bR19_cR32_bR47_aSR2_aSR6_aUAV29UAV57(e)(noprev(abs)vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUPostRAVectorize.cppNumLoopExecuted < 1000 && "Infinite loop?"QGPU::load8sQGPU::load16zNumber of workaround applied for errata A7p140.false && "Attempting to get mul2 opcode for an instruction with no corresponding vairant"NumFullRegs <= QGPU::FullRCRegClass.getNumRegs() && "Invalid full register beyond ISA encoding limit"intCpreamblecl-mad-enableFnRCID != HalfRCID && "HalfRCID must be used in this call"FalseMBB && TrueMBB && "Unexpected pattern while lowering GETONE"MapOpd!QGPURegisterInfo::isConstRegisterClass(getRegClassFor(Op2Reg)) && "cannot use multiple const register in one instruction!"GVI && "cannot compute gv size for oob (no global info)"isLongTypeSizeCI->getZExtValue() <= getTargetFeatures().getUnsignedValue(QV_MAX_HW_SHARED_CONSTANTS_SIZE_IN_BYTES) / sizeof(uint32_t)IIDstReg != DstTempReg && "Temp registers must be used for ldgb result"BaseIDCI && "Wrong operand for BaseID"0 && "Unsupported size for xchg"0 && "Unsupported data type in ldthr"CoordValue.getType()->getScalarSizeInBits() == 32 && "Packed Sample must use full register as coordinate."lm_size.3ddr63.PCreg(nan)rndne.fcat.u16bracbktOpInfoHiBound.isIntImm() && OpInfoLoBound.isIntImm()The dst data type has to be 32-bit float for DSX and DSY!"Only full precision constants expected in DX11 and GLNext"InternalError: . a half-precision float immediateUndefined register class is used.Memoryqgpu-scevqcom-sched-rulepost-sched-adjust-latencyshift > 0 && "Invalid vector type"disable-inout-overlapDestOperand && "DestOperand is Null"MovInst && "MovInst is not initialized"false && "No available registers to map fake registers"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUPreRAMIRVerifier.cppvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUPreRAMIRVerifier.hLR_Real && "Dangling register alias"false && "fail to create instruction"_efalse && "Load address is not a pointer type"llvm.ctpop.i32Print activeEnable reusing stack slotscoalesce-phifalse && "No live interval for PHI destination?"false && "Too many output registers beyond register budget"false && "interval not found"ForRC != FromRC && "expecting different rcs"Register Warning: Use instrs: QGPU Instruction selectionuppf-min-live!MustCast && "non-foldable marked as must-cast"ITex countUsedBarys <= 4 && "Too many barys"PredMBB->succ_size() == 2 LDST: Out of Range Offset with ldx.a+ instruction. Allowed Range is 9 bits, |0 - 511|the ldc instruction should use g with source 0. Usage g[r4.x+32] LDC: for src baseid 6/7 reserved for a6x and aboveLDST: no return atomic allowed only in a7x and aboveLDST: atomic.g.u64 is allowed only in a6x and aboveLDST atomic.*.gen: Only allowed in a6x and above.STIBBLK: vector read length (.vl) value should be between 1 to 16LDIB: src0 not allowed for a6x LDG.k: the ldg.k instruction should use g with source 0. Usage g[r4.x] ALU2 CAT16: dstMod (sat) is not allowedALU3 DP2ACC: Only 32 bit registers allowed.Source Operand Out of Range for 16Bit Unsigned DataType.Allowed Range is 0 - 65535TEXTURE: Relative Addressing not allowed.TEXTURE: Source2, if enabled, for .mode6 and .mode7, Immediate value is only allowed.imagedcl_input_primitive is allowed with GS shader onlyPATCH7PATCH23BUILTIN_OUTPUT%s%d%s%s%s%s%d%sPATCH_CONSTANT_SIZEreadCEILFINSTRCOVU32F16INSTRCOVS16F16INSTRLOADXU8INSTRLOADLU8INSTRLOADPS8INSTRSTLWS16INSTRLOADGBAU4DF32INSTRSTGBUT2DINSTRSTGBA3DINSTRATOMADDGENU32INSTRATOMCMPXCHGGENSOCU32INSTRATOMMINGENSOCS32INSTRATOMINCRGGGPUS32INSTRATOMBSUBGNU32INSTRATOMBANDGNU32INSTRATOMBADDGU321D1LINSTRATOMBAADDGS323D1LINSTRATOMBMINGS32INSTRATOMBANDGU321D1LINSTRATOMBANDGS32INSTRATOMBANDGS323DINSTRATOMBANDGS323D1LINSTRATOMBORGS321D1LINSTRATOMBCMPXGNU321DINSTRATOMBCMPXGS321DINSTRATOMBXCHGGU641DINSTRATOMBXCHGGNU323DINSTRATOMBXCHGGU323DINSTRATOMBDECGS323DINSTRRCPINSTRCONVINSTRSAMP0INSTRATOMCMPXLS32INSTRATOMXORLS32INSTRATOMINCLNGS32INSTRLDIBAU321DRCKINSTRLDIBAU322DINSTRRESFMT2DINSTRSWZU32INSTRSWZF32F16INSTRMOVSF32INSTRMADM32F16F16F32INSTRLDIBUNTYPEDS322DINSTRLDIBTYPEDU321DTRCKINSTRLDIBUNTYPEDU161DINSTRLDIBUNTYPEDF161DRCKINSTRLDIBUNTYPEDF161DTRCKINSTRSTIBUNTYPEDU321DINSTRSTIBUNTYPEDU323DINSTRSTIBUNTYPEDS321DINSTRLDIBBLKLU323DINSTRSTIBS161DINSTRSTIBAF161DINSTRLDIBS162DRCKINSTRLDIBAS163DINSTRATOMINCGENS32INSTRSTIBBLKS322DINSTRGATU32U16INSTRSCTU16F32INSTRSCTU32S16INSTRSCTF32S16INSTRSCTS32F16INSTRGETFIBERIDU16INSTRMM_ENABLESHFLXORW8U32INSTRSHFLUPW4U16INSTRFRAG_TYPEFLOAT16TOKENDCL_CL_DIVIDED_NUM_WORK_GROUPS_TOKENLOG2TOKENDECLARE_VIEWPORTDECLARE_ATTRIBUTES_UAVPREDTARGETATOMGENINSTRLOADGINSTRLDGBLENLDSTIBOFFSETALU2_INSTRMOV_SOURCE_OPERAND0MOV_IMM_VALUE2TEX_INSTR_1_1DCLICBVALTOKENDCLVAL0ALU2: Both the Source Operands can not be IMM ALU2: Out of Range offset in Relatively addressed Source1 Operand. Max Offset value can be 1023MOV/COV: MOVS with optional Lane ID can have src1 as address register a0 onlyMOV/COV: Destination operand of MOV/COV cannot be dummy register other than INVSR instructionLDST: Half GPR not allowed inside Relative addresing mode.STIB.BLK: src0 has to be sGPR or Immediate.binningDescriptorGroupsshaderRegisterUsagePerFiberADRENO_SO_ELEMENTADRENO_PATCHED_ASTC_TEXTURESADRENO_VSDS_OUTPUTSGL_SHADER_DATAADRENO_DESCRIPTOR_GROUPgatherTexturestcsMergedShaderDescmsAttrStridesMAX_TESS_GEN_LEVELMAX_COMBINED_SHADER_OUTPUT_RESOURCESPATCH_TEXTURE_SLOT_BASEOES_TEXTURE_3DSHADER_IO_BLOCKSKHR_BLEND_EQUATION_ADVANCEDARM_FB_FETCH_DEPTH_STENCILMaxGeometryTextureImageUnitsMaxPatchVerticesCompilerChoicespecializationInfoPtrGL_UNSIGNED_INTGL_UNSIGNED_INT_SAMPLER_2D_ARRAYQGL_TEXTURE_1DQGL_TEXTURE_2D_MSQGL_TEXTURE_2D_RECTQGL_TEXTURE_CUBE_ARRAYCOLUMN_MAJOR $TF, YUVMatrixArrayIndex = %d0 && !"Assert Index:[14] Unrecognized symbol type"false && "Assert Index:[40] unexpected symbol type"$TFBuffer3BasePtr32$DisableTransformFeedbackUint32$AtomicCounterStrideUint32$SampleFrequencyControlUint32Tessellation Control Point CountIs 90 or 270 rotation enabled for SPV_KHR_fragment_rate_shadingGeometrydisableDynamicCBCachingenableBindlessTextureForce High Precision:availableConstLimitsBinningshaderCRCllvm.qgpu.dsy.f32llvm.qgpu.umad.i32llvm.qgpu.rsq.f16llvm.qgpu.rsq.f32llvm.qgpu.global.scalar.fset.reg.p0f16.f16llvm.qgpu.global.scalar.alloc.reg.p0f32.p0f32builtInVertexSize <= BUILT_IN_VERTEX_SIZE_SSO!(mCompileData->BindlessData.m_bEnableSingleBindlessBase) && "single bindless base is not supported"uboSizeMDNode != NULL__qcom_BARY_Coordinate_centroidarrayTypeID != NULL && "ID is null"subType && "subType is NULL"false && errorMsg.c_str()mModuleFromFile.get() != NULL && "No loaded module"VH_ && "OpRayQueryGetIntersectionTypeKHR" " is not supported"GV && "GV is expected to be not NULL"offsetNameMDgl_inaliasingGV && "aliasingGV should not be Null here"false && "unknown bary coord usage"mCSData.zeroInitializedRegionOffset != -1inst && "Instruction can't be Null"dyn_cast(dataTy) == nullptr && "HitAttribute has a struct type?"false && "Unable to convert unexpected load type to constant buffer access"(isFloat || isInteger) && "Scalar expected for OpSpecConstant"m_arrayDimensions->size() == 1Globalgl_DrawIDARBgl_LocalInvocationIndexgl_MaxFragmentImageUniformsgl_MaxTessControlUniformComponentsgl_MaxTessEvaluationTextureImageUnitssampler3DisamplerCubeNV12 samplerExternalOESvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/codegen/SymbolManager.cppoldEntryBB->getTerminator() && "Terminator inst is expected."false && "setPatchFragCoordAtMainEntry called on invalid object"castInst && "incompatible casting"baseNode->isArray() || baseNode->isMatrix()0 && "Wrong type for uniform symbol"dest && "dest is Null"is2us2Amaxfaceforward#################### GLSL Source String %d #################### The GPU does not support this version of OpenGL ES, try an older versionearly_fragment_tests is not declared when enable post depth coverage!can't modify gl_ShadingRateEXTcan't modify gl_MaxComputeWorkGroupCountcan't modify gl_MaxComputeAtomicCounterBufferscan't modify gl_MaxVertexAtomicCounterBufferscan't modify gl_MaxTessControlTotalOutputComponentscan't modify gl_MaxTessEvaluationImageUniformsinteger expression requiredNumber of constructor parameters does not match the number of structure fieldscannot convert a samplerUBO/SSBO symbol creation failedDo not support array of array inputinvalid qualifier for parameterlayout(subsampled) is not supported with this sampler type, only supported samplers for ES3.0+ are [i/u]sampler2D, [i/u]sampler2DArray, and samplerExternalOES%d:%dConstruct mat4x4EqualMemoryBarrierImageblockMatchSSDQCOMTest condition and select with expression Equality operators are not allowed on unsized arraysitu_601_full_rangegl_SamplePositionOESDefault Precision Qualifierlayout qualifier 'index' can not be specified without the 'location' qualifier.function return is not matching type:duplicate macro argumentsmust not redefine a macro with different number of argumentsdisable"(" expected after 'optimize' keywordbaseDecoration && "baseDecoration shouldn't be null."operand && "Operand is Null!"$funcfalse && "The atomic opcode is not supported!"hole2OpTypeStructOpConstantNullOpPtrAccessChainOpInBoundsPtrAccessChainOpSDotAccSatKHROpAtomicIDecrementOpAtomicIAddOpBuildNDRangeOpImageSparseSampleProjDrefExplicitLodOpNoLineOpGroupNonUniformLogicalAndOpRayQueryGetIntersectionObjectRayOriginKHRBBTerminator && "Current basic block has NULL terminator."rd.lbaseray$qgpu.misc.const.raylist$qgpu.stable.fb.hitgroupbase.shader.idpush.frameelOffsahit.sdr.idWsizestable.addrhigher.32 (PatchnumWords: [ADRENO_SHADER_UAV_USAGE] (Ver numLoadStoreInst: outputsPosition: [A3X_CLIPPLANE_INFO][instanceCount: inputPrimitive: viewIDVirtualComp: [ADRENO_CS_INPUTS] (Ver [ADRENO_VSDSGS_OUTPUTS][string: wgSizeUGPRIndex: numDynamicTextureMappings: [ADRENO_GATHER_SWIZZLE_PATCHING_INFO] (Ver [ADRENO_PATCHED_GATHER_TEXTURES] (Ver globalScratchSize: precision: [GL_SYMBOL][needsMeshPrimitiveID: ([ADRENO_NAMED_SHADER_HANDLESV2]*) ([ADRENO_BINDLESSBASE_USAGE_INFO]*) bindlessUsage: [ADRENO_DEVICE_ALLOCATION][ADRENO_REGISTER_USAGE_PER_FIBER].preferPerFiberMode.numRegs.primitiveIDRegID.compMasks.patchConstTessFactorSize.inputPrimitive.needsFragCoord.outputsZ.sampleIDRegID.packFactorX.hwShaderSizeWithoutGlueCode.TexSwizzleX.samplerIndices.allocationType.isRestrict.structMemberIndex.samplerSlot.numDimensions.constColorValY.outputTopology.instructionCountN / A - Preamble stats - 3d : %8d - ldiba : %8d,%8d (rpt), ratio %5.2f - getwid : %8d,%8d (rpt), ratio %5.2f - pipc : %8d,%8d (rpt), ratio %5.2f - stgensize : %8d - SY before ei pos: %8d reg_footprinttotal_footprintpost_nop_rpttex.gatherAtex.tcinvtex.sampckmem.ldcmem.l2g_rptmem.stl_rptmem.piprmem.pipc_rptInput component countDriverDataEnableEarlyPreamblePSAALineWidthBGEResourceStrideRelaxExtensionPPCheckRasterizedStreamEnableTessellationBinningRESOURCE_SIGNATURE_INLINE_GPU_ADDRESSshaderStageMaskconst INTERNAL_SPECIALIZATION_VALUESnumStageselementCountError parsing specialization element data: inputAttachmentsoption="Error parsing tf data tag data: Unable to parse EnablePSInputPacking value 'Unable to parse EnableBindlessCBuffer value 'Unable to parse ShaderCRC value 'Unable to parse EnableEndOfLocalMem value 'Unable to parse ABGEData value 'Unable to parse DisableGatherPatching value 'Unable to parse EnableNamedConstBrac value 'Unable to parse ForceHighpOutput value 'Unable to parse IsSSO value 'Unable to parse EnableEmulatedROImage value 'Unable to parse UseMSAARenderTarget value 'Unable to parse EnableTessellationBinning value ' EmulateSBufUAVAsRaw (false): emulate structured buffer UAV as raw buffer GLIRShader (__null): GL IR Shader to link ForcePerWavePvtMemLayout (false): True: use per wave layout for private memory, overriding compiler default BGEResourceStride (0): How many bytes between UAV/CB/Texture bindless elements ForceHighpUniform (false): Force shader uniform variables to use high precision EnableEmulatedROImage (false): allow emulation for read-only usage of read-write textures (Image) {tab}Expected at least 1 dword for CSizedBuf value. A730 A330 A530 A740 structureName=",DS:0xUnable to allocate shader code, overflow in calculating shader size. Invalid initial texture texture ID, error in compiler-generated metadata. Invalid initial texture bary coordinate, error in compiler-generated metadata. Need to generate default structure for mesh vertex shader. Version 1.0: Added virtualRegIDMask: mask for correspoding virtual register IDs Added bufferIndex: Buffer index for transform feedback Added bufferOffset: Buffer offset for transform feedback Data describing barycentric coordinate inputs used by the PS. Version 1.0: Added ijUsageMask: Mask of which i/j components are used. Added numIjRegIDs: Number of potentially used register IDs. Added ijRegIDs: Array of register IDs for each i/j < NumIjRegs, 0 if no register used Data describing special inputs needed by the PS for A4x. Version 1.0: Added needsCenterW: True if the shader uses pull-model evaluation. Added needsCoverageMask: True if the shader needs a coverage mask input. Added needsSampleID: True if the shader needs a SampleID input. Added centerWRegID: Scalar full precision register ID for center W component. Added coverageMaskRegID: Scalar full precision register ID for coverage mask input. Added sampleIDRegID: Scalar half precision register ID for sample ID. Data describing special inputs for the CS. If the WGId, WorkgroupSize, or GlobalOffset are not used, they will be set to the same value as the ScratchVec4ConstID. This can be used for constants that the CS does not need (only needed for OpenCL). Version 1.0: Added localIdRegID: Where to store the group thread ID. Added scratchVec4ConstID: Unused constant location used for scratch. Added wgIdConstID: The constant ID for the thread group. Added workgroupSizeConstID: Where to store the size of the thread group (unused currently). Added globalOffsetConstID: Where to store the offset of the thread group (unused currently). Version 1.1: Added localLinearIdRegID: Where to store the local linear ID. This includes all information about binning input. mainly used when single command stream is enable. Version 1.0: Added totalBinAttributes: number of total binning used attributes. Warning: thread was already assigned a context. alertNAKnineREG_BADPATREG_EESCAPEarmv7-pc-linux-gnueabi.vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Support/ThreadLocal.cpp=<) : CommandLine Error: Argument 'USAGE: DW_TAG_variantDW_TAG_common_blockDW_TAG_try_blockDW_TAG_auto_variableDW_LANG_D --User+System--ppcLevel != 0 && "Cannot move the root node"BufLinear = !{ arm_apcscc unorderedglobal signext sspreq Ty && "Null argument to getAllOnesValue"/domtreellvm.arm.neon.vqrshiftullvm.arm.neon.vrshiftullvm.arm.neon.vsubhnllvm.atomic.load.maxllvm.dbg.valuellvm.hexagon.A2.vaddwsllvm.hexagon.A2.vcmpwgtllvm.hexagon.C2.muxllvm.hexagon.C4.and.ornllvm.hexagon.F2.conv.sf2udllvm.hexagon.F2.conv.ud2dfllvm.hexagon.F2.dfcmpeqllvm.hexagon.F2.sfcmpuollvm.hexagon.F2.sffma.libllvm.hexagon.M2.mmaculs.rs1llvm.hexagon.M2.mpy.acc.sat.ll.s0llvm.hexagon.M2.mpy.nac.sat.lh.s0llvm.hexagon.M2.mpyu.nac.hh.s0llvm.hexagon.M2.mpyu.nac.lh.s0llvm.hexagon.M2.mpyud.ll.s1llvm.hexagon.M2.vmac2su.s0llvm.hexagon.S2.asl.i.p.andllvm.hexagon.S2.asr.i.p.andllvm.hexagon.S2.asr.r.r.satllvm.hexagon.S2.asr.r.vwllvm.hexagon.S2.lsr.i.r.accllvm.hexagon.S2.lsr.r.p.andllvm.hexagon.S2.togglebit.illvm.hexagon.S2.vsatwuh.nopackllvm.hexagon.S2.vtrunehbllvm.hexagon.S4.addi.asl.rillvm.hexagon.S4.clbaddillvm.hexagon.S4.lslillvm.init.trampolinellvm.opencl.get.global.idllvm.opencl.get.image.channel.data.type1llvm.opencl.get.image.dim2llvm.opencl.get.image.width1llvm.opencl.read.image2llvm.opencl.read.image.no.sampler.2allvm.opencl.write.image2allvm.powillvm.ppc.altivec.vmhraddshsllvm.ppc.altivec.vmuleubllvm.ptx.bar.syncllvm.ptx.read.ctaid.xllvm.ptx.read.lanemask.gtllvm.qcom.s162f32llvm.qgpu.atomic.op.uavllvm.qgpu.fcombine10llvm.qgpu.fcombine48llvm.qgpu.fcreate.map64llvm.qgpu.fwrite.temp.regsllvm.qgpu.get.yield.restore.func.stack.sizellvm.qgpu.icombine18llvm.qgpu.icombine38llvm.qgpu.icombine45llvm.qgpu.icombine53llvm.qgpu.icreate.map22llvm.qgpu.icreate.map24llvm.qgpu.icreate.map47llvm.qgpu.ldx.add.stxllvm.qgpu.noptr.ldckllvm.qgpu.setup.bary.derivativesllvm.qgpu.subgroup.fquadswapllvm.qgpu.umaxllvm.qgpu.umul16llvm.spu.si.bgxllvm.spu.si.mpysllvm.spu.si.sfllvm.sqrtllvm.ssub.with.overflowllvm.x86.3dnowa.pswapdllvm.x86.avx2.phadd.swllvm.x86.avx2.psll.qllvm.x86.avx2.psrli.dllvm.x86.avx.hadd.ps.256llvm.x86.avx.movnt.ps.256llvm.x86.avx.vperm2f128.ps.256llvm.x86.fma4.vfnmsub.ps.256llvm.x86.sse2.comilt.sdllvm.x86.sse41.pmovsxwdllvm.x86.sse.add.ssllvm.x86.sse.cvtpi2pdllvm.x86.sse.div.ssllvm.x86.ssse3.phadd.dllvm.x86.vcvtph2ps.128llvm.x86.xop.vpcomfalseuwllvm.x86.xop.vpcomgeuwllvm.x86.xop.vphsubdqllvm.xcore.setcinttoptricmpshlPrint IR after each passlist'. AGI.Implementations.count(ImplementationInfo) == 0 && "Cannot add a pass to the same analysis group more than once!"ImplementationInfo->getNormalCtor() && "Cannot specify pass as default if it does not have a default ctor"getSubclassData() == val && "Subclass data too large for field"Entry block to function must not have predecessors!Instruction has a name, but provides a void value!Allocation instruction pointer not in the generic address space!Range must not be empty!SIToFP source must be integer or integer vectorBitcast requires types of same widthInvalid predicate in ICmp instruction!invalid arguments to llvm.prefetchAliasing chain should end with function or global variable.code16 .hidden .reference .sleb128 .seh_pushframeSPersonality Encoding.text.bssGOT_OFST__debug_pubnames.dtors,#tlsEmit data into separate sectionscopysignfcoshlogftanhlllvm.loop.unroll.partialNo aliasMay alias: Ptr: call sites mod & ref responses No access basicaa}"]; ; Print dominance tree of function to 'dot' file (with no function bodies)Number of mad intrinsicsNumber of SRem insts ScalarNumber of LShr instsinstsimplifyintervalsUndefined result: Shift count out of rangeSubprogram: path-profile-early-terminationWARNING: profile information is inconsistent with Print regions of function to 'dot' file (with no function bodies) * /u *GTI && "GTI is Null"mAddrSpaceToSymbolMD && "Missing metadata"Number of live out of a loop variablesTI && "Terminator inst is expected"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/LoopSimplify.cppllvm.sjljeh.jblistNumber of registers live across unwind edgesvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cppNew code to generate select instructions more aggressivelyinfloopindvarsUnifiedUnreachableBlock_wrapNextBBGLNext - propagate safe math (invariant/precise) globallySROA_IsConstantbb36-vectorize-no-bitmanipbb36-vectorize-fast-depidxscaleLHS && "LHS is NULL"RHS && "RHS is NULL"Number of instructions CSE'dDepSI &&"DepSI is Null"range_infolftr.wideiv.threadNumber of instructions hoisted out of loopUnroll loops with run-time trip countsvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp.negscalarreplNumber of allocas copied from constant globalfalse && "unexpected instruction in constant access list."Control Flow OptimizerMachineCopyPropagation should be run after register allocation!LD:[regdef-ecRegOpMustVecmachine-gchMachine Natural Loop Construction- instruction: Two-address instruction operands must be identicalLive range continues after kill flag *** Final LLVM Code input to ISel *** Number of pipeline stallsprologepilogDefaultgreedy register allocatorNumGlobalIntvs && "No global intervals configured"false && "Must have a defining instruction"TargetRegisterInfo::isVirtualRegister(VReg) && "A physical register is already assigned"gc_currheadgc_root__gc_exn_valMI && "enterIntvAfter called with invalid index"MI && "No instruction at index"stackcoloringvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/StrongPHIElimination.cpp extra input from predecessor BB#Number of tail duplicated blocksdisable-sched-heightConstantTargetBlockAddressumul_lohirotlvselectsetoEnable abort calls when "fast" instruction failsAllow promotion of integer vector element types__ashrdi3__floatunsidf__floatuntisf__gtsf2__sync_fetch_and_add_8__sync_fetch_and_and_8arm-enable-ehabi-descriptorscamlMalformed block recordinvalid type in struct typeInvalid FLOAT recordInvalid constant reference!Invalid PHI recordInvalid CALL recordBitcode stream must be at least 16 bytes in lengthmax fold cost for if conversionlodVec->getType()->isVectorTy()samImmIDRNDRTEModeC0_dHR1_aHR8_bHR15_cHR23_aHR39_dIR106IR112R2_aR12_aR25_bR44_cSR1_bSR7_dUAV42UAV56UR1_cUR4_d nop;(sat)(shr)Repeat or nop number too high.QGPU::move.f32QGPU::FCMPltQGPU::bsel16!(TBB == nullptr && FBB == nullptr)FDT && "Dominator analysis is not valid."Opcode != QGPU::GETONE && "can't remove getone"(Dim < 3) && "invalid dim"NumDefs != NumOperands-2 && "No asm string?"(IClass == QIC_ALU3) && "Not ALU3 instructions"false && "dbgIntrinsic should not be NULL"false && "invalid origOpd"numConstUsed <= QGPUTTI::getConstRegLimitInVec4(M) || (UsedConstRegBefore && TotalConstants == UsedConstRegBefore) && "Exceed const reg budget"TI && TI->getNumSuccessors() == 1 && "preamble has more than one successor?"false && "UGPR limit reached"qgpu.constant_store.ldc.usedno-reg-spillfalse && "Unexpected parameter to get.reg intrinsic"(EVI->getNumIndices() == 1) && "Invalid ExtractValue inst"Src1Reg && "Shuffle offset is not present"DataType->isVectorTy() && "Data should be in vector type"DstReg && PredReg && "bad registers for branch intrinsic"(II->getIntrinsicID() == Intrinsic::qgpu_preamble_begin) && II->hasOneUse()Op2 && "Const int expected in pipe.reserve"0 && "Unsupported data type in Ldx"Check && "Couldn't determine the address mode"IndexValuefalse && "Invalid GATHER opcode".pcmngetOperand(1).isMBB() && "PREDT/F target is not MBB!"The returned data type has to be 16-bit unsigned integer for GETSIZE and GETINFOarraySize <= 1ty->isIntOrIntVectorTy() && "unsupported data type for cl image to buffer"KernelFn != NULL && "Cannot find kernel function"false && "getAllowedMods: unsupported instr class"Register or immediateIf src0 and src2 are constant regs, no relative addressing on bothTextureRC == MRI->getRegClass(SrcReg) && "Inconsistent register class": # of regs is MI opcode Stack pointerAll registersgroup-sizeBackward DAG schedule found %d! %d, %d SU && "SU is NULL!"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUIselPrepare.cpplastReg != TailReg && "invalid CVTr chain"RC && "could not retrieve the rc"!isUGPR || (isUGPR && isSGPR) && "isSGPR must true if iUGPR is true"!is64bit && "unexpected"Static verifier for single poolinsertLoc != NULL && "first block is neither preamble nor main shader entry"neg_flag0 && "Unexpected instruction for emulateCmpxchg"false && "invalid orgInstVecTy"Use TSort Algorithm for Sorting BasicBlock OrderSrcLI && "findLiveInterval fails"LI->getLength() != 0 && "zero-length interval is not allowed"LIs[0] == LI_Cur && "Unexpected live interval."LI->endSlotIdx() > SplitSlotIdx && "Interval doesn't exist at the current slot"VecVRegs.size() > 1 && "Checking only vector registers"FrameIdx == InvalidFrameIndex && "FrameIdx is already assigned"Number of register hint warningsQGPU LM Spiller passvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUInstructionSelector.cppUse count for def to be considered for promotionEnables bc->mir uniformity propagationLocalMI && "No DefMI"false && "Unexpected ISA texture opcode"Sorted[i]->succ_size() == 2 LDST: Out of Range Offset with ldg instruction. Allowed Range is 13bits, |0 - 8191|LDIB: For stg.a Source1 should always be Immediate Value LDST: Out of Range Offset with stthr.a instruction. Allowed Range is 13bits, |0 - 8191|the stthr instruction should use g with dst. Usage g[r4.x+32] RESINFO/RESFMT/RESBASE/RESLAYOUT: need mode/baseID for a6x+ STIBBLK: for src baseid 5 is only for src mode 5/6 for a6x and aboveLDIB: for src mode0/4 src2 should be IMM for a6x and aboveLDIB: for src baseid 6/7 reserved for a4x and belowALU3 DP2ACC: Only Src0 can be CONSTTEXTURE: Source2, if enabled on A7x, for .mode0 and .mode4, 16bit GPR/sGPR is only allowed.PATCH1PATCH32OUTPUT_TRIANGLE_CWPOSITION_CENTER_WTESSELLATION_CONTROL_POINTS_LOCATIONTESSELLATION_CONTROL_POINTS_LOCATION_64BITFLATTEX1DACOVU16F32INSTRCOVU32S32INSTRGETSIZEINSTRLOADGAF16INSTRLOADPF16INSTRSTGENU16INSTRSTTHRAU16INSTRSTXU32INSTRSTPS32INSTRL2GS16INSTRUAV_UNTYPED_2D_TOKSTGBUT1DTYPEINSTRALIAS_I16STGB1DTYPEINSTRLOADGBU4DS32INSTRLOADLVUPINSTRBKTINSTRATOMORGENSOCS32INSTRATOMSUBGSOCS32INSTRATOMXCHGGSOCS32INSTRATOMCMPXCHGGGPUU64INSTRATOMMINGGPUS32INSTRATOMANDGGPUS32INSTRATOMORGGPUS32INSTRATOMBSUBGNU322DINSTRATOMBMAXGNU323DINSTRATOMBADDGU322DINSTRATOMBADDGS322DINSTRATOMBSUBGS322DINSTRATOMBASUBGS323DINSTRATOMBAMINGS323DINSTRATOMBORGS321DINSTRATOMBAORGS321D1LINSTRATOMBAXORGU323D1LINSTRATOMBCMPXGNU322DINSTRATOMBCMPXGU642D1LINSTRATOMBXCHGGS321D1LINSTRATOMBAXCHGGF322DINSTRATOMBAXCHGGF322D1LINSTRATOMBAINCLNGU322DINSTRATOMBDECGU322DINSTRATOMBDECLNGS322D1LINSTRATOMBADECRGGU32INSTRISAMMNSTRDSXOKENATOMCMPXGS32INSTRSTIU32INSTRBFREVBINSTRCBITSBINSTRLDIBU323DINSTRLDIBF321DTRCKINSTRSHLM16INSTRSWZS32F32INSTRSWZS32S16INSTRMOVSU16U32INSTRLDIBUNTYPEDS161DINSTRLDIBUNTYPEDF161DINSTRLDIBUNTYPEDS161DTRCKINSTRLDIBUNTYPEDF163DRCKINSTRLDIBUNTYPEDS163DRCKINSTRSTIBUNTYPEDS322DINSTRLDIBBLKLS162DINSTRSTIBU161DTINSTRSTIBS163DINSTRLDIBF161DTINSTRLDIBAF161DRCKINSTRGATU8S32INSTRGATS32F16INSTRSCTF16U16INSTRIMGINSTRSHFLDOWNINSTRSHFLDOWNU32INSTRSHFLGENU16INSTRVERTEX_TYPELBRACESAMPLE_REGISTERGLOBAL_COHERENT_TOKENDECLARE_TESS_PARTDEC_CONST_VECTORFLOW_DST_MODIFIERLDIBINSTRSTGINSTRCLZINSTRSHLINSTRMADSHINSTRMOV_SOURCE_MODIFER2DESTINATION_MODIFIERDCL_SYMB_LABELsyntax error, unexpected %s, expecting %sALU1/2: Destination operand of ALU1/2 cannot be mailbox.ALU3: last-use-if-source-is-a-GPR is allowed only for src0 and src2 Out of Range offset in Relatively addressed Destination Operand. Max Offset value can be 255FLOW: Float values not supported with Flow instructions.glueCodeDesc_A4xuavDescFormatADRENO_SHADER_DEVICE_ALLOCATIONSADRENO_NAMED_SHADER_HANDLESADRENO_INPUT_SYMBOLSADRENO_DS_INPUTSADRENO_SHADER_DEBUG_INFOtesMergedShaderDescUniformPatch_InputYUV_TARGETQCOM_render_pass_image_attachmentsEXT_fragment_shading_rateMaxVertexTextureImageUnitsMaxDualSourceDrawBuffersEXTMaxTextureImageUnitsMaxTessControlOutputComponentsMaxTessGenLevelGL_INT_SAMPLER_2D_MS_ARRAYGL_BUFFER_BLOCKQGL_INT_TEXTURE_2D_MS_ARRAYQGL_TEXTURE_CUBE_ARRAY_SHADOWGL_INT_IMAGE_1D_ARRAYRGBA8IRGBA32UI perPatch, coherent, hasLocationQual, offset = %d type mismatch with other stage.val && "Assert Index:[44] val is Null"$TextureFovSubsampledScaleFactor$SubpassFragCoordFovScaleFactorVec2ArrayTessellation Patch Data Base Pointer (64-bit)Transform Feedback Buffer 3 Base Pointer (32-bit)Offset of gl_vertexID in non-drawIndex modeAn array of scale factors for subpass frag coord fov patchingsetRegInst && "Assert Index:[35] missing setReg src values"Taskdisable-safe-fast-mathenableLocalMemorySpillenableSampleShadingenableConstColorBypassenableA7pAliasapiTypeavailableConstLimitsdumpShaderOptions.bcllvm.qgpu.imax.i32false && "Unexpected output found."__qcom_is_HelperInvocation(totalSize >= 1) && "array must contain at least one element"srcTy->getStructNumElements() == dstTy->getStructNumElements()vRelPatchIdgetHitT!"Unsupported matrix size"(memberCount == srcCount) && "missing struct member value"ldib_v4i32get_intersection_instance_custom_indexTraceRayv12$setupBaryN_j_slope_dxqgpu.zeroiinitialized.symbolvView && "vView is Null"(channelIndex < coordSize) && "barycoord has two channles"(cst.encoding != QGLC_COLORSPACE_ENCODING_LAST) && "cst encoding enum is not valid"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/codegen/LowerNamedPointers.cppmCSData.reqdGroupSizeIntrinsics && mCSData.reqdGroupSizeIntrinsics->getNextNode()loadInst || intriniscInstfalse && "addrSpace doesn't match between dyn index instrinsic and its usr"FogBlendTessCoordgl_MaxCombinedAtomicCountersgl_MaxComputeUniformComponentsgl_MaxVertexAtomicCounterBuffersgl_MaxTessControlCounterBufferssampler2DArraytextureCubeArrayimage2DMSArrayimage1DArrayfalse && "GetFSInfo called on invalid object"false && "setGlobalGSInfo called on invalid object"false && "unexpected binary operator"!isSrcRowMajorgl_PointCoord0 && "Default Uniform Buffer is changed to Uniform Buffer!"false && "unknown GLSL internal constant qualifier"blendme && me->getSymbolPointer()mSymbolManager->getNextSampler() == (unsigned)slotOffsetsubType->isSampler()$unpatchedFragCoordsrcSym && srcSym->GetType().isArray()active uniform symbol contained element is NULLisM2AusM2Aimgbuimg2aedge1frexplengthtextureProjGraddefine l-value requiredcan't write gl_FragData or gl_SecondaryFragDataEXT while gl_FragColor or gl_SecondaryFragColorEXThas been written"%s" (%s)(%s) assigning non-constant tofalse && "Unable to get thread local parser pointer"gl_PerVertex declared after useWrong UBO/SSBO member type qualifierinoutType->getArrayDimensions()->size() == 1 && "inout cannot be multi-dim"samplerName && "NewPoolTString returns Null"i != opaquePrecisions.end() && i->second != __null && i->second->size() > 00 && "unknown qualifier category"GL_ARB_geometry_shader4GL_EXT_fragment_shading_rate!"wrong vector size"Sub -Least significant bitarc tangentTexture2dProjLodImageLoadCubeImageStoreBufferImageStoreCubeImageAtomicAndtrue case is null %d (%s)referenceTexturememoryBarrierImagemethods are not supportedvertex spacing already specified and it is not fractional_even_spacingSAMPLERSHADOW is for Vulkan api onlyTEXTURE1DARRAYUnsigned integer overflow: #definemust not redefine a macro with different arguments#elif after an #else")" expected to end 'optimize' pragmaexecutionMode == ExecutionMode::ExecutionModeLocalSizeId && "Non ExecutionModeLocalSizeId not supported"resultDataTypeMap[id]->isPointer() && "expect a pointer operand"false && "OpCopyLogical with different types "symLLVMType && "result type is expected"OpExtensionOpTransposeOpFAddOpDPdxFineOpFwidthFineOpGroupFMinOpReservedReadPipeOpCommitReadPipeOpDecorateIdOpGroupNonUniformBitwiseXorOpRayQueryGetIntersectionTypeKHROpRayQueryGetWorldRayDirectionKHRError: Input Output Mismatch. <rd.lbasecommitted$qgpu.misc.const.pipelinestate$qgpu.misc.const.cachestatethridisAtEntrycalledFunc->getReturnType() == Type::getVoidTy(call->getContext()) && "Continuations with returns not supported"attrSizeCATasptr.phiaddrVal != NULLcallable.shader.idsubstaterd.asp.lo (Half) (Center (0,0)) (Float16) (Sampler+Texture) (D3DTPCB) (TessPatchBuf)numConstantBufferCacheEntries: interplMode: [ADRENO_DS_DESC] (Ver needsSampleIDIfMSAA: fragCoordRegID: needsCoverageMask: localLinearIdRegID: [ADRENO_GS_PER_STREAM_OUTPUTS] (Ver wgIDUGPRIndex: dynamicTextureMappings: is8BitIntWA: samplerIndex: refValue: bindlessVertexSupport: objData: 0x[ADRENO_VSDS_OUTPUTS] (Ver [ADRENO_INPUT_TARGET_DATA] (Ver inputTargetInfo[[ADRENO_STEREO_RENDERING_INFO] (Ver [ADRENO_COLOR_SPACE_CONVERSION_INFO] (Ver disableInstancePacking: hasEarlyPreamble: namedConstInfo: isReadOnly: isCoherent: bindlessSamplerOffset: unsizedArrayIndex: shaderSize: [ADRENO_MS_VPCPASSTHRU] (Ver [SMALL_BITMASK].usesSingleRegisterPool.fpDominate.numLoadStoreInst.vertexIDRegID.zrhWRegID.ijUsageMask[STRING].virtualRegisterComponent.rasterizedStream.totalBinAttributes.shaderSize.readwriteMask[ADRENO_SCREEN_COORD_TEX_USAGE]TCSUnrecognized Arch for dumping support.NumInstructions.ApplicationTypeNo return metadata pointer specified VertexShader - Bary Inputs : %8d,%8d (rpt), ratio %5.2f - idx : %8d - ldgen : %8d,%8d (rpt), ratio %5.2f ei_pos - PREDE Instrs : %8d num_of_input_componentsmem.ldckmem.ldlv_rptComplex instruction countDX11ShaderBinaryAvailableConstLimitsForcePerWavePvtMemLayoutDisableGSExitForUAVWritesBGESlotTypePtrDisableRotationWASizeOfFoveatedBinDataEnableWarningsTFDataNamePtrAuxBindGroupElementsnumRootConstantspRootConstantspRootSRVsStageelementOffsetauxDescSetOffsetfragData Unable to parse OptLevel value 'Unable to parse DisableDynamicCBCaching value 'Unable to parse GLShaderVersion value 'Unable to parse EnableWorkGroupLikeVSHS value 'Unable to parse EnableSWViewMask value 'Unable to parse BGESamplerStride value 'Unable to parse ConstantRAMMode value 'Unable to parse DisableDummyNonperspectiveIJPatching value 'Unable to parse SubgroupSizeMode value 'Unable to parse ErrataNumber value ' EnablePSInputPacking (false): Enable compression of PS inputs to reduce VPC component size EnableEarlyPreamble (false): Enable per-shader early preamble DX11ShaderBinary (__null): DX11 Shader Binary to compile SpecializationSize (0): Size of the bind group element structure stride EnableAlphaToCoverage (false): Enable Alpha to Coverage in PS EnableA6xInstancePacking (false): (a6x+) enable instance packing. ConstantRangeDriverAssigned (false): Disable compiler-based allocation of constant RAM EnableAllResourcesBound (true): Enable codgen for all resource bound case, otherwise prevent CB load from being pulled out of CFG BinningAvailableConstLimits (0): How many constant registers are available for binning ForceRotationAll (false): Force GL rotation RasterizedStream (0): which stream goes to the rasterization stage EnableResUsageInfo (): Enable resource usage info A418A640 A508 " size=" count="No InitialTexture Meta Unable to get Stream out entry. Version 1.0: Added YUVIndex: Indicate index of YUV matrix array for samplerExternalOES Added fbFetchMask: frame buffer fetch mask Contains information about which descriptors are used in Binning Stages Version 1.0: Added numDescriptorGroupsInRendering: num of Descriptor groups Added renderingDescriptorGroups Added numDescriptorGroupsInBinning: num of Descriptor groups Added binningDescriptorGroups Gives information about all shaders in a collection. Version 1.0: Added numShaders: How many substates are created for the shader Added shaders: Per-shader information Multiple threads entering the same context simultaneously. DLECANpercent-signzeroREG_NOMATCHREG_ASSERThiBitsSet <= numBits && "Too many bits to set!"DW_TAG_labelDW_ATE_imaginary_floatvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Support/ErrorHandling.cpp%9lld Total Execution Time: aurorauxnetbsdElements + Grow <= Nodes * Capacity && "Not enough room for elements"Position <= Elements && "Invalid position"FovSampled!"isa(Val) && "cast() argument of incompatible type!"nulldeplibs = [ {} filter , align ogtune umax No predecessors!declare x86_fastcallcc ptx_kernel ; [ DW_TAG_user_base ]has_kek_enqueue_queue_ vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/VMCore/ConstantFold.cppprint-fullpath [__private] elements]Enable optimization remarks from passes whose name match the given regular expressionsrcloc[llvm.arm.cdpllvm.arm.neon.vabsllvm.arm.neon.vst3llvm.atomic.cmp.swapllvm.hexagon.A2.addpsatllvm.hexagon.A2.swizllvm.hexagon.A2.sxtwllvm.hexagon.A2.vmaxbllvm.hexagon.A2.vmaxuwllvm.hexagon.A2.vminuhllvm.hexagon.A2.vnavghllvm.hexagon.A2.vsubhllvm.hexagon.A2.vsububllvm.hexagon.A4.combineirllvm.hexagon.A4.tlbmatchllvm.hexagon.A4.vcmpbgtillvm.hexagon.A4.vrmaxuwllvm.hexagon.C2.bitsclrillvm.hexagon.C2.notllvm.hexagon.C2.orllvm.hexagon.C4.and.andnllvm.hexagon.F2.conv.d2sfllvm.hexagon.F2.sfmaxllvm.hexagon.M2.cmacr.s0llvm.hexagon.M2.cmpys.s1llvm.hexagon.M2.cnacsc.s1llvm.hexagon.M2.dpmpyuu.s0llvm.hexagon.M2.mmpyuh.rs0llvm.hexagon.M2.mpy.acc.hh.s1llvm.hexagon.M2.mpy.hh.s1llvm.hexagon.M2.mpy.nac.hl.s1llvm.hexagon.M2.mpyu.nac.hl.s1llvm.hexagon.M2.vmpy2su.s0llvm.hexagon.M2.vrcmacr.s0cllvm.hexagon.M4.xor.andllvm.hexagon.M4.xor.xaccllvm.hexagon.M5.vdmpybsullvm.hexagon.S2.asl.i.r.nacllvm.hexagon.S2.brevpllvm.hexagon.S2.cl0llvm.hexagon.S2.insert.rpllvm.hexagon.S2.insertp.rpllvm.hexagon.S2.lfspllvm.hexagon.S4.parityllvm.hexagon.S5.asrhub.rnd.sat.goodsyntaxllvm.opencl.get.image.array.size2allvm.opencl.get.work.dimllvm.ppc.altivec.lvehxllvm.ppc.altivec.vpkshusllvm.ppc.altivec.vpkswssllvm.ppc.altivec.vpkuhusllvm.ppc.altivec.vsubuhsllvm.qcom.f162u16llvm.qcom.read.mem.fencellvm.qcom.u162s32llvm.qgpu.banyllvm.qgpu.dp3llvm.qgpu.fcombine24llvm.qgpu.fcombine39llvm.qgpu.fcombine59llvm.qgpu.fcombine63llvm.qgpu.fcreate.map12llvm.qgpu.fcreate.map37llvm.qgpu.fcreate.map4llvm.qgpu.fcreate.map41llvm.qgpu.fcreate.map53llvm.qgpu.get.printf.buffer.regllvm.qgpu.get.sampler.valuellvm.qgpu.gpu.ex.lock.ptrllvm.qgpu.iadd.satllvm.qgpu.icombine28llvm.qgpu.icreate.map15llvm.qgpu.icreate.map31llvm.qgpu.icreate.map5llvm.qgpu.image.atomicsllvm.qgpu.ldckllvm.qgpu.pireducellvm.qgpu.shlgllvm.qgpu.stlwllvm.qgpu.usub.shrllvm.qgpu.vkptr.get.binding.setllvm.returnaddressllvm.spu.si.andcllvm.spu.si.cgtillvm.spu.si.fallvm.x86.aesni.aesdeclastllvm.x86.avx2.psra.dllvm.x86.avx.cvt.pd2.ps.256llvm.x86.avx.max.ps.256llvm.x86.fma4.vfmadd.psllvm.x86.fma4.vfmaddsub.ps.256llvm.x86.fma4.vfmsubadd.psllvm.x86.mmx.psubs.wllvm.x86.sse2.storeu.pdllvm.x86.sse.storeu.psllvm.x86.sse.sub.ssllvm.x86.xop.vpcomgtbllvm.x86.xop.vpcomnebllvm.x86.xop.vpshaqllvm.xcore.setptllvm.xcore.zexturemgetelementptrcallextractelement Print PassManager debugging informationppcf128Function context does not match Module context!Invoke result not available in the unwind destination!Atomic load must specify explicit alignmentStore operand must be a pointer.cmpxchg instructions failure argument shall be no stronger than the success argumentzext source and destination must both be a vector or neitherPHI node operands are not the same type as the result!isvolatile argument of memory intrinsics must be a constant intllvm.stackprotector parameter #2 must resolve to an alloca.Invalid insertelement operands!.symtab_shndxFK_PCRel_1#APP .internal .weak_definition .cfi_personality .seh_savereg unable to evaluate offset for variable 'Augmentation Size>>TLSGDReg:__textcoal_nt.debug_aranges,#allocS_ATTR_NO_DEAD_STRIPAvailable CPUs for this target: ceillfabsfroundtanlqgpu.raygen.shader Total Alias Queries Performed % Total Mod/Ref Queries Performed <-> may alias responses AA use debuggerPrint CFG of function to 'dot' file (with no function bodies)Number of Invoke instsNumber of non-external functionsNumber of Add instsNumber of GetElementPtr insts ScalarNumber of UIToFP instsNumber of PHI instsda-delinearizeNumber of distinct dependence pairs analysed} End region tree (trunc offsetof( Exits: Enable instruction uniformity analysisBB && "Missing BB in PHI Node?"Branch Probability Analysislpad.phipreserve_cfgMake the -lowerinvoke pass insert expensive, but correct, EH codejblinkop && "insertedValue Operand is Null".val.fpSavedBackedgeSrces != NULLOuterLoopPreHeader && "OuterLoopPreHeader is NULL"AllocaArrayLoop Strength Reductionenable-nimbus2-unroll-watxgepseparate-const-offset-from-gepenable-tail-mergeview-edge-bundlesNumber of diamond if-conversions performedNumber of true blocks of diamonds unpredicated-phidefi <= Size && Size <= N && "Invalid index"BBMachineDominator Tree Construction# Machine code for function MMI && "MMI not around yet??"(tbaa=SubIdx && "This is not a subregister index" @[ machinelicmmachine-sinkExtra explicit operand on non-variadic instructionPost RA top-down list latency schedulerVerify during register allocationLocal SplittingAfter splitting live range around regionqgpu-drop-vector-until-cascadejoin-physregsverify-coalescingAfter register coalescingcall_sitestack-protector missing input from predecessor BB#Number of phis addedNumber of insts selected by target-specific selectorvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cppDisable scheduled-height priority in sched=list-ilpConstantSize && "AlwaysInline requires a constant size!"Generate low-precision inline sequences for some float libcalls<getOpcode() == QGPU::PREFETCH || LDSTInstrInfo::isPipeCommit(*MI) || LDSTInstrInfo::isStibBlk(MI->getOpcode())(IClass == QIC_ALU2) && "Not ALU2 instructions"llvm.qgpu.false && "invalid orgCallee"node [color=black]; StartAddr == 0 && "StartAddr(Offset) is hard coded to 0 during Metadata generation"ldcInst && "ldcInst argument null !"SharedConstantsOffset != UINT_MAX && "Shared constants offset not found?"CBIdentifyMD->getOperand(1) && isa(CBIdentifyMD->getOperand(1)) && "incorrect MD layout"PreambleEndMBB->succ_size() == 1 && " Multiple succesors to SHPE ? "[Warning] double wavesize mode is used since HW limitation, FE hint is ignored. Info->AllocReg != NULL && "No metadata generated for symbol"mod && "Error getting module in GenericToGlobal conversion"MemType && "memory type is expected."!(IsHalf && srcModVal) && "Op2 for UCAT16rr must be 0"false && "both operands should be immediates"__qcom_internal_yield_save!DestVT.isVector() && "No vector support".brcst.pack4SSD.socmul.f.div2add.f.div2cbits.brsqldc.uaddress register can't be src operand in direct addressingTexBaseID < 5 && SamBaseID < 5 && "BaseID must be 0-4"false && "SHPS must be first instruction"Register ID '&' must with a variable.qgpu_streamout_ele$vpc[it != PgmScpVarOverallInfo.GlobalVarToIndexMap.end() && "GlobalVariable not found"false && "back-end instruction validation failed"Undefined imm type found.SImmRangeError: LMBroadcastOffsetRangeError: InvalidTexDstMask: Expected Half RegisterOnly P0 is allowedDMOD.SATChoose scheduling directionBwd0 && "should be virtual regs (pre-ra)"enable-combine-aware-dcefalse && "Wrong const vector types"Func && "Function Func is Null"PreambleMBB != NULL && "Failed to get/create preamble section!"false && "info_assert"'s vector's member enable single pool register allocation for 64 fibersvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUXfrGraph.cpp_carry_on_bitsfalse && "wrong instrinsic!"false && "Cannot emulate a scalar instruction"hiHint.first == QGPURI::RegPref && "RegPref is expected"false && "No live interval?"RegCount>0 && "bad count"Number of register hint errorsQGPU Vector Hint SettingBreak mayvec reg hintsTolerance of bad targets (0..100)uppf-phiShadowMap(.s) option not allowed for conv instruction.LinearMode(.l) option allowed only for gather4x instruction.the ldg instruction should use g with source 0. Usage g[r4.x+32] LDC: ldc.k needed if destination is c[a1.x].LDGB: LDGB length is out of range. Allowed range for UNTYPED UAV is 2 bits, |1 - 4|.the stgb.a instruction not allowed in a6x and above LDST: Destination Offset out of Range with g2l instruction. Allowed Range is 13bits, |0 - 8191|STIBBLK: Source2 should always be Immediate/sGPR Value LDIBBLK(L|C): for src mode0/4 src2 should be IMM for a6x and aboveLoadStore: for Getfiberid instruction dst should be GPR only LoadStore: for stc instruction src1 should be IMM LoadStore: for stsc instruction src0 should be IMM SCT - Relative addressing not allowedSource Operand Out of Range for 32Bit Unsigned DataType.Only Allowed Range is 0 - 4294967295 Texture: (F16) and (F32) are valid destination data types with GETPOS Texture: (UINT16) and (UINT32)are valid destination data types with GETSIZE/GETINFOA4XUINT*PIPEPATCH24PATCH29BUILTINtISFRONTFACEVERTEXSIZETESS_FACTORS_SIZECOVU8S16INSTRCOVU16S32INSTRCOVF32U16INSTRLOADXAU32INSTRLOADLS32INSTRLOADPS16INSTRSTLF32INSTRSTLU8INSTRG2LS32INSTRLOADCINSTRSTGBA2DINSTRSTGBAUT1DINSTRSTGBAUT1DTYPEINSTRFENCELRWINSTRATOMXCHGGENGPUS32INSTRATOMMAXGENGPUS32INSTRATOMBSUBGNU323DINSTRATOMBMINGU32INSTRATOMBMINGS323D1LINSTRATOMBMAXGU323DINSTRATOMBMAXGS323DINSTRATOMBANDGU322DINSTRATOMBANDGU323DINSTRATOMBAORGU322DINSTRATOMBORGS32INSTRATOMBACMPXGU322D1LINSTRATOMBACMPXGS322D1LINSTRATOMBXCHGGS323D1LINSTRATOMBINCGS323DINSTRATOMBDECLNGS321D1LINSTRATOMBDECLNGU323D1LINSTRATOMBADECRGGU321D1LINSTRLINEARMODEQUADSHFLMODEHORIZU32INSTRAROMINCLNLS32INSTRSTIBAF323DINSTRLDIBF322DINSTRLDIBF323DRCKINSTRLDIBAS323DINSTRSWZU32U16INSTRSWZS16F32INSTRSWZS16F16INSTRMOVSU16S32INSTRMOVSU32U16INSTRMOVSS16S32INSTRMOVSF32S16INSTRATOMDECRGGENGPUU32INSTRATOMDECRGGENGPUS32INSTRMOVMSKW64INSTRMOVMSKW96INSTRLDIBUNTYPEDU322DRCKINSTRLDIBUNTYPEDS322DRCKINSTRLDIBTYPEDF162DINSTRSTIBTYPEDF323DINSTRLDIBS161DTRCKINSTRLDIBS163DINSTRLDIBAS161DTRCKINSTRGATU32S16INSTRPIPRREADINSTRGETFIBERIDS32INSTRGETGPRBASEU32INSTRSHFLXORW8INSTRDCL_CL_DIVIDED_GLOBAL_SIZE_TOKENDECLARE_PRIMITIVEDECLARE_CL_MaxFlowCtrlNestingDepthATOMLINCDECSTRL2GINSTRSTXAINSTREFUINSTRDEST_CHANGE_PARAM0SOURCE_REGISTER0SOURCE_REGISTER1ACCS_QUALIFUAV_STORE_DESTDCLVAL11syntax error, unexpected %s, expecting %s or %s or %s or %s Invalid Instruction Repeat Number. It can be in range of 1 - 3 (rpt1-3)gsglueCodeDesc_A5XADRENO_SHADER_BEHAVIORADRENO_RT_DESCADRENO_STEREO_RENDERING_INFOADRENO_IMAGE_ATTACHMENT_INFObindlessUsageInfofsInputstcstcsBinningPatch_OutputUnknown_value_typeOES_STANDARD_DERIVATIVESMaxTessControlImageUniformsisEmulatedROImage enableEmulatedROImage="true"" hwSlot="GL_INT_VEC2GL_FLOAT_MAT2x4GL_FLOAT_MAT4x2GL_SAMPLER_1DGL_INT_IMAGE_CUBEQGL_TEXTURE_Y2Y_QCOMQGL_UNSIGNED_INT_TEXTURE_BUFFER arraySize = %d MatrixLayout = %sgl_Layer(curName || useBlockName) && "Assert Index:[27] name is not NULL or IOBlock name"metaGV && "Assert Index:[45] metaGV is Null"0 && "Assert Index:[51]"$GLPointSizeScaleFactorFloat32Atomic counter buffer base pointers (array of uint32)Sample Position Bottom-Left Location(startComp <= packSize) && "Assert Index:[38] components cannot exceeds 4"noDefaultFragmentHighpforceMediumpPrecisionSupportPredicationdisableRotationWAenableSingleRegisterPoolSingleBBenable3rdCoordForInitialTextureviewMask-pre.bcllvm.qgpu.fract.f32llvm.qgpu.max.f16llvm.qgpu.global.fget.reg.v3f32.p0f32llvm.usub.with.overflow.i16mdOutNodes && "Cannot get output symbols!"basePtrType && "dyn_cast to basePtrType is Null"sym && "Symbol sym is Null"false && "VRS not supported or VRSFoveationQuality is not enabled."sampleIDGV != NULL && "Unable to find SampleID symbol for patching Sample Mask"(mShaderType == QGLC_SHADERTYPE_Vertex) || (mShaderType == QGLC_SHADERTYPE_TessellationEval) || (mShaderType == QGLC_SHADERTYPE_Geometry)srcME->getSize() == 1 && "gl_FrontFacing should be scalar!"aggTy && "dyn_cast to aggTy failed"dstVecElemTy && "dstVecElemTy is Null"!srcVal->getType()->isPointerTy() && !dstTy->isPointerTy()__qcom_RT0_Write_Testterminateget_intersection_instance_index__RTgetHitGrpShaderId__qcom_BARY_Coordinate_center_non_persp_igl_PrimitiveIDCBLocInfo.mDefaultUboSize == 0indices.size() == scales.size()func && "main function is expected"valueToStore && "value to store in null"false && "Fail to find ssbo GV."GV && "Named Variable not found"newAtomicInst && "atomic instruction is expected."false && "Wrong load type"retVal != NULL && "failed to lower the named constant"fragoutoutShadingRateKHRgl_MaxVertexUniformVectorsgl_MaxVertexOutputVectorsgl_MaxComputeImageUniformsgl_MaxGeometryUniformComponentsusampler2DArrayvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/codegen/TypeManager.cppleftNode->isStruct() && rightNode->isStruct()baseAddr != __null && "matrix doesn't have a base address"baseType->getQualifier() == EvqUniformBuffersignintBitsToFloatbitCountunpackUnorm2x16NrefQGLC parser codegen:>cannot convert from '%s' to '%s'can't modify gl_NumSamplescan't modify gl_MaxFragmentInputVectorscan't modify gl_MaxTessEvaluationUniformComponentscan't modify a samplerarray constructor needs one argument per array element'invariant' is only legal type-qualifer for shader outputs and varyingsVarying struct cannot contain an struct memberConstant value cannot be passed for 'out' or 'inout' parameters.the location is not within attribute range [0, MAX_ATTRIBUTES-1]image layout format and type mismatchInvalid invariant declaration on non-output varGL_OES_EGL_image_external_essl3GL_OVR_multiview2table.size() >= 0 + 1Direct Index for StructureVector SwizzleIndex Bufferinverse sqrtBit field extractTexture2dBad type in AddUnaryMath(colNum > 1 && colNum * colNum == objectSize) && "mat2/3/4 are expected"blockDimensionsdFdyprimitive mode already specified and it is not isolines'gl_FrontFacing' cannot be invariant#endif missing.malformed argument listcannot #undef a builtin GLSL compile error: Out_of_memoryDecimal constant overflowfalse && "expect them to be translated to EvqRPObjectToWorld/EvqWorldToObject"matrixPtrInfo != NULLinitC->isNullValue() && "Non null initializer???"(basePtrTy != NULL) && "base pointer type is expected"Invalid SPIR-V module: numWords in instruction is 0OpTypeImageOpSNegateOpAnyOpINotEqualOpBitCountOpDPdxOpEnqueueKernelOpGroupNonUniformBallotBitExtractOpGroupNonUniformBallotFindLSBOpGroupNonUniformUMinOpGroupNonUniformBitwiseAndOpRayQueryGetIntersectionInstanceIdKHROpRayQueryGetIntersectionGeometryIndexKHRrd.lbasecommittedAttrsrayList.executingRaysCount.execrc_nzgetCommittedHitInfoAddrgep->hasAllConstantIndices() && "unhandled non-constant index" (TES) (Float32)allocationHandle: fpDominate: pointSizeVirtualRegAndComp: mergedShaderInfoRegID: vpcIndexes: vpcIndexes[outPrimType: enablePostDepthCoverage: bufferIndex: [ADRENO_PATCHED_ASTC_TEXTURES] (Ver hwSlot: numEmulationHWSlots: numBindlessRanges: yuvCSCStandard: useBindlessSampler: [ADRENO_DYNAMIC_CBCACHE] (Ver isWriteOnly: isSamplerForBlockMatch: isRootUniform: parentUBOName: numScalarRegisters: ]: [ADRENO_MS_VSPASSTHRU] (Ver scratchBufferSize: vertexPayloadSizePerWorkgroup: substateCRC: maxAttributeSizeInBytes: .metadataSize[ADRENO_SHADER_TEXTURE_USAGE].vpcIndex.domainVRegID.primitiveIDVirtualRegID.primitiveIDVPCIndex.localIdRegID.localSizeX.numElements.numTextures.set.numUsedTextures.rootParamIndex.virtualRegIDMask.isCoherent.offsetInBytes[GL_NAMED_CONST][ADRENO_MS_VPCPASSTHRU].screenCoordTexUsagesUnrecognized structure id BINNINGSECT_SHADER_CODEUnable to load diff metadata. - EFUs : %8d,%8d (rpt), ratio %5.2f preamble_move - imm : %8d - hof : %8d - ldck : %8d,%8d (rpt), ratio %5.2f - ldgk : %8d,%8d (rpt), ratio %5.2f - ldca : %8d,%8d (rpt), ratio %5.2f - ldcasize : %8d memory_stAllsize - Output Size : %8d max_number_of_wavesfibcntefu_rptflat_bary_rptpreamble_all_rpttex.pcmnmem.ldlvmem.stgaQCCOptionStringEnableBindlessUAVSpecializationValuePtrShutOffUAVVPIndexValuesEnableUnifiedSchedulerBGEElementCountPtrEnableDeviceIndexAsViewIndexForceHighpOutputForceHighpUniformOutputD3D10ShaderStatsValidateASICIDOptionABOpcodeVM32BitBindlessIndicesUCHETrapBaseLoshaderRegisterisSSBOresourceValueSize="fragDataEntryunaligned frag data location elements bufferA7pUnable to parse SpecializationInfoCount value 'Unable to parse DumpObjFile value 'Unable to parse AvailableGprLimits value 'Unable to parse ForceDoubleWaveSize value 'Unable to parse EnableSingleRegisterPoolSingleBB value 'Unable to parse EnableASTCPatching value 'Unable to parse TextureFormatForSSBO value 'Unable to parse EnableBindlessSampler value 'Unable to parse EnableSingleBindlessBase value 'Unable to parse ABOpcode value ' OptLevel (1): Optimization level EnableUnSafeMath (false): enable LLVM unSafeMath optimizations EnableFSFovPatching (false): Enable foveation patching for fragment shader builtins {newline} ErrataQueryOpts A619 A430 A506 A617 A621 "BB#gc gc-lowering********** MACHINEINSTRS ********** !branched() && "Cannot acces leaf data in branched root"codegen-cpParentMBB && "bad instr"Post SSAkilljbuf_gepexn_selector_geplsda_addrNumber of PHIs loweredNumber of spill slots allocateddagcombineNumber of load/op/store narrowedAtomicLoadMaxRegisterMaskfcosffloorsetccbuild_pairNumber of times dag isel has to try another pathf__negsi2__gcc_qadd__divxf3fmal__powisf2__floatundisfInvalid VST_BBENTRY recordInvalid Type ID in CST_SETTYPE recordUnknown element type in CE_DATAInvalid CE_CAST recordGlobal not a pointer type!vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/IPO/GlobalDCE.cpp in other contextsslp-vectorizedisable-replace-idiv-i64-optsMemOrder && MemScope && "mem order / mem scope not const in atomic_work_item_fence"nextSlotNum[resType] < getTargetFeatures().getValue(QV_MAX_SAMPLER_SLOTS)LowerHighLevelIntrinsicsPassSupports 16-bit int divHR5_bHR27_bHR42_aHR46_bHUR0_aHUR4_aHUR6_aHUR6_cIR94IR100R6_cR7_aR10_aR15_aR18_cR27_bR30_cR36_cR37_cR43_cUR2_c<0>invalid operand for instructionQGPU::move.f64QGPU::ICMPltQGPU::fsel16(!KILLSeen || getTargetFeatureFlag(QF_SUPPORTS_BARY_AFTER_KILL)) && "Bary after KILL instruction"_CL_extra_lm_varfalse && "Too many multicopy destination registers"Disable scalarizing Oxili BC instructions_false && "Operand is NULL\n"__preamble_MultiBB Kernel )"->"Enable aggressive vectorization of readonly loadsDefInst && "Unexpected pattern while lowring image read"false && "Unsupported type \n"getRegClassFor(prefReg) == dstRC && "Register class mistmatch"srcVT.getSizeInBits() <= MAX_SRC_VT_BITS && "Unsupported src type in ZERO/ANY_EXTENED"false && "Exceeded maximum number of write image id's"AllocIID == Intrinsic::qgpu_alloc_temp_regs && "Invalid intrinsic"false && "unsupported size"initializerMappingData.NumCompToCopy >= LenVal * NUM_CHANNELS && "LDCK Length exceeds GV size"0 && "Unknown shuffle mode"false && "Unknown image dim in HandleWriteImage"MemType != nullptrfalse && "QGPUHandleAtomicCmpExchgIntrinsic(I) should be handled by CL builtins now"Fn && "Indirect calls are not supported"!CS.getType()->isVoidTy() && "Bad inline asm!"false && "Unhandled getcycle return type"ResultReguse_wmms24m16.s2en << add.f.mul2mad.f32shlm.b16mova1.ugetsizeimg_bindlessstthrstscuvgs.evendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUMachineEncoder.cpp0 && "unknown src operand type!"The dst modifier is NOT allowed in EFUthis->useLocalMemnumber of nops exceed max of 6!qgpu_uav_sizes_in_elementspMD != NULL && "Unexpected MS primitive attribute enabled metadata operand"abs(DstRegRelOffsetError: RegClassMismatchError: NumConstRegsOrImmsError: Half precision temporaryPredicateStrategy to force grouping by 6 for 6 samsA3BC && "Instruction is NULL"no-dcvt-folding-phnewMILRs.size() <= RC->getNumRegs() - 4 && "Not enough physical registers?"SNode->NumOutEdges > 0 && "Negative # of edges?"!E->DstNode->IsMem && "No memory node in cyclic edges"FreeReg != 0 && "No available free register"neg_hi_with_carryfalse && "StoreThr address is not a pointer getCalledFunction()"Check register hint warningD!LI_Cur->isChild() && "Cannot spill a PHI live interval that was already split."AllocInstSlot < nextUseSplitSlotIdx && "Sanity checking failed"MDForcedConstantRAMModeValueuppf-halfAlways promote halves (using movp currently)!TargetRegisterInfo::isPhysicalRegister(VReg) && "bad register class"!AllocatedUGPR && "already allocated a UGPR" LDST: Out of Range Offset with stx.a instruction. Allowed Range is 13bits, |0 - 8191|the stgb instruction should use g with dst. Usage g[r4.x+32] ATOMIC.b: for src mode1/2/5/6 src2 should be GPR for a6x and aboveRESINFO: for src mode0/1/2, baseid ignored for a6x and aboveSTIBBLK: for src mode1/5 src2 should be GPR for a6x and aboveSTC: for stc instruction dst should be GPR or sGPR LDG.k: the ldg.k instruction should use g with source 0. Usage g[r4.x+32] ALU2 CAT32: DST is 32 bit but all source operand are not 32 bitALU3 - AND MERGE: b32 is for 32 bit sources src[1]Only address register a0 is allowed for mova instructionMOVS: getcycle is only available since A8xSource Operand Out of Range for 16Bit Signed DataType.Only allowed Range is -32768-32767Source Operand Out of Range for 16Bit Signed DataType.allowed Range is -32768 - 32767TEXTURE: Source2,if enabled is hGPR(mode0/4), GPR(mode1,2,3), imm(mode6/7).Texture: img instr - only hof/sad/ssd/conv/mm is allowed unsupported Data Type provided with dcl_const_store_mapping HS: Invalid OutPut Primitive TypeDOMAIN_QUAD..Not a Valid Access QualifierDEPTHLESSEQUALVSDS_PRIM_SIZEPERSP_SAMPLECENTERUNORMCleanup: discarding lookaheadAt line: COVU32F32INSTRCOVF16U32INSTRGETINFOINSTRJUMPPOINTTOKENLOADTHRCCHEAF16INSTRLOADTHRS32INSTRSTXF32INSTRLOADGBU2DF32INSTRLOADGBT3DF32INSTRXCLRINSTRATOMADDGENGPUS32INSTRATOMXCHGGGPUU64INSTRATOMINCGGPUU32INSTRATOMMAXGGPUU32INSTRATOMBADDGNU32INSTRATOMBADDGNU323DINSTRATOMBMAXGNU32INSTRATOMBORGNU32INSTRATOMBAADDGU322D1LINSTRATOMBAADDGS321DINSTRATOMBAMAXGU322D1LINSTRATOMBAXORGU322D1LINSTRATOMBAINCGS32INSTRATOMBAINCLNGS32INSTRATOMBINCLNGU321DINSTRATOMBINCRGGU321D1LINSTRATOMBAINCRGGU322DINSTRATOMBADECGS323DINSTRATOMBADECLNGS322DINSTRATOMBADECRGGS323DINSTRCLZBINSTRSELB32INSTRBRCSTACTIVEW2U32INSTRLDIBAS322DINSTRSHLM32INSTRSWZU32F32INSTRSWZF32U16INSTRATOMDECRGGENSOCS32INSTRLDIBUNTYPEDU321DINSTRLDIBTYPEDU161DTINSTRLDIBUNTYPEDF162DINSTRLDIBUNTYPEDU161DTRCKINSTRLDIBUNTYPEDS162DRCKINSTRSTIBU163DINSTRSTIBF163DINSTRSTIBAU162DINSTRLDIBF162DRCKINSTRSCTS32S16INSTRPACK4SAD_ENABLESHFLDOWNW8U16INSTRROUND_NERBRACEDCL_CL_GROUP_ID_OFFSET_TOKENUAV_TYPEDECLARE_HS_EXTRALOCALMEMORYSIZEDCL_PS_TEX_ENTRY_TEXTUREIDDCL_CL_CSSTATESIZEHALF_GEN_REG_NAMEstmtDEST_RENDER_TARGETFLOW_PRED_INSTRSTTHRINSTRADDINSTRCMPVINSTRMAD32INSTRSOURCE_MODIFER0IMM_VALUE2DCLVAL33ALU3: Destination operand of ALU3 cannot be dummy registerTEX: last-use-if-source-is-a-GPR is not allowed. LDST: Destination operand type cannot be dummy registervendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/core/StaticAnalysisPass.cppStatic AnalysisstaticTextureMappingsmergedShaderDesc_A4xADRENO_PS_GENERATED_INPUTSADRENO_PS_OUTPUTSADRENO_PATCHED_SHADER_HANDLESastcTexturesfsRenderTargetFormatscsDescUniformSubElementcollectionDatamaximumShaderRegisterUsagePerFibertripleString64Bit.size() < MAX_TRIPLE_LENGTH - 1 && "Assert Index:[5]"MAX_VERTEX_IMAGE_UNIFORMSAMD_LINE_COORDANDROID_EXTENSION_PACK_ES31AMaxTessEvaluationImageUniformsMaxBufferBlockSize============ Enabled Link Options ============ " elementType="0x%04xSubElementInputGL_FLOATGL_SAMPLER_709R2Y_QCOMQGL_UNSIGNED_INT_TEXTURE_CUBE_ARRAY pOutProgramBinary = precise, useUAVSlot, Struct name = %s image attachment index = %dvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/MetaDataExportGL.cpp$YUVControlInt32$PointCoordCenterVec2Fragment Coordinate Z Scale and OffsetVertex SizeLocal Memory Primitive SizeOpenGL Compute Shader gl_NumWorkGroupsPosition Rotation Matrixto get fragment invocation count for GL_EXT_fragment_invocation_densityifCvtThresholdWithUniformBranchLM sizeenableTexturePromoteWAenableVGPRenableEndofGlobalMemforceVariablesforceInputllvm.qgpu.global.iset.reg.p0i16.v4i16llvm.qgpu.iabsneg.i16llvm.qgpu.fceil.f32llvm.qgpu.scale.v3f16gs_exit_bbfalse && "unknown image type for query"mTESIOMD != NULL && "Unable to add TES IO metadata to module"GV && "GlobalVariable should not be Null here"vecMe->getSize() == matrixMe->getRowSize() && "vector and matrix have different size for multiply!"(dRefOP || biasOrLodOP) && "GLSL expect shadeow cube array Dref in biasOrLodOP"srcTy->isStructTy()srcTy->isArrayTy()mGlobalKill != NULLgetInRayFlagsgl_SampleIDsrcOP->getSize() == 2 && "Wrong vector type for physical AS ptr"dest && "OpRayQueryGetIntersectionObjectToWorldKHR is not supported"get_world_ray_originorig_mainReportHit$setupBaryP_i_over_w(*mSymbolObjectMap)[gv] == NULLfalse && "Unknown or unexpected symbol type"$aliasingGVgetOffsetFromCallFramegl_SecondaryFragDataEXTgl_ViewportIndexgl_MaxVertexTextureImageUnitsgl_MaxCombinedShaderOutputResourcesUYVY samplerExternalOESutexture2Dimage3Dvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/thin_compiler/programbinaryloader/ProgramBinaryLoader.cppfalse && "setNumSamplerSlots called on invalid object"leftOperand->getLLVMOperand()->getAddrPointer() && "right value must have an address pointer"rhsVal && "rhsVal to StoreInst is Null"trueLastBB && falseLastBB && "true or false branches of question mark if-then-else have no basic blocks!"contained && "active uniform expected"node->isInBlockObject() && "not in a named UBO/SSBO"baseSym != __nullbaseNode->getAsBinaryNode()vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/include/LA/gl_core/CodeGenHelper.hpp(leftNode != NULL) && "invalid binary node"isCuimgctransposegreaterThanusubBorrowimageAtomictextureGraddefinedcan't modify gl_MaxSamplescan't modify gl_MaxVertexAtomicCountersreserved built-in namevariables with qualifier 'const' must be initialized cannot initialize this type of qualifier Cannot offset into the matrix$nestedSamplersoverloaded functions must have the same return typefuncNode != __nullstructure has no fieldstype name can't be used to access uniform/storage buffer members field selection requires structure, vector, or matrix on left hand sideCan not redeclare gl_out with array sizegl_PointSize must be a scalar float!duplicated precise qualifiers for parameter or parameter already has const qualifierInput/Output ArraySize dosn't match with layout declarationinvalid local_size_y of 0GL_OES_sample_variablesGL_EXT_geometry_point_sizeGL_NV_shader_noperspective_interpolationGL_QCOM_block_matchSelection Node found in constant constructorConvert Uint to IntTexture2DShadowLodOffsetImageStore1DArrayImageAtomicCompSwap%f (%s).astUnary operation not folded into constantCannot promotelodftoiLocation is only allow for in/out/uniformvertex spacing already specified and it is not fractional_odd_spacingSAMPLER is for Vulkan api onlyarray dimension not fully specified for variableReserved word.ivec2 GLSL error:' is not supported#version must be followed by a numbervendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/vulkan/codegen/SPVCodegen.cppvecTycompResultDataType &&"Component Data Type cant be Null"(sc == StorageClassRayPayloadKHR || sc == StorageClassIncomingRayPayloadKHR) && "Incompatible storage class"false && "OpPtrDiff compare pointers of different types \n"conditionOperand->getSize() == 1 && "Unexpected condition size"srcOperand && "src operand is expected"srcME && srcME->get(0)scope && "scope constant value is expected"OpLineOpExecutionModeOpSpecConstantOpOpFunctionOpCompositeExtractOpCopyObjectOpFNegateOpISubOpFMulOpLogicalNotEqualOpBitFieldUExtractOpGroupAsyncCopyOpReserveReadPipePacketsOpIsValidReserveIdOpPtrDiffOpRayQueryGetIntersectionInstanceShaderBindingTableRecordOffsetKHROpRayQueryGetRayFlagsKHRshaderObjects[i] && "cant be a null pointer"@@getRayIdstv3scheduleCHitgeneric.stack.storeoffsSTy != NULL && "array type is not expected"insertBefore && "a call to getRayId should have been followed by a call to loadRayId"funcSchedShader && "scheduleShader() should have been inserted in init()"mbcount.ptrstack.base.ptrrd.lbasecurStackPointerrd.lbaseaccelerationStructurePtrWOri != NULLvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/include/common/raytracing/StateFunctionTransform.hgep && "Unhandled live pointer"higher32 (Undefined) (SampleL) (QGLNEXT_PUSH_CONSTANTS_UBO_INDEX)symbols[regIDs: ]: outputsViewportArrayIndex: pointSpriteUVVirtualComp: outputsStencil: [ADRENO_RT_DESC] (Ver TexSwizzleW: constSlotID: sourceByteOffset: numViews: positionSymbols[[ADRENO_HW_SPECIFIC] (Ver [ADRENO_SHADER_DEVICE_TYPED_ALLOCATIONS] (Ver [ADRENO_BINDLESS_USAGE_INFO] (Ver numUsedTextures: isSamplerForFBFetch: blockMemberIndex: structMemberIndex: numVertexAttrs: [ADRENO_NAMED_SHADER_HANDLESV2] (Ver hwInfo: hwCRC: maxPayloadSizeInBytes: .minVGSv.uavUsageMask.usesKillInstruction.constantBufferCacheEntries.needsBaseInstance[A3X_CLIPPLANES].orientationType.facenessRegID.scratchVec4ConstID[ADRENO_CS_DESC].useTexelCounts.useHWStereoRendering.numViews.useBindlessCBuffer.HWCodeCRC[ADRENO_DYNAMIC_CBCACHE_ENTRY].fbFetchMask[GL_SYMBOL_INFOS].isNoPerspective.structName ============ Unable to read CBMapsDesc, InputsDesc, OutputsDesc, CBUsageDesc, DXMetaDesc or CBDynCacheDesc SECT_CONST_TAB[BinningTessEvalShaderCompilerResultUnknown - MOVs : %8d,%8d (rpt), ratio %5.2f - dsypp : %8d - gatherG : %8d - gquad : %8d - store callst : %8d - stp : %8d,%8d (rpt), ratio %5.2f - ldgasize : %8d - Num Of Input Components: %8d wave_size_modepreamble_efu_rpttex.getinfotex.img_bdlmem.atomicl_rptmem.ldca_rptmem.shfl_rptmem.shflsame_rptOutput component countAddInstrumentationEnablePSInputPackingGLSerializedBufferReservedLocationsSRefFragDataBindingSRefEnableUAVBGRSwizzleWASkipCodeGenOutputSignatureOutputPassTimersDisableDummyNonPerspectiveIJBGEElementTypePtrBGEBaseShaderRegisterPtrABGEAuxBindlessIndexPtrBGEStrideInBytesPtrForceRotationAllEnableFilterCubicPatchingFilterStatsSrcPreserve32bDenormPipelineCreateFlagsRayShaderStagesVkflagsRESOURCE_SIGNATURE_DESCRIPTOR_TABLEresourceCategoryauxDescTypeauxBindlessIndexTargetError parsing auxiliar bind group element data: Unable to allocate resource name string ' Unable to parse CompilerCfgName value 'Unable to parse Use64BitAddr value 'Unable to parse GLIRShader value 'Unable to parse InputAttachmentSize value 'Unable to parse EnableProfiling value 'Unable to parse ForceSingleWaveSize value 'Unable to parse EnableAllResourcesBound value 'Unable to parse EnableLiteralPreloadViaPreamble value 'Unable to parse DisableDummyNonPerspectiveIJ value 'Unable to parse ForceHighpTexCoord value 'Unable to parse PerInstanceAttributesMask value 'Unable to parse AllCompilerOptions3 value 'Unable to parse VMAssertonNoSymbol value 'Unable to parse EnableConstTSForInitTex value ' ReservedLocationsCount (0): number of symbols with reserved location GLShaderType (__null): GL shader stage type for IR shader Nv12RenderTargetMaskWA (0): Enable workaround for nv12 uint view outputs (output = (float)output * 1.0 /255) EnableSharedConstants (false): Enable shared constants AllowUniformInGlobalInit (false): Allow using uniforms in global initializers SimulateVariableRateShading (false): Simulate variable rate shading ForceHighpOutput (false): Force shader output variables to use high precision TFDataSize (0): size of one TFData entry > A330 A509 ShaderStageUnknown,HS:0xABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/qcc_skip_validate_uav_metadataInvalid Texture * Const is limited to sam opcode only., error in compiler-generated metadata. No SteamOut Meta This is the equivalent of the GLNext symbol, it only excludes data that has previously been marked as compiler-only. Ultimately we can save a lot of space by specializing the symbols for each type. Version 1.0: Added name: symbol name defined in the shader Added ioBlockName: symbol name used for instanced IO block (input/output/patch/builtin/subelement symbols) Added structName: hold the type name of parent struct symbol, valid for flatten varying struct Added uboLocation: Holds information about location information for symbols placed in UBOs Added namedConst: Holds information about named constants Added arrayDimensions Added flags Added arraySize: 0 for non-arrays Added declaredArraySize: used for uniform arrays Added bindlessOffset: the descriptor set offset within a set/group Added bindlessSamplerOffset: the descriptor set offset within a set/group for a combined tex/sampler symbol Added binding: binding layout qualifier Added symbolID: used for identifying buffer symbols Added location: location id defined in GLSL explicitly, used by API layer to resolve the ID conflicts Added numLocations: number of locations needed Added numSubelements: number of subelements after UBO is fully flattened to matrix/vector/scalar Added bindingStride: binding stride (0 or 1) Added blockMemberIndex: fieldIndex of flatten IOblock symbol Added structMemberIndex: fieldIndex of flatten Struct symbol Added advancedBlendLayoutMask: Its mask of all the active blending stages using E_QGLC_GLSL_ADVANCED_BLEND_LAYOUT Added samplerSlot: sampler slot, s# Added textureSlot: texture slot, t#, applies to sampler/image Added textureSlotForIntGather: t#' used for samplers that are used with integer gather operations Added UAVSlot: UAV slot #, applies to image/SSBO Added numDimensions: number of dimensions if this is an array symbol Added dataType: gl ARB type value GL_SIGNED_INT, GL_UNSIGNED_INT_VEC2 etc Added layout: Layout qualifiers used by API layer to pass the information to App Added unsizedArrayIndex: index for named constant for unsized array in SSBO Added component: starting component, this can be specified in GLSL 4.4 shader explicitly, packing can also impact this Added matrixLayout: Matrix Layout qualifiers used by API layer to pass the information to App Added precision: The precision info which is used in codegen Added defPrecision: The precision info which is declared in the GLSL shader Added bindingSet: set layout qualifier in Vulkan Added dualSrcBlendingIndex: frag output symbol index for dual src blending Added infos Version 1.1: Changed unsizedArrayIndex to be 32 bits. Information necessary for executing a merged shader (VS+GS, VS+HS, DS+GS). Note that all stages will declare a primitive ID in case the next stage needs it. Version 1.0: Added needsMergedShaderInfo: True if the shader uses the merged shader info register. Added needsPrimitiveID: True if the shader really uses primitive ID. Added mergedShaderInfoRegID: Scalar Reg ID assigned for MergedShaderInfo. Added primitiveIDRegID: Scalar Reg ID assigned for PrimitiveID. Defines a list of shader statistics in CSV format, with names corresponding to the ones defined in StaticOBJStats.h. Version 1.0: Added csvStats The compiler can choose to use .a instructions for UAV accesses in A5x+, but this means that the descriptors may be incompatible with the code generated previously for a4x. Version 1.0: Added useTexelCounts: True if UAV descriptors are expected to have all strides except for the texel stride specified in texel counts. Information about how to initialize the boolean_cf_mask register used by the brac instruction. Version 1.0: Added numConstantExpressions Added constantExpressions Incompatible program binary provided, failing load. Pixel Shader found, use LoadObjectFileDXPS solidusseven"can't happen" -- you found a bug' is invalid value for boolean argument! Try 0 or 1 DW_TAG_reference_typeDW_TAG_GNU_template_parameter_packstatstarget triple = "module asm " inbounds atomic_counter section "zeroext uwtable rs_user pcmpgtfalse && "Unknown aggregate type!"] DFSNumbers invalid: llvm.arm.neon.vld4llvm.arm.neon.vminullvm.arm.neon.vqrshiftnullvm.arm.neon.vrshiftsllvm.arm.neon.vst2lanellvm.arm.neon.vst3lanellvm.convertuullvm.cosllvm.expectllvm.hexagon.A2.satuhllvm.hexagon.A2.svavghsllvm.hexagon.A2.svsubhllvm.hexagon.A2.sxthllvm.hexagon.A2.vminbllvm.hexagon.A2.vnavgwrllvm.hexagon.A2.zxtbllvm.hexagon.A4.cmpbeqillvm.hexagon.A4.cmpheqillvm.hexagon.A4.combinerillvm.hexagon.A4.rcmpneqillvm.hexagon.A4.round.ri.satllvm.hexagon.C4.cmplteullvm.hexagon.F2.conv.sf2d.chopllvm.hexagon.F2.dffma.scllvm.hexagon.F2.dffmsllvm.hexagon.F2.sfcmpgellvm.hexagon.M2.cmacsc.s0llvm.hexagon.M2.mmpyh.rs1llvm.hexagon.M2.mpy.lh.s0llvm.hexagon.M2.mpy.up.s1llvm.hexagon.M2.mpyd.hh.s1llvm.hexagon.M2.mpyu.acc.hh.s1llvm.hexagon.M2.mpyu.acc.ll.s1llvm.hexagon.M2.mpyud.nac.ll.s1llvm.hexagon.M2.vmac2llvm.hexagon.M2.vmpy2s.s0packllvm.hexagon.M2.vmpy2s.s1llvm.hexagon.S2.asl.i.p.orllvm.hexagon.S2.asl.i.r.andllvm.hexagon.S2.asl.i.r.xaccllvm.hexagon.S2.asl.r.pllvm.hexagon.S2.asr.i.pllvm.hexagon.S2.asr.i.svw.trunllvm.hexagon.S2.asr.r.pllvm.hexagon.S2.lsl.r.rllvm.opencl.vec.type.hintllvm.opencl.write.image1allvm.opencl.write.image1bllvm.ppc.altivec.vavgshllvm.ppc.altivec.vcmpgtfp.pllvm.ppc.altivec.vmladduhmllvm.ppc.altivec.vmuloubllvm.ppc.altivec.vpermllvm.qcom.f322u16llvm.qcom.u162s16llvm.qgpu.atomic64.dec.oobllvm.qgpu.atomic.inc.rangellvm.qgpu.atomic.work.item.fencellvm.qgpu.calc.offset.bary.coordsllvm.qgpu.dsxppllvm.qgpu.fcombine47llvm.qgpu.fcreate.map21llvm.qgpu.fcreate.map24llvm.qgpu.fcreate.map49llvm.qgpu.fcreate.map6llvm.qgpu.fldgallvm.qgpu.gather4xllvm.qgpu.get.special.const.floatllvm.qgpu.icombine16llvm.qgpu.icombine34llvm.qgpu.icreate.map38llvm.qgpu.mulhillvm.qgpu.rcpllvm.qgpu.set.mesh.special.attrllvm.qgpu.subgroup.fshufflellvm.qgpu.subgroup.get.active.maskllvm.qgpu.umadshllvm.spu.si.cgthllvm.spu.si.dfnmsllvm.spu.si.fmallvm.spu.si.fsmbillvm.spu.si.sfxllvm.x86.avx2.pblendvbllvm.x86.avx2.pbroadcastq.128llvm.x86.avx2.pminu.wllvm.x86.avx2.pmul.dqllvm.x86.avx2.psll.wllvm.x86.avx.cvtdq2.ps.256llvm.x86.avx.vzeroupperllvm.x86.mmx.pavg.wllvm.x86.mmx.pextr.wllvm.x86.mmx.pmulu.dqllvm.x86.mmx.psra.dllvm.x86.mmx.psrli.wllvm.x86.mmx.psubs.bllvm.x86.sse2.clflushllvm.x86.sse2.ucomige.sdllvm.x86.sse41.insertpsllvm.x86.sse41.pmovsxbdllvm.x86.sse41.pmovsxbqllvm.x86.sse42.pcmpistris128llvm.x86.ssse3.pabs.d.128llvm.x86.ssse3.psign.bllvm.x86.xop.vpcomneubllvm.x86.xop.vpshlb0 && "ReplacementGlobalContext not set?"rangedisable debug outputviInvalid user of intrinsic instruction!Referencing function in another module!invalid fpmath accuracy!Logical operators must have same type for operands and result!Invalid binary operation!invalid llvm.dbg.declare intrinsic call 1 does not match parameter %invalid linkage for intrinsic global variableNamed metadata operand cannot be function local! .def is_stmt .seh_pushreg Number of assembler layout and relaxation stepsLanguage Specific Data AreaDTPOFFDTPREL_HIInst:(__gcc_except_tab__compact_unwind__debug_macinfoS_MOD_TERM_FUNC_POINTERSDon't know what kind of handler this is! (ignoring feature) "%noregyCatanlceilflog10__cxa_guard_abortvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/IREmitter/IREmitter.cppqgpu.miss.shaderllvm.loop.unroll.disableprint-no-modref forwarding to cfg.label="{IV Users for loop S && I && L && SE && LI && "Null arguments in isInteresting !"Number of instructions (of all types)Number of instructions Scalar (of all types)Number of reassociationsUndefined result: insertelement index out of rangeTry to delinearize array references.ZIV independenceBanerjee independenceVerify loop info (time consuming)Loop Pass Manager print-memdepsNo Alias Analysis (always returns 'may' alias)N <= size() && "Invalid specifier"In path profiling, insert extra instrumentation to account for unexpected function termination.(zext list && "Uninitialized control dep list?"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/Target/TargetLowering.hlpadun.tmpWeight of the branch unlikely to be taken (default = 4)lowerinvokeinvoke.num.notsimplyfycfg.ifconvert.shufflevector.cost0 && "Not supported RT dimension."interpAtGV && "input GV expected"gv && "Unknonw getreg pattern"GEPInst && "GEPInst is NULL!"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Scalar/CodeGenPrepare.cppenable-lsr-phielimpartially unrolling with count: false && "Unhandled alloca case"Number of aggregates converted to scalarexn.objNumber of duplicated blocksi < N && "Bad index"!Traits::stopLess(b, a) && "Invalid interval"(i == 0 || Traits::stopLess(stop(i - 1), a)) [Unknown] deadRegMustVecconvergeMachine Instruction SchedulerNumber of machine instructions sunkInstruction: Found Missing mayLoad flagExplicit operand marked as implicit register, but got a No live range at defMissing PHI operand is not needed live through the block. Valno #opt-phisAfter Register AllocationTarget cannot enable pass!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"Number of registers unassignedNumber of loads added!ProgressRequired && "Didn't make progress when it was required."false && "No interval info"join-liveintervalsdag._Unwind_SjLj_UnregisterMI && "enterIntvBefore called with invalid index"Number of splits that were simpleMalformed PHI in BB#Number of post-indexed nodes createdProcessed value not in any map!sourceDisable live use priority in sched=list-ilpNumber of loads clustered togetherAssertSextFrameIndexsmuloctpopsetule, anyext__subdf3__mulsf3__floatdidfInvalid CE_BINOP recordInvalid CE_INSERTELT recordMalformed BlockInfoBlockFunction not a pointer type!Invalid GEP recordInvalid INDIRECTBR record!Invalid STOREATOMIC recordAggressively disable extra passesrun-gl-full-pipelineres != resIDMap.end()TI && "no null terminator."constIntType && "input operand must have integer types"llclib: error: could not find triple for target 'llclib: target does not support generation of this CriticalEdgePHIAccessCount: TotalVectorCreated: HC0_dHR3_aHR5_cHR15_aHR15_dHR21_cHR24_bHR30_cHR36_bHR41_dHUR1_bHUR2_aHUR3_dHUR7_dIR34IR63IR71IR83IR90P0_bR5_dR21_dR31_bR34_aSAM24SR5_bUAV13UAV17UAV39UR2_bFVGPRRCUnhandled dialectQGPU::FCMPleQEI->getITexCount() > 0 && "Cannot subtract from non-positive ITexCount\n"false && "invalid branch opcode"false && "vecTy is invalid"false && "invalid vecTy"llvm.qgpu.mad.f32size > 0 && "int/float is expected and 16/32 are supported"VecTy->getVectorNumElements() == NUM_CHANNELS && "Must be of type [# x <4 x elem>]"SrcTy->isVectorTy() && SrcSize == 32BeginOffset && EndOffset && "must have size operand if no index operand"Op0 && Op1false && "Unsupported constant during lowering of shuffle "_CL_group_id_CL_gpu_ex_lock_ptr_CL_num_groupsgv && "GV is NULL. Should have been created by CallGraphSCCPass\n"LenInt && "The 4th argument of qcom_sub_group_constant_load must be an immediate value"0 && "Unsupported cmpxchg type"AM.AddressSpace == GLOBAL_ADDR_SPACEII && "Unsupported converision BC instruction"0 && "Unknown loc info!"isTextureQuery(IID)(eolm).conv.1d(signed)0.01/log2(e)wt#sel.b16gather4gdsxppstlwatomic.oratomic.b.minalias.rtMO && "Machine Operand is Null"(CV != NULL || CZ != NULL || CDV != NULL) && "Expected a constant global variable"__qcom_PSMetaInfoa registerRPTRangeError: MI operands must be balance between reg footprint and latency hidingenable-groupQGPU Post List Schedulerfalse && "Unexpected field: non-const struct element offset"enable-reladdr-foldMin->getOpcode()==QGPU::IMINrr && Max->getOpcode()==QGPU::IMAXrr && "Should be saturation MIRs with IMINrr and IMAXrr"0 && "DCHE: unexpected instruction format"false && "Scalar unit WA only implemented for MOV class"MIOpdIdx < MI->getNumExplicitOperands() && " Out of bound"Only promote N outputs to alias.rt instructions was not defined anywhere in the program.enable-wave64-regfile(Idx >= 0 && (unsigned)Idx < RC->getNumRegs()) && "Not in this class"Convert Metadata to combine instructionsllvm.uadd.with.overflow.i32(lraStatus != QGPU::LocalRA_NotExecuted || lraStatus == QGPU::LocalRA_MultipleBasicBlocks) && "LocalRA should have been attempted first\n"RLI->Bottom != NULL && "All RA loops should have found a bottom exit block."LI_Earliest && "At least one interval must exist"LI_Rep_Child->getStackFrameIdx() != InvalidFrameIndex && "Invalid frame index"FrameIdx != InvalidFrameIndex && "No storage assigned to a intra-block split interval"!UseRightAfterSplit && "Cannot spill a register that needs to be reloaded immediately" Register: uppf-use-distance-nffold targets coverage test, block countQTM->getFlag(QF_ENABLE_UGPR_PROMOTE) && "UGPR Promotion is not enabled"MBB == QTM->getMainShaderEntryBlock(MF) && "Expecting shader entry block" LDST: Out of Range Offset with ldx.a instruction. Allowed Range is 13bits, |0 - 8191|.LDST: last-use-if-source-is-a-GPR is not allowed. ATOMIC.b: for src mode 3/7 reserved for a6x and aboveSTIB: Valid Data Types are u32/s32/f32/u16/s16/f16LoadStore: for pipr instruction dst should be full GPR LoadStore: for stc instruction dst should be GPR or sGPR STSC: for stsc instruction src1 should be IMM LDG.k: the ldgk instruction should use c with dest. Usage c[32] ALU2 CAT32: dstMod (sat) is not allowedALU3 - AND MERGE: b32 is for 32 bit sources src[0]ALU3 - AND MERGE: b16 is for 16 bit sources src[0]ALU3 WMM: src2 immediate value should be in the range of 0 to 4095.Destination operand cannot be ImmediateValueMOV movmsk: Only allowed in a6x and above. the half decimal for Mov/Conv Instruction should start with h/H Source Operand Out of Range for 16Bit half Unsigned DataType.Only Allowed Range is 0x0-0xffffTexture: broadcast.active instr is allowed only in a6x and above only .x component is allowed with address register a0 unrecognized operand type the half imm value should start with h. USAGE: h(imm value)uint16SAMPLERpixelOUTPUT_POINTBARYNONPERSPSAMPLEGSINSTANCEIDDOUBLEError: discardingMULFINSTRKILLINSTRLOADTHRCCHES32INSTRLOADTHRCCHEU32INSTRLOADLF16INSTRLOADPU32INSTRSTTHRF32INSTRSTLU32INSTRSTGBAT3DINSTRLOADLVFPINSTRATOMINCGGPUS32INSTRATOMDECRGGGPUU32INSTRATOMDECRGGGPUS32INSTRATOMANDGSOCS32INSTRATOMBMINGS321D1LINSTRATOMBXORGS321D1LINSTRATOMBCMPXGNU643DINSTRATOMBCMPXGU64INSTRATOMBCMPXGU322D1LINSTRATOMBXCHGGS323DINSTRATOMBXCHGGF32INSTRATOMBXCHGGF321DINSTRATOMBDECGU321D1LINSTRATOMBDECGU323D1LINSTRATOMBADECLNGS321D1LINSTRATOMBADECRGGU322DINSTRSUBUINSTRSHADOWMAPDSYPPTOKENSTIBU322DINSTRANDG32INSTRRCPHINSTRSWZS32F16INSTRATOMCMPXGENS32INSTRATOMDECRGGENS32INSTRLDIBTYPEDF321DINSTRLDIBUNTYPEDF321DINSTRLDIBUNTYPEDS323DRCKINSTRLDIBUNTYPEDF321DRCKINSTRSTIBTYPEDS321DINSTRSTIBTYPEDS321DTINSTRSTIBUNTYPEDF161DINSTRSTIBUNTYPEDF163DINSTRLDIBBLKLU163DINSTRLDIBBLKGF323DINSTRSTIBS161DTINSTRSTIBAS161DINSTRLDIBU161DRCKINSTRLDIBS162DINSTRLDIBAF163DINSTRSTIBBLKU322DINSTRGATS16F32INSTRSCTU16S32INSTRPIPCWRITEINSTRGETWIDU32INSTRSAD_ENABLESHFLDOWNW4INSTRSHFLRDOWNW8INSTRSHFLDOWNW8U32INSTRUIR_RM_NEGIDCL_32BEXPTOKENPIETOKENINVLOGETOKENDECLARE_RESOURCEDECLARE_CS_ThreadGroupLocalYFULL_SGEN_REG_NAMEPIPRINSTRLOADGBAINSTRCMPSINSTRABSNEGINSTRWMMINSTRIMM_VALUE1syntax error, unexpected %sALU3: last-use-if-source-is-a-GPR is allowed only for General registerTEXTURE: .Offset modifier can be provided only for ISAM instruction. LDST: Destination/Source can not be in Constant Memory.STIB.BLK: dst has to be GPR.StaticAnalysisconstantBufferCacheEntriesdynamicTextureMappingsADRENO_SHADER_SAMPLER_USAGEADRENO_VSDSGS_OUTPUTSADRENO_CS_DESCADRENO_INITIAL_TEXTURE_DATAbindlessObjectAtomicCounterhasConstInitializer(tesDSInitializer)gl_PatchVerticesInqgpu_enable_mulitple_positionderef->getType()->isPointerTy()false && "vector alloc need to be scattered"(theUint->getType()->isIntegerTy()) && "scalar int type argument is expected for unpack"val != __nullfragOpnd->getLLVMOperand()->getAddrPointer() && "No FragSize addr pointer"srcWidth == E_WIDTH_QUARTER(isSrcInt || isSrcUint) && "~ operates on integer operand only"false && "can only be default UBO or named constant UBO"gl_SubgroupLeMaskfalse && "construct physical pointer in a wrong place"get_intersection_tVH_ && "OpRayQueryGetIntersectionTKHR" " is not supported"$setupBaryP_j_slope_dxGV != NULL && "Redefined global variable with different type?"qgpu.output.gl.pervertex.offsetflattenfactor == sym->getArrayDimensions()[0]II->getIntrinsicID() == llvm::Intrinsic::qgpu_icreate_map3indexVal && "Invalid Value!"load && "no load for input, found store instead\n"subSampledCBGV && "GV is Null"false && "foudn else in generateUAVAtomicIntrinsic"false && "Unexpected instruction"num < QGLNEXT_NUM_UBOSvaryingFragColorInterfaceBlockOutShaderStorageObjectgl_MaxCombinedAtomicCounterBuffersusampler2DMSuniform buffer(imageFormat == EvqImageFormatNone) && "subpass is expected to have unknown format"dstVecTy->getNumElements() == srcVecTy->getNumElements()loopTestBB && !loopTestBB->getTerminator() && "loop test BB should not have terminator at this point"weightindexNode->getAsConstantUnion()baseType && "baseType is invalid."isM2iimg2aimgcafloatBitsToUintpackUnorm4x8carryrgb_2_yuvtextureGradOffset!copyOf.type.getStruct()plusmultiple same type qualifiers not allowedcan't modify gl_MaxAtomicCounterBindingscan't modify gl_MaxTessControlCounterBufferscan't modify gl_MaxGeometryTotalOutputComponentscan't modify gl_MaxPatchVerticesINTERNAL ERROR inserting new symbolvariable expectedundeclared identifiercan not redefine the type of fragment inoutVarying IO member var creation failedbarrier() can't be at any point after a return statementNot a correct geometry shader input primitive type.GL_OES_texture_3D%sAnd Assign &=Logical NotPre DecrementConstruct boolConstruct mat2x4Construct mat3x3StepBarrierimageAtomicMaxgl_FragDepthEXTprimitive mode already specified and it is not quads: name must not start with GL_Too few args in Macro scopeIdOp && "scope operand is expected"inst &&"inst is Null"OpTypeRuntimeArrayOpLoadOpFSubOpLogicalNotOpFUnordNotEqualOpEmitStreamVertexOpEndStreamPrimitiveOpGroupNonUniformSMinOpRayQueryTerminateKHRQGLC parse overheadLinker - Link UniformsAdding tf entry: vpc] (array size -bc stage="tMaxrestoreInsertBefore && "parentBB should have a terminator".framepushtofhcmp_kindloadOriginrd.lbasecurCallableDataPointeralloc && "GEP of non-alloca pointer"rd.asp.hi.rbc (LineAdj) (Triangle) (GLES2)stackNestingLevel: numTexSamInLoop: compMask: instanceIDRegID: compMasks[extraLocalMemorySize: clipPlanes[relPatchIDRegID: zrhWEnableMask: textureID: ConstSwizzleZ: fastColorBypass: patchedTextureSlotIndexBase: [ADRENO_BINDLESS_EMULATION_MAPPING_RANGE][bindlessTypes[[GL_SYMBOL_INFO_SAMPLER] (Ver hasUnsizedArray: arrayDimensions: shaders[[ADRENO_SHADER_CBUFFER_USAGE].usesPushConstants.usesUAVs[ADRENO_CBCACHE].physicalRegisterPrecision.needsMergedShaderInfo[A4X_VSDS_MERGED_SHADER_DESC].inputControlPointCount.clipPlanes[ADRENO_HS_INPUTS].needsPrimitiveAttributeBuffer.preferredWaveSize.coverageMaskRegID.ConstSwizzleY.yuvCSCStandard.castUniformsToFloat[GL_SYMBOL_INFO_IMAGE].uboInfo.useUAVSlot.isSamplerForFBFetch.matrixStrideInBytes.component[ADRENO_DESCRIPTOR_USAGE_INFO].regIdVS Unable to load shader codeSECT_IMM_CONST_BUF_TABHeader mismatch, skipping the rest of the diff. - None - tcinv : %8d output_sizewave_sizes - Early Preamble : %8d tex.befkilltex.getsizemem.ldib_rpt,num_runs,arch,acc16bitModeUse64BitAddrDumpBCFileDisableHSPrimWriteCheckEnableAlphaToCoverageEnableMultiPositionOutputForceWaveSizeDisableDummyNonperspectiveIJPatchingFilterStatsFreeShaderMemoryCallbackQGLC_MaxUniformBuffersnumStaticSamplersshaderSizeQCC_BindlessSlotType ASICFamily (TargetData::ASICFamilyA4x): Which ASIC family to compile for (needed for GL) Unable to parse EnableTexturePromoteWA value 'Unable to parse DX11ShaderBinary value 'Unable to parse PrevStageGLIRShader value 'Unable to parse SkipParse value 'Unable to parse GenerateMissingBindGroupData value 'Unable to parse DisableHSPrimWriteCheck value 'Unable to parse EnableLMSpilling value 'Unable to parse SingleTriangleMode value 'Unable to parse EnableA7pAlias value 'Unable to parse EnableTextureHighpWA value 'Unable to parse ForceConstantRAMMode value 'Unable to parse FetchFrameBufferViaSP value 'Unable to parse EnableFilterCubicPatching value 'Unable to parse EnablePackSmallWorkGroup value 'Unable to parse EnableSignedImmInALU3 value 'Unable to parse EnableSignedExtensionInLDST value ' DisableInitialBary (false): Disable Initial bary optimization DisableDynamicCBCaching (false): Disable constant buffer caching for dynamic accesses (may be unsafe) EnableProfiling (false): Enable stats generated by the profiler ShaderName (__null): name of shader file HighestBankBit (14): The highest bank bit used for a tiled resource, used to generate addresses for tiled UAVs. EnableUGPR (false): (a5x+) enable u GPR. ForcePerFiberPvtMemLayout (false): True: use per fiber layout for private memory, overriding compiler default DisableCentroid (false): Replace centroid with center interpolation, useful if not using MSAA RT. BGECount (0): Size of the bind group element structure stride RotationShaderPatching (false): Enable GL rotation DisableYUV (false): Disable YUV ReserveSharedConstant (false): Don't use the shared constant registers for normal constants ForceHighpExpFunctions (0): Force highp for exp functions ForceHighpCommonFunctions (0): Force highp for common functions DisableVersionCheck (false): Disable gl linker version checks EnableMixedPrecALU3 (): Enable mixed precision inputs and DC (dest conv) on output for ALU3 instructions. SamplerHeapBindlessBase (): where the compiler accesses sampler descriptors RayPipelineDebugPointerHigh (): Internal-only, enable writing launch ID to this memory location at the beginning of each shader (high bits). Expected format of VerTok,SizeInDWORDS,Code for DX11SB value. A613 A305 UNKNOWN-ELEMENTpEmulatedGroupsPtr + pEmulatedGroupsDesc->m_ElementSize * i && "memcpy dest pointer is NULL!" These fields are only used by one symbol type. They can be put into union. Version 1.0: Added symbolInfoType Added namedConstInfo Added samplerInfo Added atomicCounterInfo Added uboInfo Added inputOutputInfo Added ssboInfo Added imageInfo Version 1.0: Added numSymbols Added pSymbols QGLC_METADATA_IRSHADER: - Top level output data for compile when target is intermediate object. - Part of the input data for Link. Notes - shaderType is copied over from QGLC_SRCSHADER. Input shader type is also embedded in shader object bits. Making it a member here is for fast link time shader type checking and processing. Version 1.0: Added shaderType: Shader type Added shaderHandle: Shader object bits Added shaderSize: shader object size in bytes Added shaderVersion: Shader Version Added shaderEntryPoint: Shader entry point Added metadataHandle Version 1.1: Added shaderSignature: Shader output signature Data for all shaders that precede the rasterizer/stream out. Version 1.0: Added outputsPosition: True when the shader exports position. Added positionRegID: Scalar Reg ID assigned to position.x. Version 1.1: Added outputsPointSize: True when the shader exports point size (GL only). Added pointSizeRegID: Scalar Reg ID assigned to point size. Version 1.2: Added positionVirtualRegAndComp: Virtual register location for position output (vreg * 4 + comp). Added pointSizeVirtualRegAndComp: Virtual register location for point size output (vreg * 4 + comp). Version 1.3: Added positionVPCIndex: VPC Index for position. Added pointSizeVPCIndex: VPC Index for point size. Version 1.4: Added outputsShadingRate: True if the shader exports VRS primitive shading rate. Added shadingRateVPCIndex: VPC Index for VRS primitve shading rate. Data describing the location of a single clip plane in a constant buffer. This is a 4-component, 128-bit value located cbOffset bytes from cb[cbSlot]. For DX11, cbOffset will always be a multiple of 16. Version 1.0: Added cbSlot: The slot of the constant buffer containing the clip plane. Added cbOffset: The byte offset of clip plane in the constant buffer. This is a container for the ADRENO_R24_UNORM_PATCHING_READ structure. Version 1.0: Added numReads: How many texture reads may be patched. Added textureIndices: A bitmask of all texture indices that could be patched if using an R24_UNORM resource with a point-sample sampler. Added samplerIndices: A bitmask of all sampler indices that could be patched if using an R24_UNORM resource with a point-sample sampler. Added reads Data describing input target. For each target, driver needs the following info been reported back Version 1.0: Added inputTargetIndex: input attachment index to the previous subpass. Added set: binding set Added binding: binding offset Added textureSlot: t# allocated by Driver Version 1.1: Lets the driver know which bindless bases are accessed in the shader. Version 1.0: Added usedBases: Which bindless bases are referenced Added scratchBufferSize: Size of the compiler's scratch buffer used for writing descriptors, if enabled (ret != NULL) && "context not set yet?"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/QCC/Context.cppQCC Pack PS InputsDomain Shader found, use LoadObjectFileDXDS 0123456789newlineleft-square-bracketright-square-bracketshiftAmt <= BitWidth && "Invalid shift amount"*no default*' specified.llvmDW_TAG_subrange_typeDW_TAG_unspecified_typeDW_ATE_lo_userDW_ATE_hi_uservendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Support/MemoryBuffer.cpp%*u %-*s - %s ,timer!wall_time!%.4fTotal oxilipatch <= 255 / = Tex2D!{ ] memory_scope_cross_subgroup uniformx86_stdcallcc arm_apcscc <>_pipe_ ptr && "out of memory!"pass-remarksEnable optimization analysis remarks from passes whose name match the given regular expressionllvm.arm.mcr2llvm.arm.neon.vacgedllvm.arm.neon.vpadalsllvm.arm.neon.vrhaddullvm.arm.neon.vrshiftnllvm.hexagon.A2.addh.h16.sat.hlllvm.hexagon.A2.addh.l16.llllvm.hexagon.A2.maxupllvm.hexagon.A2.vminhllvm.hexagon.C4.cmplteuillvm.hexagon.F2.conv.uw2dfllvm.hexagon.F2.dffmallvm.hexagon.F2.sfaddllvm.hexagon.F2.sfimm.pllvm.hexagon.M2.hmmpyl.rs1llvm.hexagon.M2.mmpyuh.s0llvm.hexagon.M2.mpyd.hl.s0llvm.hexagon.M2.mpyud.nac.lh.s0llvm.hexagon.M2.vcmac.s0.sat.illvm.hexagon.M2.vcmac.s0.sat.rllvm.hexagon.S2.asl.r.p.andllvm.hexagon.S2.asl.r.p.nacllvm.hexagon.S2.asl.r.r.nacllvm.hexagon.S2.asr.i.p.accllvm.hexagon.S2.asr.i.r.andllvm.hexagon.S2.lsr.i.p.xaccllvm.hexagon.S2.lsr.r.p.accllvm.hexagon.S2.shuffehllvm.hexagon.S2.tableidxb.goodsyntaxllvm.hexagon.S2.vsplatrbllvm.hexagon.S4.ntstbit.illvm.hexagon.S5.asrhub.satllvm.hexagon.S5.vasrhrnd.goodsyntaxllvm.opencl.get.image.width2dllvm.opencl.read.image1.fllvm.opencl.vstore.half8llvm.opencl.write.image1aullvm.opencl.write.image3llvm.ppc.altivec.mtvscrllvm.ppc.altivec.vcmpgtub.pllvm.ppc.altivec.vmaxuwllvm.ppc.altivec.vminswllvm.ptx.read.tid.yllvm.qcom.s322f16llvm.qcom.u162u32llvm.qgpu.atomic.and.oobllvm.qgpu.atomic.dec.oobllvm.qgpu.atomic.umax.oobllvm.qgpu.fchkptllvm.qgpu.fcombine16llvm.qgpu.fcombine3llvm.qgpu.fcreate.map2llvm.qgpu.get.dynamic.offsetllvm.qgpu.get.rt.stbl.baseaddr.raygenllvm.qgpu.icombine49llvm.qgpu.iload.componentllvm.qgpu.interp.atllvm.qgpu.l2gllvm.qgpu.private.addr.calcllvm.qgpu.signllvm.qgpu.store.raystackllvm.qgpu.subgroup.iquadshufflellvm.qgpu.uav.resfmtllvm.rs.get.globalsllvm.spu.si.andbillvm.spu.si.ceqbllvm.spu.si.ceqhllvm.spu.si.fmsllvm.var.annotationllvm.x86.3dnow.pfrcpllvm.x86.avx2.pabs.dllvm.x86.avx2.pbroadcastd.256llvm.x86.avx2.phsub.wllvm.x86.avx2.pmovzxwqllvm.x86.avx2.pmulu.dqllvm.x86.avx2.psllv.d.256llvm.x86.avx.maskload.pd.256llvm.x86.avx.vtestnzc.psllvm.x86.sse2.maskmov.dqullvm.x86.sse3.addsub.psllvm.x86.sse41.movntdqallvm.x86.sse41.pmovzxbqllvm.x86.sse.ucomilt.ssllvm.x86.xop.vpcomfalseuqllvm.x86.xop.vpcomgedllvm.x86.xop.vpmacsswdllvm.x86.xop.vprotwllvm.xcore.setpscextractvalueCause a memory leak in the LLVMContext object to verify leak detection.isVoidv4i8v2i64More than one parameter has attribute nest!Referencing global in another module!Type too small for ZExtFPExt only produces an FPClause is not constant!Alias and aliasee types should match!NO_APP$a. .indirect_symbol .org .cfi_def_cfa_register .seh_savexmm ')Offset DW_CFA_offset_extended_sfTLVP__debug_str.rodata.rodata.cst4.ctors .linkonce same_size mod_term_funcsnoneMisaligned saved register offset!invalid native integer size 'coslexp2lpowpowlmCurrentLLVMModule && "Init Lang: LLVM module doesn't exist"rhsValllvm.loopAlias Analysis Analysis counted: mod/ref responses ( no alias responses postdomonlyiv-usersNumber of GetElementPtr instsNumber of Fence instsNumber of FPToUI insts ScalarNumber of PtrToInt insts ScalarNumber of factorizations------------------------------------------------------------- lintUnusual: unreachable immediately preceded by instruction without side effects Pairwise dependence results: Number of cached, but dirty, non-local ptr responsesGlobalVariable: Verify profiling informationprint regions in detail with block_iterator(sext enable-tbaavaluetracking.knownzero.maskMaximum CGSCCPassMgr iterations on one SCCstrncpyvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/LoopUtils.cppLoop exit-block-insertion failedNumber of loops unrolled (completely or otherwise)setjmp.catchstackptr.restoreExtractElem && "llvm ExtractElement IR generation failed\n"Number of IV identities eliminatedUnifiedRetValtcOpenGL GS Lowering PassSimplifyVectorAllocaThe maximum number of pairing iterationsbb-vectorize-max-cycle-check-pairsbb-vectorize-no-mathslp-vectorizerpreHeaderTerminator && "Pre-Header terminator can't be null"for.end.memsetOuterLoopIndexVar && "OuterLoopIndexVar is NULL".lr.phWill not try to unroll partially because partial unrolling not enabledloop-unswitch-thresholdDisable induction variable type promotion.vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/CodeGen/MachineInstr.hNumber of dead instructions deletedunwind_resumeNumber of spilled live rangesvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/ADT/IntervalMap.h(i == Size || Traits::stopLess(b, start(i))) && "Overlapping insert"STRegAliasmachine-sink-splitMBB exits via conditional branch/fall-through but the CFG successors don't match the actual successors!AnalyzeBranch returned invalid data!Debug instruction has a slot indexIllegal physical register for instructionInvalid definition indexDefining instruction does not modify registerInstruction ending live range doesn't read the register components in ocamldisable-code-placeenable-mischeddisable-postra-machine-licmPrint LLVM IR input to isel passprint-gcStackRegister AllocationEmit Debug Infofast register allocatorvectorize-mayvec(ExtraRegInfo[Intf->reg].Cascade < Cascade || VirtReg.isSpillable() < Intf->isSpillable()) && "Cannot decrease cascade number, illegal eviction"Enable use of AA during MI GAD constructionMax number of calls in a block for MIschedulingScheduleDAG::viewGraph is only available in debug builds on .contSpill Code Placement AnalysisAdditional instructions due to tail duplicationmachine-branch-probcombiner-global-alias-analysis SoftenedFloatsTrack register pressure and switch priority to in-depthcouldn't allocate output register for constraint 'RETURNADDRfgetsignaddecallseq_startvacopyctlz_zero_undefsetultsetuneunknown intrinsic #"]; X__ashlhi3__lshrti3__umodti3__truncdfsf2__floatundidfError at end of type table blockInvalid metadata kind IDInvalid instruction with no BBenable-gvn-before-loopenable-ldc-return-type-unificationsplit.cl.program(groupOpModeVal == 0 || groupOpModeVal == 1 || groupOpModeVal == 2) && "Invalid groupOperation Specified".loopUnified Expansionqgpu-enable-prera-ssa-destructionllclib: error: run out of registersQgpuSelect the a5x_64 processorHR13_aHR37_bHR47_bHW_A0HW_A1HW_PCHW_TREG16IR20IR50R14_aR22_aR24_dR29_bR30_dR34_bR40_bR45_bSAM10SAM11UAV36UAV50UR6_cImageWriteRC], g[gefalse && "Invalid instruction class"SrcOpd.isReg() && "Invalid operand type"QGPU::orQGPU::rcpqgpu.use.denorm.libCustom lowering code for this instruction is not implemented yet: %d CandidateNode && "Expecting a valid DT node"MF == MI->getParent()->getParent() && "Ensure we only visit curent function"numElements <=32 && "Incorrect number of return elements detected"false && "A forward-declared operand mustbe an instruction"PromoteAllLDCUButuniformKernel CFG: ------------------- INext && "Some instruction(s) should follow after the current vec instruction")"; I && "Instruction is null"enable-qgpu-lraenable-qgpu-grafalse && "Unsupported constant kind!"$DX_empty_vec4Set the maximum number of yields (<=8)false && "No global variable info."_CL_global_offset0 && "opencl_work_group_size_hint without enough parameters"llvm.nonnegative_offset.enablefalse && "Wrong atomic image intrinsic operation type"b16(ei)braasamgqgetbufstg.ag2latomic.dec.lnatomic.cmpxchg_assert0 && "Unknown fixup instrution!"__qcom_DXMetaInfoToo many const registers md != NULL && md->getNumOperands() == 1 && md->getOperand(0) != NULL In inst# : is not allowed in the ISA spec.SrcRegRelOffsetError: No program end instructionHalf precision registersdot-sched,fontcolor=red,fontsize=20.0QGPUInstrInfo::isTextureInstruction(B) && "B should be a tex!"QGPUUndefInitializationfalse && "OutDefMI is NULL!"DefInstr && "DefInstr is NULL"(FinalUsers[i] && MRI->getRegClass(FinalUsers[i]->getReg()) == &QGPU::FullRCRegClass) && "All Final User Must have same RegClasses"false && "invalid cmp mode"QGPU Collect CallGraph information for Kernel FunctionMI && "Null instruction"QGPU Local Register Allocatorv != NULL && !isa(v) && "Invalid emulated instruction"%5s = LI->getReg() >= Base && "unexpected vector vreg id"SpillInstSlot < SplitSlotIdx && SplitSlotIdx < AllocInstSlot && "Sanity checking failed"pseudoExitBlock != NULL && "Could not find back edge source basic block\n"QGPUGlobalRegAllocRC && "Unknown register class in LM Spiller rewrite"uppf-no-scastDefMI && "No DefMI"LDST: Destination operand type can be sGPR only for LDC instructionthe stthr.a instruction should use g with dst. Usage g[r4.x+32] LDST: Source offset Out of Range with g2l instruction. Allowed Range is 8bits, |0 - 255|STIB: for src baseid 6/7 reserved for a6x and aboveLDIB: offset val should be in [0, 127]LDIB.A: Valid Data Types are u32/s32/f32/u16/s16/f16LoadStore: for shfl instruction allowed only from a6x ALU2 CAT32: DST can be 32 bit only.SCT - This instruction cannot be repeated EFU:Source0 Operand can not be located in Constant Register Texture: .1D modifier with ISAM cannot be used along with .o or .3d or .a optionsPATCH4PATCH9PATCH11dcl_output_control_point_count is allowed with HS onlyCONSTANTDEPTHGREATEREQUALMIXEDRAW_BUFMAXSINSTRBRAINSTRLOADGS16INSTRLOADTHRAF16INSTRLOADXAF16INSTRLOADLU32INSTRSTGENS16INSTRSTTHRAS16INSTRSTXF16INSTRG2LU32INSTRATOMADDLS32INSTRSTLWU8INSTRFENCEGLINSTRATOMADDGGPUU32INSTRATOMANDGENGPUU32INSTRATOMXCHGGGPUS32INSTRATOMINCRGGENGPUU32INSTRATOMCMPXCHGGGPUS32INSTRATOMBDECGNU32INSTRATOMBAADDGS32INSTRATOMBAADDGS321D1LINSTRATOMBSUBGS323DINSTRATOMBAMINGS321D1LINSTRATOMBAANDGS321DINSTRATOMBORGS322D1LINSTRATOMBCMPXGS323DINSTRATOMBINCGU322DINSTRATOMBINCLNGS32INSTRATOMBINCLNGU323DINSTRATOMBAINCRGGU323DINSTRATOMBADECGS321D1LINSTRATOMBADECGS322D1LINSTRATOMBDECGU322D1LINSTRATOMBDECGU323DINSTRATOMBDECLNGS323D1LINSTRATOMBDECRGGU323DINSTRATOMBDECRGGU323D1LINSTRRSQINSTRATOMINCRGGS32INSTRADDHU32INSTRSWZF32S16INSTRSWZF32S32INSTRDBZTOKENATOMORGENS32INSTRLDIBTYPEDS321DINSTRLDIBTYPEDF161DTINSTRLDIBBLKLU162DINSTRLOADLBLKF16INSTRSTIBAF161DTINSTRLDIBF163DRCKINSTRLDIBAU161DINSTRGATF16INSTRGATU32S32INSTRGATS32U16INSTRSCTU32F32INSTRCHAR_KDECLARE_CB_DESC_STORE_MAPSOURCE_REPEATCOMP_IDFLOWDESTLOADGENINSTRCMPOPCODESELINSTRSHRLGINSTRTEX_INSTR_3_2TEXTURE_MODIFIERSHADER_TYPEDCLICBVAL1syntax error, unexpected %s, expecting %s or %sALU3: Source1/Source2 modifier can not be abs. ALU3: destination convert is not supported for this instructionUnknown ArchType... Picking a5x as defaultALLOCATIONADRENO_CBCACHE_ENTRYA4X_VSDS_MERGED_SHADER_DESCADRENO_ASTC_PATCHING_STATIC_READADRENO_ASTC_PATCHING_INFOGL_SYMBOL_INFO_IMAGEADRENO_MS_OUTPUT_DESCMAX_FRAGMENT_IMAGE_UNIFORMSMAX_GEOMETRY_INPUT_COMPOENTSOES_TEXTURE_STORAGE_MS2DARRAYIMPLICIT_CONVERSIONSMaxOutputBlocksMaxTessControlInputComponentsMaxComputeAtomicCounters Name : 0x%08xfalse && "valid hw bindless type is expected."GL_UNSIGNED_INT_VEC3GL_SAMPLER_2D_RECT_SHADOWQGL_TEXTURE_3D_OESGL_UNEXPECTED_TYPE flags = InstanceIOBlock, format = %s precision mismatch with other stage. interpolation mismatch with other stage.(pos2 != llvm::StringRef::npos) && "Assert Index:[49] invalid TF name"ROImage:$FragCoordRotMat2$FSFoveationParametersVec4$PointSizeFovScaleFactorFloat32ArrayTransform Feedback Buffer 2 Base Pointer (32-bit)Tessellation Patch Tess Factor Outer SizeDisable Transform Feedback for A3xAn array of offsets for subpass frag coord fov patching(component == 0) && "Assert Index:[31] && HW symbols and TF should be in channel 0"(mStage < QGPUCompiler::ShaderStages::NumShaderStages) && "Invalid mStage value!"enableInstancePackingusePerPixelDerivativeenableScalePointSizeenableUseTextureForLargeUBOisAssembleShader============ OPT BC ============ llvm.exp2.f32llvm.qgpu.floor.f32llvm.qgpu.rcp.f32llvm.qgpu.global.fget.reg.v2f16.p0f32llvm.qgpu.global.fget.reg.v3f16.p0f32llvm.qgpu.global.iset.reg.p0i32.v4i32llvm.qgpu.fcreate.map4.v4f32.f32llvm.qgpu.sign.f16llvm.qgpu.stlw.i32llvm.qgpu.stlw.v4i32llvm.qgpu.iadd.sat.i32tesDSGV != NULLBinning - clone module__qcom_BARY_Coordinate_centersampleIDVal && "sampleIDVal is Null"srcME->getIndexInst() != __null && "Array index is missing!"!"Invalid matrix size"llvm.qgpu.image.load.v4%s.p0i32.%sblock &&"Invalid block."src->getType()->isPointerTy() && dst->getType()->isPointerTy()vMisco.ray.oriinst.custom.idxblendModulateextractInst && "extractelement instruction is expected!"fieldCount <= typeListSizesrcFn && "OpTypeRayQueryProceedKHR is not supported"getMissShaderId__qcom_BARY_Coordinate_centroid_j__qcom_BARY_Coordinate_sample_non_persp_j(mSymbolObjectMap.get() != NULL) && "Cannot alloc symbol object map"qgpu.tcs.output.read.backfalse && "Unexpected symbol location type"qgpu.read.only.imageptrValgvInfoIt != symInfoMap->end() && "Unable to find GV info in the map"Enable promote shared variable to local memloc && "Location cant be Null"false && "Invalid Image Format for generating ISAM in LowerNamedPointers.cpp"mCBLocInfo.mCBLocationMap.get() != NULLintToPtr && "intToPtr isNull"pValue->resourceIdentityType == QGLC_SPECIALIZATION_IDENTITY_TYPE_NAMEgl_InstanceIDgl_MaxVertexAttribsgl_MaxComputeAtomicCountersgl_MaxFragmentAtomicCounterBuffersgl_MaxGeometryTextureImageUnitsgl_MaxTessControlImageUniformsgl_ShadingRateFlag4VerticalPixelsEXTsamplerCubeShadowtextureCube__textureExternal2DY2YEXTfalse && "setFbFetchDepthSampler called on invalid object"srcEle && "incompatible casting"resultAddr != __null && "Logical Expression Result Address is Empty!"$sampler_sym!isLeafNode && "array indexing node a[i] cannot be a leaf node"uniformType->getStruct() != __nullbaseNode && idxNodesamplerVarsS2unpackHalf2x16texelFetchOffsetQGLC parser initializationQGLC parseCompute is only available in ES3.1 or above-=/=endifno operation '%s' exists that takes an operand of type %s (or there is no acceptable conversion)can't modify a default Uniform Block membercan't modify gl_MaxFragmentImageUniformscan't modify gl_MaxComputeImageUniformscan't modify gl_MaxGeometryUniformComponentscan't modify voidNon-zero positive array size needs to be specifiedvarying struct and member qualifier mismatchsamplers specified with subsampled layout can only be used with texture2D function.atomic memory function argument is not shared/SSBO variablegl_PerVertex member name is wrong!Unexpected storage qualifier!samplerType->isSamplerOrTexture()GL_KHR_shader_draw_parameters!"wrong matrix size"Branch Node found in constant constructor%d:? Bitwise NotfwidthComma Construct mat3x4Read PixelTexture2DShadowProjOffsetTexture2DArrayShadowGradImageLoad3DImageStore2DMSArrayblockMatchSADQCOMBranch: BreakDivide by zero error during constant foldingMod by zero error during constant foldinggl_FragDepthbreak statement only allowed in loop and switch statementsmat3can only undef an identifierifndef needs an identifier#pragma directive must end with a newlineExtension directives must occur before any non-preprocessor tokens.16 bit denorm preserve not supported on current HW_$id_false && "Matrix type to be supported yet\n"srcOPME->getSize() == 2 && "src expected to have two components"dstVecTy && srcVecTy && (dstVecTy->getNumElements() == srcVecTy->getNumElements())OpTypeMatrixOpTypeForwardPointerOpGroupMemberDecorateOpImageSampleExplicitLodOpImageQuerySizeLodOpFConvertOpOuterProductOpDotOpDPdxCoarseOpMemoryBarrierOpGroupAnyOpMemoryNamedBarrierOpGroupNonUniformBitwiseOrInvalid SPIR-V module: magic numberQGPU State Function Transform Passstate.idgetNumRaysToDisatpchcommit.hitLoadRCpop.framePCSshader.table.stridemailbox.slot.addrgetOutUIntsprev.stack.framerd.lbasecurPayloadPointertmpvec (RWBuffer) (InternalCBPtr) (Gather4R) (GLES31)id: minVGSv: uavUsageMask: uavReadMask: ]: [ADRENO_GENERIC_SYMBOL][clipUsageMask: isControlPointBypass: patchConstTessFactorSize: localSizeZ: [SHADER_TYPE] (Ver dynamicTextureMappings[textureIndex: textureIndices: isReversed: gathers[extracts[mappings[numBindlessTypes: [ADRENO_BINDLESS_MAPPING_DATA][bindlessRWBufferSupport: needsInnerCoverage: binding: primSizePerVertex: isUsed: isSamplerForBlending: numLocations: numDescriptorGroupsInBinning: ([ADRENO_HW_SPECIFIC]*) shaderHandles: bindlessBaseUsage: screenCoordTexUsages: .constantBufferUsageMask.outputsPosition.pointSizeVirtualRegAndComp.needsPrimitiveID.fragCoordEnableMask.needsViewID.foveationQualityRegID.useEarlyDepthStencil[SHADER_TYPE].wgIDUGPRIndex.initialIJCoordinate.isReversed[ADRENO_PATCHED_R24_UNORM_TEXTURE].numMappings.numFullConstRegistersUsed.useBindlessUAV.needsFramebufferTime.descOffsetInDescTable[ADRENO_DYNAMIC_CBCACHE].isIOBlockArray.blockLayout.ioBlockName.numConstColorOutputEntries.primitiveAttrSizePerWorkgroup[ADRENO_NAMED_SHADER_HANDLESV2].shaders.maxPayloadSizeInBytesArch type mismatch BinningMeshAmplificationShader - rpos : %8d - dsxpp : %8d - conv_pp : %8d - stpsize : %8d - EI Position : %8d - Long sync flags : %8d - CBs needing OOB : %8d preamble_texld_rptmem.preamble_ldc_rptDisableLLVMOptFragDataBindingBufferRefBGECountBGESamplerStrideVulkanPatchCPCountEnableBindlessImageVMAssertonNoSymbolEnableAliasForLDSTErrataNumber' ignored. RangeRESOURCE_SIGNATURE_INLINE_CONSTANTSdescriptorData0resourceIdentityTypeCBuffername="Error parsing frag data tag data: Error parsing input attachment tag data: Currently available ASICFamilys are: Unable to parse ASICID value 'Unable to parse SkipCodeGen value 'Unable to parse RelaxExtensionPPCheck value 'Unable to parse DisableSharedConstantForCS value 'Unable to parse EnableBindlessAccelerationStructure value 'Unable to parse AllCompilerOptions0 value 'Unable to parse EnableWarnings value 'Unable to parse ScratchBindlessReservedMask value ' DriverData (__null): driver data to save in program binary StageAvailableConstLimits (0): Set available full vec4 constant registers for one shader stage. Only takes effect if ConstantRangeDriverAssigned is true. Otherwise the compiler decides the constant distribution. DisableLineAAIfNotLines (false): (QNGC) Disable PSAA lines when not rendering lines EnableSWViewMask (false): Enable view mask emulation for multi-view EnableUnifiedScheduler (false): Enable unified instruction scheduler EnableRTAndVPIncrFlags (false): Enable changes that let more shaders use HW stereo rendering using the RT and VP increment flags DoBinningVS (false): Enable binning for the VS only FetchFrameBufferViaSP (false): Use LDIB to load data from FrameBuffer ForceHighpTrigFunctions (0): Force highp for trig functions VulkanPatchCPCount (0): set the control point count for vulkan MaxPayloadSizeInBytes (): from maxPipelineRayPayloadSize. PipelineCreateFlags (): from flags field in VkRayTracingPipelineCreateInfoKHR, QCC_PipelineCreateFlags --> QGLCCompile A507A690" structureSize="Invalid initial texture opcode, error in compiler-generated metadata. Dynamic size mismatch, unable to fill out metadata. Version 1.0: Added offset: offset layout qualifier Data describing how the CS executes. Version 1.0: Added reuseGPRMode: Whether registers are shared between SP threads. Added hasBarrier: Whether the shader contains barrier synchronization. Added preferredWaveSize: True if compiler thinks shader can benefit from running twice as many pixels per wave. Added localMemoryUsedBytes: How many bytes of local memory are used by the CS. Added kernelDim: How many dimensions there are to the thread group. Added localSizeX: The size of the thread group's first dimension. Added localSizeY: The size of the thread group's second dimension. Added localSizeZ: The size of the thread group's third dimension. Version 1.1: Added disableTiledWIRasterization: True if complier thinks tiled rasterization need be disabled. Version 1.2: Added packFactorX: The num of work group packed in X dimension for small workgroup packing. Added packFactorY: The num of work group packed in Y dimension for small workgroup packing. Added packFactorZ: The num of work group packed in Z dimension for small workgroup packing. Version 1.3: Added lpacTooSlow: true if number of instruction is > 1024. Information about each stream out buffer to be written to. Version 1.0: Added vertexStride: The size of a vertex written to this buffer. Added bufferIndex: Which buffer this description applies to [0,3]. An entry in ADRENO_DESCRIPTOR_USAGE_INFO For the following resource: Texture2D tex2[4] : register(t3) baseShaderRegister is 3 then relDescOffset of tex2[2] is 2 = 5 - 3 and descriptorCount is 1 (static indexing) relDescOffset of tex2[idx] is 0 = 3 - 3 and descriptorCount is 4 (dynamic indexing) Version 1.0: Added slotType: The HW slot type being allocated Added bindlessIndex: bindless Index Added descriptorSetOffset: bindless descriptor Set Offset. For DX it is baseDescOffset(bge->elementOffset) + relDescOffset(lowerbound - bge->baseShaderRegister) Added descriptorCount: num of Descriptors. Always 1 for static indexing case and bge->elementCount - relDescOffset for dynamic case. Added readwriteMask: Bit pattern signifies Read Write Usage. Per-pipeline mask if needUsageInfo is true. Version 1.1: Added elementType: only for DX, resource type since slot type in DX is different from ESX/VK. Unknown Shader type found, library needs to be updated. [:>:]]tabSOSIapostropheasteriskempty (sub)expressionvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/ADT/ArrayRef.hDisplay the version of this programDW_TAG_template_value_parameterDW_TAG_class_templateDW_LANG_Fortran95false. -===qgpu_64spu = type LowLevelFBppc_fp128 atomic[ x86_stdcallcc ptx_kernel ninfExpected mangling specifier in datalayout string [local] Actual: .pllvm.arm.ldrexdllvm.arm.neon.vst1llvm.arm.neon.vtbl2llvm.arm.neon.vtbx1llvm.atomic.load.minllvm.ctlzllvm.dbg.callstackllvm.dbg.inlinedfunctionreturnllvm.hexagon.A2.addh.h16.sat.llllvm.hexagon.A2.negllvm.hexagon.A2.subrillvm.hexagon.A2.svadduhsllvm.hexagon.A2.vaddubllvm.hexagon.A2.vcmpweqllvm.hexagon.A2.vmaxwllvm.hexagon.A4.cmpbgtuillvm.hexagon.A4.round.rr.satllvm.hexagon.C2.cmpgtupllvm.hexagon.F2.conv.uw2sfllvm.hexagon.F2.sfsubllvm.hexagon.M2.acciillvm.hexagon.M2.cmpys.s0llvm.hexagon.M2.mpy.rnd.lh.s0llvm.hexagon.M2.mpyu.acc.hh.s0llvm.hexagon.M2.naccillvm.hexagon.M2.vrcmaci.s0cllvm.hexagon.S2.asr.r.p.orllvm.hexagon.S2.insertllvm.hexagon.S2.lsr.i.r.nacllvm.hexagon.S2.svsathbllvm.hexagon.S2.vtrunohbllvm.hexagon.S4.extractllvm.hexagon.S5.popcountpllvm.hexagon.SI.to.SXTHI.asrhllvm.invariant.endllvm.opencl.write.image2aullvm.opencl.write.image2ullvm.ppc.altivec.lvsrllvm.ppc.altivec.vcmpbfp.pllvm.ppc.altivec.vlogefpllvm.ppc.altivec.vmaxsbllvm.ppc.altivec.vmhaddshsllvm.ppc.altivec.vsum4ubsllvm.ppc.altivec.vupklpxllvm.qcom.s322u32llvm.qgpu.chshllvm.qgpu.extract.lollvm.qgpu.fcombine35llvm.qgpu.fcombine37llvm.qgpu.fcombine56llvm.qgpu.fcreate.map61llvm.qgpu.get.kek.profiling.buffer.regllvm.qgpu.get.spidllvm.qgpu.get.tensor.heightllvm.qgpu.icombine44llvm.qgpu.icombine55llvm.qgpu.icombine63llvm.qgpu.icreate.map63llvm.qgpu.iread.temp.regsllvm.qgpu.ldx.compare.exchange.strong.stxllvm.qgpu.roundazllvm.qgpu.scalellvm.qgpu.sub.group.ballot.bit.countllvm.qgpu.sub.group.syncllvm.qgpu.subgroup.fquadshufflellvm.qgpu.unroll.beginllvm.spu.si.norllvm.x86.3dnow.pavgusbllvm.x86.3dnow.pfcmpgellvm.x86.avx2.pmadd.ub.swllvm.x86.avx2.vbroadcasti128llvm.x86.avx.dp.ps.256llvm.x86.avx.vtestc.psllvm.x86.bmi.bzhi.32llvm.x86.fma4.vfmaddsub.pdllvm.x86.fma4.vfnmadd.pdllvm.x86.fma4.vfnmsub.psllvm.x86.mmx.packuswbllvm.x86.mmx.pandnllvm.x86.mmx.pavg.bllvm.x86.mmx.pcmpeq.wllvm.x86.mmx.pmaxu.bllvm.x86.sse3.monitorllvm.x86.sse41.pminuwllvm.x86.sse41.pmovsxdqllvm.x86.sse41.round.sdllvm.x86.sse.cvtsi2ssllvm.x86.xop.vpcomnewllvm.x86.xop.vpcomtrueuqllvm.xcore.chkctbitcastboth values to select must have same typedbgtbaaPrint IR after specified passesvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/VMCore/PassRegistry.cppf64v4i16v8i32v8i64vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/PassAnalysisSupport.hAttributes after last parameter! only applies to parameters with pointer type!Function has metadata parameter but isn't an intrinsicAlloca array size must have integer typeInvalid number of indices!Expected value type does not match pointer operand type!ZExt only operates on integerIntToPtr Vector width mismatchA @@ version cannot be undefinedFK_Data_8 .quad .desc.eh_frame @code .cantunwind .personality <>Imm: .linkonce discard 0123456789_.abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ%physregacosasinfexpm1lfloorlinvariantpartial alias' functiondomNumber of FMul instsNumber of Xor instsNumber of AddrSpaceCast insts ScalarNumber of InsertValue instsUndefined result: sub(undef, undef)Pessimization: Static alloca outside of entry blockdependentNonFuncLocalmodule-debuginfo: Error opening 'verify-region-infoView regions of functionUnpredictable backedge-taken count. indvarvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Analysis/UniformityAnalysis.cppUniformityAnalysisvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/HLC/QGPUSymbolInfo.hNo target informationNode && "Contorl Dependency: Cannot find branch join point"Break critical edges in CFGsavedstackeh.lpad-bodyoldjmpbufptrGEPI && GEPI == Inst && "the address of Store must be from GEP\n"OldTI && "DomBlock->getTerminator() is NULL"allowExtOpenGLWorkaroundsval && "Null Val"arr != NULL || arrData != NULL || arrZero != NULLaggTy && "Dynamic cast to StructType failed"bb-vectorize-no-pointersbb36-vectorize-search-limitllvm.large_buffer.enableNumber of iterations.maskednotlhssadd.overflowadcecodegenprepare.offsetNumber of uses of [s|z]ext instructions optimizeddce.pre-phi.leInterchanges loops for cache reusereroll-aggregatevendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Scalar/PostIncrement.cppdisable-pcleIn && "Expecting instruction"Number of multiplies factorededge-bundlesNumber of reloads removedMachine Block Frequency Analysisblock-placement-statsmachine-cpNumber of common subexpression eliminatedpred: flags: Number of machine instructions hoisted out of loopsMBB exits via unconditional fall-through but doesn't have exactly one CFG successor!MBB exits via unconditional fall-through but has a condition! where valno #phi-node-eliminationDisable the probability-driven block placement, and re-enable the old code placement passdisable-machine-sinkPrint LLVM IR produced by the loop-reduce passAfter PostRegAlloc passesAfter Machine LICM, CSE and Sinking passesBreak post-RA scheduling anti-dependencies: "critical", "all", or "none"post-RA-schedPrologue/Epilogue Insertion & Frame FinalizationfastAttempt coalescing during PBQP register allocation.stress-regallocNTRI && "register info is not available"cleanup.lpadfuncnameBasicInfoprint SR sets for each iterationfn_contextVerify sanity of PHI instructions during tailduptailduplication ScalarizedVectorslist-burrlist-hybridDisable no-stall priority in sched=list-ilpNumber of physical register copiesvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpplimit-float-precision<getParent() && "Ensure we only visit curent function"0 && "Forward-declared operand not present"false && "invalid intrinsicFunc"promote.ldcGV && "Invalid gv"I->hasOneUse() && "GEP for aggregateConst should have one use"bindlessno-nop-insertion0 && "Casting to different address space not supported in bitcast"false && "Unsupported sign extend \n"RC != NULL && "Null register class"!isHalfReg(op0Reg) && !isHalfReg(op1Reg) && !isHalfReg(op2Reg) && "sad instruction is in a wrong format"false && "cannot compute gv size for oob (no gv info)"false && "Invalid sampler type"UAVID < 256 && "Src2 ID overflow"false && "Unsupported intrinsic in pattern\n"DstType->isVectorTy() && "UAVImageRead: image.load type NOT vector"0 && "Unknown ImageType"4.0add.fxor.bclz.bmovppredtldg.aldlatomic.b.inc.lnatomic.b.andatomic.b.ordcfluOnly one source operand of ALU2 can be located in constant memory0 && "Src2 of shfl needs to be immediate val"Exceeded limit of the number of GPRqgpu.previous.vertex.sizeqgpu_image_attachmentImmUndefinedTypeError: is not allowed.undefined, but registers are required.ISA opcode Full RegisterFixed registersTemporaryqgpu-sched-scenarioUseI && "Uses must all be casts"cmp-sel-enableEnable remvoing unnecessary saturation MIRsenable-dche0 && "wrong rc!"MovMap[SrcRegi] && "MovMap[SrcRegi] is not initialized"OldDefMI && "OldDefMI is NULL"!"unimplemented"false && "Potential conflict"MI.getNumExplicitOperands() == MCID->getNumOperands() && "Each instruction's parent must be the current basic block"FurthestUseSlot >= MIInfo.SlotIdx && "Invalid slot idx"getPhyReg(LR->Reg) == 0 && "Already assigned"_hi_result_hillvm.qgpu.subgroup.reduce.int.v2i32false && " should be ptr type"_sum0 && "non-rematerializable reg encountered"RCIdx < NumRegsInRC[RCID] && "out of index"Allocating registersRC && "Unknown register class in LM Spiller colorSpills"Consider long queue instructions for promotionQGPU Wavesize stats collection passIBaryMI && "Empty def!"FLOW: predicate inversion is not allowed for predicate instructions with a target WARNING: LDTHR.a with RRI form only allowed from a7p LDST: Out of Range Offset with ldthr.a+ instruction. Allowed Range is 9 bits, |0 - 511|LDST: For destination operand type GPR, allowed regNum range 0 to 47LDC: for legacy src2 should be IMM for a6x and above LDST: Out of Range Offset with ldgen instruction. Allowed Range is 13bits, |0 - 8191|. LDST: Out of Range Offset with stx.a+ instruction. Allowed Range is 9 bits, |0 - 511|ATOMIC.b: for src mode0/4 src2 should be IMM for a6x and aboveSTIB: Source2 should always be Immediate/GPR Value LDIBBLK(L|C): for src mode0/1/2, baseid ignored for a6x and aboveLoadStore: for shfl instruction src1 should be GPR or IMM STSC: src0 is out of range. Allowed Range is 0 - 159Source Operand Out of Range for 16Bit half Signed DataType.Only allowed Range is -32768-32767Texture: img pcmn s34 should be enabled Texture: .rck/.clp/.s34options are only allowed for texture fetch instructions(*sam*, conv*, gather*)The sGPR number should be between 48 and 55OXILIMONOdcl_inputfloat*PIXELDOMAIN_TRIwriteADDFDIV2INSTRMULFDIV2INSTRCOVS16S32INSTRLOADTHRCCHEF32INSTRLOADTHRAU16INSTRLOADXF32INSTRG2LF16INSTRLOADLWS16INSTRLOADGBU1DU32INSTRLOADGBAU2DS32INSTRSTGB2DINSTRFENCEGRWINSTRSTKSINSTRATOMINCGENGPUS32INSTRATOMXORGENGPUS32INSTRATOMINCRGGENSOCS32INSTRATOMBANDGNU322DINSTRATOMBAMINGU323DINSTRATOMBAMAXGU323DINSTRATOMBCMPXGU321D1LINSTRATOMBCMPXGU323DINSTRATOMBACMPXGS321DINSTRATOMBXCHGGNU642DINSTRATOMBXCHGGS321DINSTRATOMBAXCHGGS321DINSTRATOMBINCLNGS322DINSTRATOMBDECRGGS321DINSTRATOMBDECRGGS323D1LINSTRISAMINSTRSAMDP2INSTRAROMINCRGLU32INSTRATOMXCHGLF32INSTRLDIBS323DINSTRSTIBS321DTINSTRSHRM32INSTRDP2ACC32INSTRDP4ACC32INSTRMOVSU16INSTRMOVSU16F32INSTRMOVSF32U32INSTRLDIBUNTYPEDU323DRCKINSTRSTIBUNTYPEDF323DINSTRSTIBTYPEDF161DINSTRLDIBBLKLU322DINSTRLDIBBLKLF162DINSTRLDIBBLKGF322DINSTRLDIBBLKCS163DINSTRLDIBAF162DINSTRGATF32INSTRGATU16F16INSTRSCTU8S16INSTRSCTU32S32INSTRPIPRWRITEINSTRSHFLDOWNW4U32INSTRSHFLUPW8U16INSTRINVLOG2TOKENLCURLYDECLARE_TOPODECLARE_CS_ThreadGroupLocalXDECLARE_CS_ThreadGroupLocalZDECLARE_CS_ThreadGroupOffsetRegDCL_PS_TEX_ENTRY_DSTDATATYPEDECLARE_CL_CL2_FEATUREPREDIREGMREG_TOKENMEMID_NAME_TOKENSTGBAINSTRLDCKINSTR_SYNCGETBITINSTRDCL_CL_REGDCLVAL3ALU3: Source1 Operand cannot be Relatively AddressedFLOW: Destination operand of FLOW cannot be in sGPRbindlessRangesvsA4X_MERGED_SHADER_INPUTSglueCodeDesctcsDesctcsInputsvsBinningTESSELLATION_SHADER====E031.41.03.64====MaxVertexUniformVectorsMaxTessEvaluationTextureImageUnitsMaxTessEvaluationAtomicCounters enableBindlessRWBuffer="true" enableBindlessSampler="true"BuiltInOutputGL_UNIFORM_BUFFERGL_IMAGE_CUBEGL_UINT_IMAGE_BUFFERGL_UINT_IMAGE_2DGL_UINT_IMAGE_CUBE_ARRAYQGL_UNSIGNED_INT_TEXTURE_2D_MS outShaderCnt = %u VIDMask = 0x%x GlobalScratchSize = %dqgpu.invariant.fragcoordfalse && "Assert Index:[28] unscoped UBO/SSBO member do not have parent symbol"Helper values to compute binCoord for subpassvertex shader foveation parametersmdNodes && "Assert Index:[33] namedMDNode should not be Null here"ASIC Chip IDenableUGPRenableDeviceIndexAsViewIndexuseMSAARenderTargetforceBuiltinsforceUniformllvm.qgpu.global.fset.reg.p0f16.v2f16llvm.qgpu.fcreate.map10.v10f16.f16llvm.qgpu.iabsneg.i32llvm.qgpu.icombine2.i32llvm.qgpu.fcreate.map3.v3f16.f16llvm.qgpu.clzs.i16llvm.atomic.load.umax.i32Error: Bindless AccelerationStructure are supported on a740 aboveWARNING: qglnext_tes_io!((opnd->getSymbol())->getFlags().bitfields.isOutParameter)basePtrType && "basePtrType is NULL!"dynamic indexing case unhandled for matricesindex->getType()->isIntegerTy()srcME->getSize() == 2$constRam_framebufferTimeqInst != NULLinsn && "Dyn_cast to Instruction failed"resultVal && "incompatible type casting"src->getType()->isPointerTy()ty && "ty is null"hit.tVH_ && "OpRayQueryGetIntersectionObjectRayDirectionKHR" " is not supported"$setupBaryN_i_over_wglLayerValue && "gl Layer is Null"false && "expected get symbol location intrinsic"mGSIOMap.get() != NULLallocstore && "store is Null"load && "GS output is set to reg"partitionCount != 1this->GetArrayDimensions()->at(0) == (unsigned)(this->GetArraySize())FragDataPatchVerticesIngl_MaxGeometryAtomicCounterssampler2DShadowNV21 samplerExternalOESiimage3DGenBinary: symbol %s, map offset %d, uboLoc %8x false && "addFbFetchSampler called on invalid object"sampleIDSymswitchBody && "switch body AST type is not correct!"(containerDim == ST_UNIFORM_BUFFER) || (containerDim == ST_STORAGE_BUFFER)this->isMatrix()uimg2diimgcinversesqrtuintBitsToFloatunpackUnorm4x8QGLC parser state initializationclip cull planes exceed limit!vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/opengl/gl_parser/MachineIndependent/PoolAlloc.cppescan't modify gl_PrimitiveIDcan't modify gl_MaxFragmentAtomicCounterBufferscan't modify gl_ShadingRateFlag2VerticalPixelsEXT cannot assign tolayout qualifier value had been setup multiple times with different value.blending layout qualifier is not supportedunsized array is not allowed for function returnfunction name redefines a non-function global namearray parameters dimension size mismatches.cannot apply dot operator to an arrayPatch out is allowed in tessellation control shaders onlyGL_EXT_YUV_targetGL_EXT_texture_cube_map_arrayGL_EXT_shader_implicit_conversionsGL_QCOM_framebuffer_clockRight shift Assign >>=arc sineFloorNotEqualDot ProductImageAtomicXorconst intgroupMemoryBarrieratomicCompSwapcan not specify binding id for a SSBO without struct bodymust not redefine builtinsextension 'all' cannot have 'require' or 'enable' behaviormacro argsidSymbol && "sid symbol is expected"pointerTy && "pointTy is not PointerType in handleSpecCompositeConstruct"OpSampledImageOpImageSampleDrefImplicitLodOpImageFetchOpSConvertOpGenericCastToPtrOpEndPrimitiveOpAtomicCompareExchangeWeakOpAtomicOrOpAtomicXorOpImageSparseGatherOpImageSparseDrefGatherOpCopyLogicalFunction not found for shader vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/raytracing/RayPipelineCompiler.cppstackIntPtr$qgpu.misc.const.mailboxstategetCalledFunctionName(payloadStackPtr).startswith("stack.ptr")cfoffset0ray.stack.offsetWgetRayInfoSBTHGStridedir.xtrv.stack.offsetcacheState.updatedMailboxCountOffset.elnext.offset (PointList) (D3DRootTable)unsigned char[[ADRENO_SHADER_TEXTURE_USAGE] (Ver dynamicallyIndexesSamplers: numVectorALUInst: [A4X_MERGED_SHADER_INPUTS] (Ver clipPlanes: facenessRegID: localIdRegID: disableTiledWIRasterization: bufferByteOffset: ]: [ADRENO_R24_UNORM_PATCHING_READ] (Ver [ADRENO_R24_UNORM_PATCHING_INFO] (Ver bindlessTextureSupport: viewIDRegID: enableSPMLMode: [GL_PROGRAM_DATA] (Ver [GL_SYMBOL_INFO_ATOMIC_COUNTER] (Ver samplerInfo: parentUBOSizeInBytes: bindlessIndex: descriptorCount: readwriteMask: rcInfo: ([ADRENO_BINDLESS_USAGE_INFO]*) [ALLOCATION].nonBufferUavReadMask.useWithoutFormatUAVMask.compMask.vertexCountRegID.instanceCount.fragCoordRegID.pointSpriteUVVirtualRegID.packedFragcoordXYRegID.outputsCoverageMask.vsdsgsOutputs.buffers.fastColorBypass.initialTexBypass[ADRENO_ASTC_PATCHING_DYNAMIC_READ].apiBindlessGroup.numEntries.mappings.patchConstantSize.numLocations.vertexPayloadSizePerWorkgroup.constRegUsageTES============ DCB ============ - ALUs : %8d,%8d (rpt), ratio %5.2f - Half EFUs : %8d,%8d (rpt), ratio %5.2f movehalf_move - MIN : %8d,%8d (rpt), ratio %5.2f - array : %8d - proj : %8d - itex*const : %8d memory - emit : %8d,%8d (rpt), ratio %5.2f - ldpsize : %8d - ldlsize : %8d - Sync Instrs : %8d - Scratch space : %8d tex.gatherRtex.gpixelmem.ldgenmem.stibmem.ldgba_rptmem.ldgamem.getspidHalf precision register footprint per shader instanceMemory read instruction countSpecializationStageMaskPtrSpecializationResIdentityPtrPrevStageGLIRShaderOutputBinningObjectFileDumpObjFileSkipMetadataVerificationSingleTriangleModeEnableSWViewMaskDisableImplicitConvReserveSharedConstantSimulateVariableRateShadingEnableBindlessSamplerTFDataVaryingsSRefEnableDP4ACCWithSignedWeightsAllocateShaderMemoryCallbackQGLC_MajorVersionIDQGLC_MaxImageUnitsRootUAVresourceNameRTCOMPILERINTERNALpStagesbitdepthunsizedArraySizeIndexTessFactorBufauxBindGroupElements Unable to parse Shutdown value 'Unable to parse UCHETrapBaseLo value 'Unable to parse Quiet value 'Unable to parse EnableConstMulTexture value 'Unable to parse StageAvailableConstLimits value 'Unable to parse RTIndexValues value 'Unable to parse EnableLegacyCBPreloadViaPreamble value 'Unable to parse FilterStats value 'Unable to parse MaxPayloadSizeInBytes value ' FragDataSize (0): Size of the bind group element structure stride DumpMetadataToDebug (false): Dump generated metadata to debug callback AvailableGprLimits (__null): Set available full vec4 GPRs for each stage. If NULL, then defaults are VS,HS,DS,GS: 48, PS,CS: 32 SingleTriangleMode (false): Tell compiler if it is single triangle mode or not ABGEData (__null): Array of bind group elements EnableASTCPatching (false): Enable patching for ASTC EnableSafeNormalize (false): Generate normalize code that is less likely to overflow EnableSingleBindlessBase (false): allow a single bindless base with offsets from UBO EnableFilterCubicPatching (false): Enable foveation patching for fragment shader builtins EnableBindlessAccelerationStructure (false): allow bindless acceleration structure usage A503A616A740Compare UAV metadata against symbolsNo Flow Meta desc Unexpectedly high sampler index in patching metadata. Unable to get Stream out Buffer entry. Which constant buffers are referred to in the shader. Note that this data is not valid for shaders using bindless, since the indexing used for bindless has no analog here. The driver has the actual resource layout in this case. Version 1.0: Added constantBufferUsageMask Data specific to VS input registers. Version 1.0: Added needsInstanceID: true when the shader requires an InstanceID. Added needsVertexID: true when the shader requires a VertexID. Added instanceIDRegID: Scalar Reg ID assigned to Instance ID. Added vertexIDRegID: Scalar Reg ID assigned to Vertex ID Version 1.1: Added needsVertexCount: true when the shader requires a VertexCount. Added vertexCountRegID: Scalar Reg ID assigned to Vertex Count Version 1.2: Remove dummyField to avoid size change of total structure. Added needsDrawID: true when the shader requires a DrawID. Added needsBaseVertex: true when the shader requires a BaseVertexIndex. Added needsBaseInstance: true when the shader requires a BaseInstanceIndex. Added drawParametersRamLocation: Vec4 based constant RAM location assigned to DrawParameter stage=FFUScommaexynos9810: can't create temporary directoryrwlock != 0Print all option values after command line parsingintDW_TAG_base_typeDW_TAG_template_type_parameterDW_TAG_function_template --System Time--cygwinmingw32%e to arcp contractone acquireblockaddress(vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/DerivedTypes.hTy && "Null argument to getTrue"print-dbginfoDominator Tree Constructionllvm.arm.neon.vmullsllvm.arm.neon.vqshiftnullvm.arm.neon.vrsqrtsllvm.arm.qaddllvm.convertsullvm.hexagon.A2.combine.hlllvm.hexagon.A2.sathllvm.hexagon.A2.subh.l16.sat.hlllvm.hexagon.A2.subsatllvm.hexagon.A2.tfrpllvm.hexagon.A2.vabswllvm.hexagon.A2.vmaxubllvm.hexagon.A2.vminwllvm.hexagon.A4.vcmpbeq.anyllvm.hexagon.C2.cmpgtullvm.hexagon.C2.cmpltullvm.hexagon.F2.sfimm.nllvm.hexagon.M2.mmachs.s1llvm.hexagon.M2.mmacls.s1llvm.hexagon.M2.mpy.rnd.hh.s0llvm.hexagon.M2.mpyud.nac.hl.s1llvm.hexagon.M2.vdmacs.s1llvm.hexagon.M2.vradduhllvm.hexagon.M2.vrcmpyi.s0cllvm.hexagon.S2.clbnormllvm.hexagon.S2.lsr.i.r.orllvm.opencl.prefetchvllvm.ppc.altivec.lvewxllvm.ppc.altivec.vadduwsllvm.ppc.altivec.vcmpeqfp.pllvm.ppc.altivec.vselllvm.ppc.altivec.vsrabllvm.ppc.dcbstllvm.ptx.read.lanemask.gellvm.ptx.read.lanemask.ltllvm.ptx.read.pm0llvm.qcom.barrierllvm.qcom.f162f16llvm.qcom.u322u32llvm.qgpu.bfrevllvm.qgpu.calculateprtuavoffsetllvm.qgpu.create.handle.for.lib.illvm.qgpu.fcmpxllvm.qgpu.fcombine19llvm.qgpu.fcombine30llvm.qgpu.fcombine44llvm.qgpu.fcreate.map23llvm.qgpu.ichkptllvm.qgpu.icombine19llvm.qgpu.icombine31llvm.qgpu.icombine39llvm.qgpu.icombine48llvm.qgpu.icombine61llvm.qgpu.icreate.map10llvm.qgpu.local.addr.calcllvm.qgpu.mulshillvm.qgpu.opencl.image.loadllvm.qgpu.selgtllvm.qgpu.shrmllvm.qgpu.sub.group.matmulllvm.spu.si.mpyhhllvm.spu.si.mpyullvm.x86.3dnow.pfrsqrtllvm.x86.avx2.mpsadbwllvm.x86.avx2.pmins.dllvm.x86.avx2.psrl.dllvm.x86.avx2.vbroadcast.ss.psllvm.x86.avx.cvtt.ps2dq.256llvm.x86.bmi.pdep.64llvm.x86.fma4.vfmsubadd.ps.256llvm.x86.mmx.paddus.wllvm.x86.sse2.cvtpd2dqllvm.x86.sse2.lfencellvm.x86.sse2.pavg.wllvm.x86.sse.comilt.ssllvm.x86.sse.cvtps2pillvm.x86.xop.vfrcz.ps.256llvm.x86.xop.vpcomeqqllvm.x86.xop.vpmacsddandvector select requires selected vectors to have the same vector length as select conditionTwo passes with the same argument (-Cannot find option named 'v16i8Preliminary module verificationResolver && "Pass has not been inserted into a PassManager object!"Called function must be a pointer!Incorrect number of arguments passed to called function!GEP is not of right type for indices!PtrToInt result must be integralAddrSpaceCast result must be a pointer'. It should be '.note.GNU-stack .lazy_reference .weak .size .cfi_restore_stateinvalid .org offset 'sdata4indirect pcrel sdata4GOTOFFSECREL__mod_init_func8byte_literalsself_modifying_codeJust Ref <-> Ref Block Frequency Analysis error opening file for writing!digraph unnamed { done. Number of Ret instsdisable_simplify_divlibcall-aaExact SIV applicationsExact SIV independencern***COULDNOTCOMPUTE***qgpu.enable_fsinstance_packingllvm.sjljeh.jmpbuftysimplifycfg-dup-retbb-vectorize-max-iterDon't try to vectorize floating-point valuesincomingTerminator && "Terminator can't be null!"bin.rdxAllow instructions to be vectorized even if they span across a callRes && "Res is NULL"sadd.resultDisable branch optimizations in CodeGenPrepareOptimize for code generationpromote.to.bufferdseNumber of loops rotatedPrecomputing Loop Expressionsqgpu.has.zeroinitializer.array!state.isVectorReplNumber of block tails mergedMI && "MI is NULL!"Pop up a window to show edge bundle graphs Successors according to CFG:Potential frequency of taking unconditional branches0 && "Register used without definition"RegAggRegMayVecMultiple connected components in live intervalDisable Post RegallocDisable pre-register allocation tail duplicationDisable code placementAfter copy propagation passfoundReg && "Could not find space for reserving regs"NumSplits > 0 && "Must have at least one split point"Enable aggressive QGPU coalescingBefore register coalescingNumber of identity moves eliminated after coalescingprint basic DF setsprint all DF setsInsert stack protectorsSrcVNIdisable-sched-hazardNumber of instructions aggressively commutedvirtregmapIndirect operand for inline asm not a pointer!FRAME_TO_ARGS_OFFSETmulhsconcat_vectorssign_extend_inregfp_to_sintsetne)> [ID=DAG Combining 1__modqi3__fixsfqi__ltsf2__sync_val_compare_and_swap_2__sync_fetch_and_xor_2' is too large for the ocaml GC! Live root count Invalid BB ID in VST_BBENTRY recordInvalid CST_INTEGER recordInvalid CE_SELECT recordInvalid CE_SHUFFLEVEC recordInvalid MODULE_CODE_DEPLIB recordTy && "Type to enumerate can't be null!"Control the amount of inlining to perform (default = 225)tesDSGV != nullptrfalse && "Intrinsic is null"false && "source operand is null for Quad Shuffle Operation"promote ocl pointer argument to image buffer NonCriticalEdgePHIAccessCount: Enable Pre-RA SSA Destrcution for Workaround Disable Pre-RA SSA Destrcution HR3_dHR7_bHR11_aHR20_aHR20_cHR30_dHR43_cHR44_bHR45_bHW_NULL2IR18IR32IR40IR107IR124IW3R2_cR6_aR15_cR21_bR32_dR35_aR39_dR43_bR46_cSAM22SR6_dSR7_bUAV43UR1_bFullCC(absneg)false && "Register is neither physical nor virtual"QGPU::ICMPgeQGPU::FCMPgtvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUISelLowering.cppExitBlock && "Exit block not valid!"!isMAD && "No Mad instruction expected in early preamble"FirstSrcPhyReg != 0 && "Invalid dst and src mapping"false && "Invalid TD operand type" (nopfalse && "invalid cmpi"origOpd != NULL && "The first parameter of llvm.dbg.* function can not be NULL"QGPULiteralLoweringCBIdentifyMD->getOperand(2) && isa(CBIdentifyMD->getOperand(2)) && "incorrect MD layout"Enable constant buffer cachingfalse && "Cannot create virtual registers for Value object"(scalarBits & 0x7) == 0 && "scalarBits must be a power of 2"false && "Unsupported zero extend \n"_CL_divided_global_size_CL_event_queue_reg!isHalfReg(op2Reg) && "mad instruction is in a wrong format"LDCKSize != 0!isHalfType(I->getOperand(1)->getType()) && "i32 is expected."NewOffWeightReg && "failed to create new registers for offset and weight"0 && "unknown image intrinsic"opcode && "atomic opcode is not set, unexpected address space"false && "Sleep cycles should be no greater than 512.".packed(high)and.bmul.umul.sshr.bsad.s32shrm.b16rbildx.aldg.kshfl.genalias.memMI->getOpcode() == QGPU::END && "The last instruction must be END"QTM->get_stack_size() < 0 && "evaulated stack sizes in wrong order"tex.OffsetEn == 0 && "OffsetEn should be 0 here"clMI->getOperand(NumDefs).isSymbol() && "No asm string?"qgpu_const_color_output_dataCountconstData && "const data is a null ptr "QGPUInstrInfo::getInstrClass(*MI) == QIC_ALU2QGPUInstrInfo::getInstrClass(*MI) == QIC_ALU3FImmRangeError: SrcModNotAllowedError: NoCvtF32I16InSALUInA650Error: A6x HW Errata #217AddrModeOffsetNotAllowedError: Register or Integer ImmediateDMOD.UNDEFINEDfalse && "This type not yet supported for ldg.a"GEPI && "Pointer is NULL"Set a ratio to decide if a function is ALU-dominated or notEnable dead channel eliminationDistanceFromMI >= 0 && "Use before def!"max-cse-numsrc3Loc.valid() && "FAKEMOVA1 used by instruction without src3"MOVDstOpd.isReg() && "MOV can have only register for destination"UseMI->getParent() != entryBlock && " Cannot have remaining uses in entry block"max-aliasrtqgpu-dce!FirstDstNode->IsMem && !FirstSrcNode->IsMem && "Cyclic edges must have only register nodes"false && "invalid cmpi instruction"obit_loQGPUEmulateTargetRegisterInfo::isPhysicalRegister(PReg) && "Invalid physical register"%16uInvalid hint on output instructionsNumber of operands with redundant vector hintuppf-min-promotionsCasting a uGPR to a GPR is always profitableMIAfterWhichToInsert && "MIAfterWhichToInsert is NULL"itex-check-kill LDST: Out of Range Offset with ldthr instruction. Allowed Range is 13bits, |0 - 8191|. LDST: Out of Range Offset with stthr instruction. Allowed Range is 13bits, |0 - 8191| LDST: Source offset Out of Range with l2g instruction. Allowed Range is 13bits, |0 - 8191|ATOMIC.b: for src baseid 6/7 reserved for a6x and above LDIB.A: Out of Range Offset with ldib.a instruction. Allowed Range is 8bits, |0 - 255|. LDG.k: Out of dest range size with ldg.k instruction. Allowed Range is 12 bits, |0 - 4095|ALU2 CAT32: DST is 32 bit but all source operand are not 16 bitmad.m32 supported on A8X+ onlySource Operand Out of Range for 16Bit Signed DataType.Allowed Range is -2147483648 - 2147483647 Texture: Only dst is allowed for only for RGETINFO instructionTexture: broadcast.active dst type should be a GPRISAM: Valid .offset modifier value is between 0 to 255 Dummy register number should be 63Declare Constant instruction should be dcl_constFLOAT*PATCH12dcl_instance_count is allowed with GS shader onlybyteBARYPERSPSAMPLETHREADIDPSIZENONPERSP_SAMPLEHS_FLAGSMINUINSTRMULSLOINSTREQOPCODECMPSSINSTRCOVS16S16INSTRLOADGF32INSTRLOADGS32INSTRLOADTHRU32INSTRLOADXF16INSTRSTGS16INSTRL2GU32INSTRL2GS32INSTRLOADPU8INSTRLOADGBAT1DF32INSTRLOADGBAT2DF32INSTRLOADGBAT3DS32INSTRSTGBA1DINSTRATOMDECLNGENGPUU32INSTRATOMINCRGGENSOCU32INSTRATOMCMPXCHGGSOCU32INSTRATOMBDECGNU323DINSTRATOMBSUBGU322D1LINSTRATOMBAMINGU321D1LINSTRATOMBMAXGS32INSTRATOMBAANDGU321DINSTRATOMBORGU323DINSTRATOMBAORGS322D1LINSTRATOMBXORGS322DINSTRATOMBXORGS322D1LINSTRATOMBXCHGGNU321DINSTRATOMBAINCGU323DINSTRATOMBADECRGGS321D1LINSTRATOMBDECRGGU32INSTRSELS16INSTRMOVA0UINSTRSQRTINSTRAROMDECLNLS32INSTRATOMINCGU32INSTRATOMINCGS32INSTRSTIS16INSTRSTIBAF322DINSTRSTIBF321DTINSTRMOVPINSTRMOVSU8S16INSTRLDIBUNTYPEDU163DINSTRLDIBUNTYPEDS162DINSTRSTIBTYPEDF321DINSTRLDIBF161DINSTRLDIBAF161DTRCKINSTRGATU16U32INSTRSCTU16F16INSTRSCTU16U32INSTRGETFIBERIDS16INSTRGETFIBERIDF16INSTRIMGBINDLESSINSTRCOMMAUNKNOWN_TYPESIGNED16TOKENDCL_CL_GROUP_ID_TOKENDCL_GLOBALLOGETOKENHALFINVLOGETOKENDECLARE_VERTEX_SIZEDCL_NUM_BARY_COR_TOKENFENCE_INSTRFLOWINSTRLOADCBINSTRLOADGBINSTRALU2_MODIFIERSOURCE_MODIFER2ALU3: Destination Operand cannot be Relatively AddressedMOV/COV: For INVSR instruction, src0 operand of should be sGPRFLOW: Destination operand of FLOW cannot be dummy registerTEXTURE: Destination can not be Relatively addressed.gsOutputsextractstextureMappingsADRENO_GENERIC_SYMBOLA4X_GS_MERGED_SHADER_DESCADRENO_PATCHED_STATIC_ASTC_TEXTUREbinningInfoOutputNULLMaxTessControlTotalOutputComponentsMaxTessControlAtomicCountersMaxAtomicCounterBindingsMaxComputeSharedMemorySizeisBindlessAccelerationStructurecount%02xUniformBlockArrayGL_FLOAT_VEC4GL_UNSIGNED_INT_VEC4QGL_INT_TEXTURE_2D_ARRAY flat, sampler4Gather, InsideStruct, IOBlock Idx = %d(src || !count) && "Assert Index:[65]" location or component mismatch with other stage.InputTarget:Transform Feedback Buffer 0 Base Pointer (32-bit)Atomic counter buffer stridePointcoord Rotation Matrixprecision != EvpqUndefined || dimension == ST_STRUCTuse64BitAddrenableUnSafeMathvalidateLinkResultdisableSharedConstantForCSenableStateCacheWarmInPreamblecommon_functions2false && "Unknown shader type!"llvm.qgpu.trunc.f16llvm.qgpu.dsy.f16llvm.qgpu.global.fget.reg.v4f32.p0f32llvm.qgpu.global.scalar.iset.reg.p0i32.i32llvm.qgpu.global.iset.reg.p0i32.v3i32llvm.qgpu.icreate.map3.v3i32.i32Error: Only VS, TES and GS shaders in SSO mode can have transform feedback.Error: Linking failed.mCompileData &&"cant be null ptr"__qcom_BARY_Coordinate_sample_non_perspsym && "no image symbol?"lhsVSize > 1getWorldRayDirvCenterWgl_SubgroupGeMaskVH_ && "OpRayQueryGetIntersectionInstanceShaderBindingTableRecordOffsetKHR" " is not supported"Adreno-SCioblockNamevPrim && "vPrim is Null"cbLoc->cbSlot == QGLNEXT_DEFAULT_UBO_INDEXfalse && "Unable to allocate texture slots"it != mSymbolObjectMap->end() && "Unable to find downgraded symbol metadata node in map"false && "Encountered unsupported input/output category"insertPos && "insertPos is null"cst.bitdepth < numFormatBit && cst.encoding < numS2vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/codegen/OpenGLSpecialization.cpppValue->resourceValueSize >= numOfElements * sizeof(unsigned int)InterfaceBlockIngl_MaxGeometryOutputVerticesstructureWritting to a read-only variable!isDstRowMajor!dstTy->isVectorTy() && !srcTy->isVectorTy()src_sourceOverdstOp && samplerOpparam$formalidxNode && idxNode->getAsConstantUnion()innerIdxNode && innerIdxNode->getAsConstantUnion()sCAimg2dmsaiimg2drradiansclampnormalizeequalnotgl_PerVertex.gl_PointSize# Strings = %d !table.empty()!stack.empty()__FILE__' : can't modify gl_MaxCombinedImageUniformsIO Block wrong declarationbarrier() can't be called in flow control.the location is not in supported DrawBuffers range [0, MAX_DRAWBUFFERS-1]Invalid atomic counter bindingInvalid precise/invariant declaration on non-writeable varLeft shift << Most significant bitConvert mediump/lowp to highpConstruct bvec2TextureCubeShadowTexture2DShadowOffsetImageLoadCubeArrayImageStoreCubeArrayMemoryBarriertargetCoordsample qualifier is not allowed with GL_QCOM_shader_framebuffer_fetch_rate extensionUTEXTURE1DSAMPLER1DARRAY#elif after an elseInvalid hexadecimal constantEOF found inside commentComment is too longch == '\0'Extended instruction PackDouble2x32 not supportedmultiple entry points match((width == 16) || (width == 32)) && "unexpected DenormFlushToZero operand"Invalid SPIR-V module: ends prematurelyOpConstantTrueOpVariableOpFDivOpFUnordGreaterThanOpPhiOpBranchOpGroupSMinOpReadPipeOpEnqueueMarkerOpGetKernelNDrangeSubGroupCountOpGetKernelWorkGroupSizeOpImageSparseFetchOpGroupNonUniformAllEqualStateFunctionTransformprerayidnwici1ret.stateIdStoreRCWithResumerayid.addrrd.lbasefloats!m_contCtxFramePush && "m_contCtxFramePush not cleared"committed.hit.grpdepth < 10 && "too large a depth"cmp_base (CCW) (LessEqual) (InputTarget)majorVer: metadataDesc: minVGSMem: numScalarALUInst: sourceVec4Offset: neededRegisters: cullUsageMask: outputPrimitive: [ADRENO_PS_GENERATED_INPUTS] (Ver outputsCoverageMask: zOutputRegID: stencilOutputRegID: wgIdConstID: rasterizedStream: wgOffsetUGPRIndex: uvVirtualRegAndComp: numEmulatedGroups: offset: isBoundedToTF: isSamplerForGather: name: declaredArraySize: [ADRENO_IMAGE_ATTACHMENT_DATA_ENTRY] (Ver numImageAttachmentDataEntries: descriptorSetOffset: [ADRENO_SHADER_COLLECTION_SUBSTATE_INFO] (Ver skipProcedural: .usesCBs.icb[ADRENO_INPUT_SYMBOLS].positionVPCIndex.needsFoveationQuality[ADRENO_GS_PER_STREAM_OUTPUTS].bufferByteOffset[ADRENO_BOOLEAN_CONSTANT_EXPRESSION].emulatedGroups[ADRENO_BINDLESS_DATA].viewportIndexIncr[ADRENO_BINNING_INFO].isReadOnly.isWriteOnly.dataType.precision.stackSize.hasCrossWaveCommunicationSECT_IMM_CONST_BUF_TAB[ - ldg : %8d,%8d (rpt), ratio %5.2f - ldlw : %8d,%8d (rpt), ratio %5.2f - stlw : %8d,%8d (rpt), ratio %5.2f - stib : %8d,%8d (rpt), ratio %5.2f - PREDT Instrs : %8d - Wavesync : %8d sgpr_footprint - per uSPTP : %8d - Full Registers : 0 tex.shadowtex.imgtex.hoftex.itexconsttex.preamble_imgtex.preamble_inittexmem.g2lmem.l2gmem.stgenmem.resbasemem.preamble_stcProgramBinaryResultDriverDataResultEnableDynamicCBCachingReservedLocationNamePtrInputAttachmentInfoCountASICFamilyASICCHIPIDForceDoubleWaveSizeEnableA6xColorSpaceConversionFetchFrameBufferViaSPForceHighpTrigFunctionsSOGEVirtualLocationPtrABTexDescriptorOffsetSamplerHeapBindlessBaseQNGC_MinorVersionID> QGLC_SPECIALIZATION_CATEGORYdescriptorSetOffsetcolorSpaceTransform="auxDescType="Unable to parse FastCompilation value 'Unable to parse EnableSingleRegisterPool value 'Unable to parse DisableInitialBary value 'Unable to parse DumpBCToDebug value 'Unable to parse ISSCommand value 'Unable to parse EnableUnifiedScheduler value 'Unable to parse BGEDataBufRef value 'Unable to parse DisableYUV value 'Unable to parse EnableBindlessImage value 'Unable to parse IsGotcha value ' EnableSingleRegisterPool (false): Enable single register pool ClientID (ClientData::ClientIDD3D11): Client API being used SpecializationInfoCount (0): number of resources to be specialized EnableSingleCommandStreamBinning (false): (a6x+) enable single command stream for binning ShutOffUAV (false): Tell compiler there is no UAV usage so that compiler can use the reserved 64 vec4 constant registers for UAV EnableR24UnormPatching (false): Enable patching for R24 Unorm reads IsDynamicConstRange (false): const range is dynamically determinced by the linker VM32BitBindlessIndices (): VM 32-bit indexing into bindless data ', couldn't find end of tag A420A520 A405 A613 A623 Size:0x:0xb64#Unable to allocate shader device memory, no callback available. pUsagePtr + pUsageDesc->m_ElementSize * i && "memcpy dest pointer is NULL!" Holds miscellaneous information about the program compiled Version 1.0: Added numViews Added isAdvancedBlendingEnabled: populated from FS Version 1.0: Added unsizedArrayOffset: offset for unsized array in SSBO Added unsizedArrayStride: stride for unsized array in SSBO Added textureFormat: store E_QGLC_GLSL_IMAGE_LAYOUT value enum? Defines a dynamically sized bitfield used to identify usage masks. Any bits larger than the number of words are assumed to be zero. Version 1.0: Added numWords Added words This includes all information necessary to execute texture fetches in hardware before the pixel shader begins execution. Version 1.0: Added initialIJWriteDis: Disables the IJ write to GPRs for the initialIJCoordinate. Added initialIJCoordinate: Which barycentric coordinate to use for interpolating initial texture U/V coordinates. Added numLoads: Number of initial texture loads (0-7, limited to 4 for a5x). Added loads Version 1.1: Added endOfQuad: True if all bary instructions are initial bary instructions. Version 1.2: Added constColorBypass: True if const bypass is enable in the PS shader(A6x+) . Added constSlotID: full precision vec4 constant RAM slot used for const color bypass or tex*const. Version 1.3: Added fastColorBypass: True if fast bypass is enable in the PS shader(A6x+) . Added initialTexBypass: True if initial texture bypass is enable in the PS shader(A6x+) . Version 1.4: Added constant3rdCoordEn: True if 3rd coordinate is enabled(A7p). Added constSlotID4Coord: full precision vec4 constant RAM slot to read texure array indices when constant3rdCoordEn is true. E031.41.03.64 Unsupported deferred query. abcdefghijklmnopqrstuvwxyzETXform-feedIS2less-than-signvertical-lineinvalid character rangemutex != 0vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Support/Mutex.cppDisplay all available optionsDW_TAG_entry_pointDW_TAG_formal_parameterDW_TAG_ptr_to_member_typeDW_TAG_interface_typeDW_TAG_namespaceDW_TAG_arg_variableDW_ATE_unsigned_fixedr600kfreebsdIO failure on output stream.x86_fp80ule xor imageappending alias readonly Print fullpath when printing debug infoUnknown specifier in datalayout stringllvm.arm.thread.pointerllvm.atomic.swapllvm.convertfuillvm.exp2llvm.hexagon.A2.addh.h16.lhllvm.hexagon.A2.subh.h16.sat.llllvm.hexagon.A2.svsubhsllvm.hexagon.A2.vavghllvm.hexagon.C2.cmpgtuillvm.hexagon.C4.fastcorner9.notllvm.hexagon.F2.dfimm.nllvm.hexagon.M2.mmachs.rs0llvm.hexagon.M2.mpy.acc.sat.hl.s1llvm.hexagon.M2.mpy.nac.hh.s0llvm.hexagon.M2.mpy.nac.hh.s1llvm.hexagon.M2.mpy.sat.rnd.hl.s0llvm.hexagon.M2.mpyd.nac.hh.s1llvm.hexagon.M2.mpyu.nac.ll.s0llvm.hexagon.M2.mpyud.nac.hh.s0llvm.hexagon.M2.mpyud.nac.hl.s0llvm.hexagon.M2.vmac2su.s1llvm.hexagon.M4.nac.up.s1.satllvm.hexagon.M5.vmacbuullvm.hexagon.S2.asl.r.p.orllvm.hexagon.S2.asr.i.vhllvm.hexagon.S2.asr.r.p.accllvm.hexagon.S2.extractup.rpllvm.opencl.write.image1bullvm.ppc.altivec.lvebxllvm.ppc.altivec.stvebxllvm.ppc.altivec.vavgsbllvm.ppc.altivec.vavgubllvm.ppc.altivec.vcfuxllvm.ppc.altivec.vexptefpllvm.ppc.altivec.vminuwllvm.ppc.altivec.vsrahllvm.qcom.mem.fencellvm.qcom.s162u32llvm.qgpu.atomic64.xchg.oobllvm.qgpu.fcombine53llvm.qgpu.fcombine60llvm.qgpu.fcreate.map9llvm.qgpu.get.rt.hit.stbl.stridellvm.qgpu.global.fset.regllvm.qgpu.iabsnegllvm.qgpu.icombine60llvm.qgpu.icreate.map54llvm.qgpu.iminllvm.qgpu.load.uavllvm.qgpu.stthrllvm.qgpu.sub.group.broadcast.first.floatllvm.qgpu.subgroup.ballllvm.qgpu.subgroup.builtin.Gemaskllvm.spu.si.dfsllvm.spu.si.shlqbyillvm.x86.3dnow.pf2idllvm.x86.aesni.aeskeygenassistllvm.x86.avx2.maskstore.q.256llvm.x86.avx2.phsub.swllvm.x86.avx2.pmins.bllvm.x86.avx2.pmovsxbdllvm.x86.avx2.pmovsxdqllvm.x86.avx2.psllv.dllvm.x86.avx.min.pd.256llvm.x86.avx.vpermilvar.psllvm.x86.avx.vtestnzc.pdllvm.x86.fma4.vfmadd.ssllvm.x86.fma4.vfmsub.pd.256llvm.x86.mmx.pcmpgt.dllvm.x86.rdfsbase.32llvm.x86.sse2.comigt.sdllvm.x86.sse2.paddus.bllvm.x86.sse2.psra.dllvm.x86.sse2.psrai.dllvm.x86.sse41.pmovzxwqllvm.x86.sse41.round.pdllvm.x86.sse41.round.ssllvm.x86.sse.comieq.ssllvm.x86.sse.cvttss2si64llvm.x86.sse.max.psllvm.x86.sse.stmxcsrllvm.x86.xop.vfrcz.pdllvm.x86.xop.vfrcz.pd.256llvm.x86.xop.vpcomeqdllvm.x86.xop.vpcomfalseqllvm.x86.xop.vpcomfalseudllvm.x86.xop.vpcomltqllvm.x86.xop.vpcomtruedllvm.x86.xop.vpmacswwllvm.xcore.outctllvm.xcore.setevunreachablefdivcmpxchgsitofplandingpad on module 'i64x86mmxv32i8v8f16fpmath requires a floating point result!Called function requires more parameters than were provided!Vector GEP pointer operand is not a pointer!Both operands to FCmp instruction are not of the same type!Intrinsic has wrong parameter attributes! does not match return type.Global is marked as dllimport, but not externalFK_PCRel_2.uleb128 assemblerDW_CFA_advance_loc4DW_CFA_offset + Reg(GOTNTPOFF(tpoff)(gottpoff)__common__apple_namespac .section "S_GB_ZEROFILLAvailable features for this target: HC: Alias Analysis Evaluator Pointer Alias Summary: defC && ByteOffset <= TD.getTypeAllocSize(C->getType()) && "Out of range access"postdomDominance Frontier ConstructionNumber of Br insts ScalarNumber of Alloca insts ScalarNumber of FPTrunc insts ScalarNumber of FPExt insts ScalarNumber of UserOp1 instsInterval Successors:
DefUnknownlabel = ""; Loop Lazy Uniformity analysis> calls external node <reg)==RegAliasInterferenceMap.end() && "LI is not expected to be regalias tree root"!SlotIndex::isEarlierInstr(RMS[ri], Uses[i])false && "Try to erase a must_assign interval"systems with Graphviz or gv! __stack_chk_failDisable hazard detection during preRA schedulingEnable instr mix profit analysis during postRA schedulingDisable critical path priority in sched=list-ilpDisable use of AA during schedulingcouldn't allocate input reg for constraint 'TargetGlobalAddressTargetConstantPoolfpowextract_subvectorany_extenduint_to_fptrapsetoltsetgt__mulsi3__udivhi3__subsf3__gnu_h2f_ieee__fixunssfhi__fixunsxfdi__floatsitf__floatunditf__floatuntitf__sync_fetch_and_add_2NumBits < static_cast(std::numeric_limits::digits) && "undefined behavior"' is too large for the ocaml GC! Frame size live roots for invalid element type in pointer typeInvalid MODULE_CODE_FUNCTION recordFunction not a pointer to function type!Invalid VAARG recordInvalid blockaddress block #Disable localize init global optimizationRun GVN instead of Early CSE after vectorization passesCDV && "cValue should be either llvm::ConstantVector or llvm::ConstantDataVector"divide6qgpu.opencl.promoted.pointeridForce a6x style regfile layout regardless of arch Disable Pre-RA SSA Destrcution (CS) C0_bHR3_cHR21_aHR29_aHR44_dHUR6_bHW_AL3IR1IR5IR52IR59R4_bR8_aR25_dR43_dR44_bSR1_dUAV41UAV46UAV51UR5_c(ss)leu16s16vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUCombiner.cppQGPU::isel16&Suc == FBBopc == QGPU::MULTICOPY4rr || opc == QGPU::MULTICOPY3rr || opc == QGPU::MULTICOPY2rrOpcode != QGPU::HIFAKEMOVA1 && "setting A1 with halfreg ids not yet supported"isa(ElementTy) && "IntegerType is expected" (sy)(numElements <= 32) && "return value size should <= 32"enable-large-combineisa(initializer)false && "invalid newInst"false && "A dummy mov is expected here"Constant_Promotion_Limit != 0xFFFFFFFF && "Constant_Promotion_Limit uninitialized"false && "Invalid constant value"SwapTypeCI && "Constant int expected"false && "Image type and data type attributes are missing\n"ResultReg && "failed to get regs for shlm".vert.mode.basemul.f.mul2mad32.f16shlm.b32andg.b16rsqhlog2hgetlodstgenshfl.downldlvuvgs.sqgpu.substate.listqgpu.mesh.shaderforceConstantRamModeNodevalNodeqgpu.ms.prim.attr.enabled__qcom_BARY_Coordinate0 && "No function defined"0 && "should be no dup."IImmRangeError: SrcRegPrecisionMismatchError: an integer immedaite must be < MemCpy instructions is not generated by the code generator.minimize nopsyellowReplace Undefs with constants (zero)(ElementType->getScalarSizeInBits() == 64 && ElementType->isIntegerTy()) && "Inavalid integer type"UseMI && UseMI->getParent() == MBB && "Currently limited to the entry block"QGPU pre-emit passTargetRegisterInfo::isVirtualRegister(LR_Base->Reg) && "Already allocated aggregate"res_lob_hi_1bit_convert_to_bool_carry_on_bits_temp , Use : false && "No dominator information"VecUseSlot.isInstSlot() && "SlotIdx must be an instruction slot."PrevMBB != CurrMBB && "PrevMBB must be the immediate layout predecessor of CurrMBB"Child && "Unexpected result from splitting"Inconsistent hints on vector operandfalse && "Instruction selection failed"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUResumeCount.cpp!FakeInstrInfo::isCOMBINE(UseMI) && "combine marked as non-foldable"false && "ISAM no longer supported! Replaced by PI2GPR."the ldg.a instruction should use g with source 0. Usage g[r4.x+32] LDC: Out of Range Offset with ldc instruction. Allowed Range is 8 bits, |0 - 255|.the ldlblk instruction should use l with source 0. Usage l[32],src[0] of ugpr type the stx instruction should use g with dst. Usage g[r4.x+32] the stgb instruction not allowed in a6x and above LoadStore: for Getwid instruction dst should be GPR ALU3 MAD32: Only allowed in a6x and above.Source operand0 cannot be ImmediateValue EFU:Source0 Operand cannot be Predicate Register. Texture register should start with t(T) the half decimal value should start with h/H PATCH21dcl_extra_local_memory_size is allowed with HS onlyOUTPUTCONTROLPOINTIDPRIMITIVESIZEINPUT_INNERCOVERAGEMULSINSTRLEOPCODESYNCLSNPSINSTRLOADTHRU8INSTRLOADTHRAU8INSTRLOADXS8INSTRLOADPF32INSTRCHMASKINSTRLOADLWU32INSTRSTLWU32INSTRSTLWS32INSTRGETBUFINSTRLOADGBT3DS32INSTRBRAOINSTRDGBINSTRATOMSUBGENGPUS32INSTRATOMDECGENSOCU32INSTRATOMINCLNGENSOCU32INSTRATOMINCRGGENGPUS32INSTRATOMCMPXCHGGSOCU64INSTRATOMBDECGNU322DINSTRATOMBSUBGU323DINSTRATOMBMINGU322DINSTRATOMBMINGU323D1LINSTRATOMBMAXGS321DINSTRATOMBMAXGS322D1LINSTRATOMBANDGS322D1LINSTRATOMBAORGU321D1LINSTRATOMBORGS322DINSTRATOMBORGS323DINSTRATOMBACMPXGU321D1LINSTRATOMBAXCHGGU322DINSTRATOMBAINCGU321D1LINSTRATOMBAINCRGGS323DINSTRATOMBADECGU322D1LINSTRATOMBADECRGGU322D1LINSTRMADF32INSTRMADU16INSTRSADS32INSTRSININSTRPROJECTOFFSETENABLECONVMINSTRSAMBINSTRBRCSTACTIVEW4U16INSTRAROMDECRGLS32INSTRCATU16INSTRMGENBINSTRDSXPPTOKENLDIBU321DTRCKINSTRLDIBS323DRCKINSTRRESBASE2DINSTREXP2HINSTRMOVSU32S16INSTRMOVSS32S16INSTRMOVSS32F16INSTRATOMANDGENU32INSTRMADM32F32F16F32INSTRLDIBUNTYPEDU321DRCKINSTRLDIBUNTYPEDU321DTRCKINSTRLDIBTYPEDF161DRCKINSTRLDIBUNTYPEDF162DRCKINSTRLDIBTYPEDS162DRCKINSTRSTIBUNTYPEDU321DTINSTRSTIBAS163DINSTRSTIBAF163DINSTRLDIBS163DRCKINSTRLDIBAF162DRCKINSTRGATU16INSTRGATU16S32INSTRGATF32S16INSTRGATS32U32INSTRSCTU32F16INSTRSCTS32U32INSTRGETSPIDU32INSTRPACK4SSD_ENABLEDCL_CL_LOCAL_LINEAR_ID_REGHALFINVPIETOKENSOURCE_NEGHS_TYPERCURLYDCL_DXMETADATA_FLAGS_TOKENUNPACKEDTOKENSOURCE_ABSUNLOCK_INSTRGETGPRBASEINSTRLOADLBLKINSTRATOMRGLINCDECSTRLOADXINSTRMOV_SOURCE_MODIFER1DEST_DATA_TYPEDEST_OPERANDCB_DESC_DESTALU3: NEG is not a valid source modifier for this instruction. STIB.BLK.L: dst has to be GPR.symbolsuboLocationmergedShaderInputs_A4xA3X_CLIPPLANE_INFOADRENO_BINDLESS_DATAADRENO_MS_VSPASSTHRUADRENO_MS_VPCPASSTHRUmergedShaderInputsstereoRenderingInfoNamedConstants"/> MAX_VARYING_VECTORSMAX_GEOMETRY_TOTAL_OUTPUT_COMPOENTSFRAG_DEPTH_EXTOES_SAMPLE_VARIABLEPRIMITIVE_BOUNDING_BOXPOST_DEPTH_COVERAGEpatchControlPoints============ fragData Binding Info ============ GL_FLOAT_VEC2GL_SAMPLER_2D_SHADOWGL_INT_IMAGE_3DGL_UNSIGNED_INT64GL_IMAGE_1D_ARRAYRGB2YUV601RGBA8_SNORMRGBA8UI description = %sN/Avendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/OsUtils.cppTexture instruction is found in non-uniform control flow, behaviour/result might be underfinedqgpu.invariant.pointcoord$LWMPrimSizeUint32$AtomicCounterBasesPtr64$FragCoordWChannelPatchingFloatTessellation Factor Data Base Pointer (64-bit)Transform Feedback Buffer 2 Base Pointer (64-bit)SupportFastColorBypassenableNamedConstBracdisableReuseSimpleVSAsBSreserveSharedConstantcommon_functionsllvm.sin.f16llvm.sqrt.f32llvm.qgpu.umin.i16llvm.qgpu.global.fget.reg.f16.p0f16llvm.qgpu.global.scalar.alloc.reg.p0f16.p0f16llvm.qgpu.fcreate.map4.v4f16.f16llvm.qgpu.atomic.cmp.xchg.oob.i32((entry.size() == 2) || (entry.size() == 3)) && "combined sampler needs two or three bindless group entries"reg_user && "Unexpected user of Layer getreg"0 && "RHS is not struct type"(isSrcInt == isWeightInt) || wtIsScalarrhsSize == 1 && "indirect index is not scalar!"matrixMe1->getColSize() == matrixMe2->getColSize() && matrixMe1->getRowSize() == matrixMe2->getRowSize() && "two objects of matrix multiply have mismatch sizes!"namedConstantGV && "namedConstant doesn't exist"imageSym && "imageSym Null"getObjRayDirloadInst && "load instruction is expected!"gl_SubgroupLocalInvocationIdval && "OpRayQueryGetRayTMinKHR" " is not supported"get_intersection_candidate_AABB_opaquesrcFn && "OpRayQueryProceedKHR is not supported"srcFn && (RT_RP_GET_OBJ_WORLD_TRANSFORM " is not supported")$setupBaryN_w_slope_dx$setupBaryP_w_slope_dypConst1 != NULL && pConst2 != NULLdummyTerminator != NULL && "No terminator found"false && "expected named constant buffer location for lowering"(base->getType() != mInt64Ty) && (offset->getType() != mInt64Ty) && "should be int64 typed"FragDepthVec4gl_WorkGroupSizegl_GlobalInvocationIDgl_MaxCombinedImageUniformsgl_MaxGeometryInputComponentsgl_MaxTessControlInputComponentsitextureCubeArrayYV12 textureExternalOESuimageCubedataType != NULLfalse && "setPatchFrontFacingAtMainEntry called on invalid object"node->getOp() == EOpSequence && "switch body AST opcode is not correct!"!this->isArray()vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/opengl/gl_parser/CodeGen/Codegen_Support.cppiimgcafractmaxValpackHalf2x16greaterThanEqualsubpassLoadtextureProjgl_PointSizeelifcan't modify gl_PrimitiveIDIncan't modify gl_MaxTessEvaluationInputComponents(structure contains a sampler)gl_BoundingBox is only allowed in ES3.2+second argument must be an l-valueDot selection can not be applied on matrixcentroid inout is invalid qualifier combinationnumber of invocations should be a non-zero valueGL_EXT_shader_io_blocksGL_EXT_clip_cull_distancehighpMatrix * Scalar Assign *=Logical And && hyperbolic sineConstruct mat2x3Cross ProductBitmap MSBTexture3dProjTexture2DShadowgradOffsetTexture2DShadowArrayGradOffsetEmitVertexImageLoadBufferImageStore3DMemoryBarrierSharedCondition Constant Folding cannot be done for vector times matrixgl_ShadingRateEXT*invariant declarationwarnextension name is truncatedGL_EXT_scalar_block_layout$vpointeeTy->isVectorTy() && "vector type is expected"resultTy && "Unexpected OpCompositeExtract into non-aggregate"gl_SubgroupId$paramImageOpTypeVectorOpSpecConstantTrueOpCopyMemoryOpImageSampleDrefExplicitLodOpImageQueryLevelsOpUConvertOpMatrixTimesScalarOpULessThanOpGroupNonUniformShuffleUpOpRayQueryInitializeKHRunsigned(numArrayDims) == numArrayStrides"> -bc> vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/raytracing/StateFunctionTransform.cpp$qgpu.misc.const.dispatchstateStoreIntoInPLCDtraceFramePopargnext.ray.to.executevec != NULLget.asptr.lincoming.CD.offsetvalue != NULLQCC initial codegen (One)words[positionRegID: needsVertexCount: needsBaseVertex: drawParametersRamLocation: constantLayoutVecSize: needsPrimitiveID: numClipPlanes: partitionType: pointSpriteUVVPCIndex: ]: useSampleFrequency: useEarlyDepthStencil: formats[[ADRENO_SO_ELEMENT] (Ver [ADRENO_INITIAL_TEXTURE_DATA] (Ver constant3rdCoordEn: loads: ]: bindlessRanges[bindlessImageSupport: enableExternalSamplerYUV2RGB: hasLocationQualifier: numDimensions: numConstColorOutputEntries: [ADRENO_MS_VSPASSTHRU][shaders: [ADRENO_SCREEN_COORD_TEX_USAGE_INFO] (Ver .uavWriteMask.dynamicallyIndexesSamplers.outputsPointSize.vpcIndexes.needsDomainV.conservativeZMode.wgIdConstID.formats[ADRENO_SO_BUFFER].needsLocalId.textureID.destRegID.numDynamicTextureMappings.numConstantExpressions[A6X_PS_INPUTS].numPositionOutputs.primSizePerVertex.globalScratchSize.bufferOffset.unsizedArrayOffset.isInstanceIOBlock.isBypassVarying[GL_SYMBOLLIST].imageAttachmentDataEntries.primStride.*(.Value[0] - lclamp : %8d - fsam : %8d - getlod : %8d - pcmn : %8d - immoff : %8d - sti : %8d,%8d (rpt), ratio %5.2f - ldib_b_c : %8d,%8d (rpt), ratio %5.2f - ldibasize : %8d - stgasize : %8d - BRAA Instrs : %8d const_reg_footprintfpconvert_rpttex.immmem.ldib_bmem.preamble_ldckLong latency sync instruction countLLVMOptionStringsFastCompilationEnableSingleRegisterPoolSingleBBRootSignatureUnavailableGLViewMaskEnableBGPRBGERootTableOffsetPtrForceHighpCommon2FunctionsEnableVKPreRotationPatchingSOGEOutputIndexPtrEnableRelaxedVectorMatchingIsGotchaQCC_ResourceSignature_VisibilityFilterHARDWARE_BUFFER_DESCencodingCOLOR_SPACE_TRANSFORMsubsampledconst INTERNAL_COLOR_SPACE_TRANSFORMError parsing bindless data: Output metadata specified, but no shader memory callback provided UCHETrapBaseLo (): lower 32 bit of the UCHE_TRAP_BASE_PTR Unable to parse EnableUnSafeMath value 'Unable to parse GLShaderType value 'Unable to parse LLVMDebugType value 'Unable to parse EnableSharedConstants value 'Unable to parse BGEResourceStride value 'Unable to parse EnableDefaultUBOBrac value 'Unable to parse DisableSingleRegisterPool value 'Unable to parse UsePerPixelDerivative value 'Unable to parse ReserveSharedConstant value 'Unable to parse EnableRobustBufferAccess value 'Unable to parse SizeOfFoveatedBinData value 'Unable to parse SOGECount value 'Unable to parse EnableFP16DenormPreserve value 'Unable to parse ScratchBindlessBase value 'Unable to parse RayPipelineDebugPointerHigh value ' Use64BitAddr (false): 64 bit addresses in A5x EnablePreamble (false): Enable per-shader preamble EnableSafeNopInsertion (false): Enable safe nop insertion IsAssembleShader (false): Is input an assembly shader EnableBinningShader (false): Generate both render and binning shader if different from render shader ForceBinningShader (false): Generate binning shader even if equivalent to rendering shader, implies EnableBinningShader EntryPointName (__null): Entry point name (defaults to "main") EnableA7pAlias (false): (a7p) Enable alias instruction ForceWaveSize (false): Force wave size setting ForceMemLayout (false): Set the preferred memory layout EnableRobustBufferAccess (false): [GLES3.2 robust buffer access] enable OOB checking for CB caching EnableBindlessImage (false): allow bindless read-write texture (Image) usage EnablePreloadDrawParam (false): Enable draw parameter to be preloaded in preamble SOBGESize (0): size fo one output buffer entry TFDataIsInterleaved (false): If this is true, then the layout can be more complex, otherwise each output goes to a separate buffer EnableMinMaxDestConversion (): Enable destination conversion on min/max ScratchBindlessReservedMask (): Scratch bindless offets reserved by the driver. QGLCCompileA506A504" type="Number of used regs exceeds the number of regs, error in compiler-generated metadata. Describes a single input/output used in a pass-through mesh vertex shader. Version 1.0: Added offset: Offset from the beginning of the vertex/primitive data. Added numComponents: How many components to load Added surfFormat: Used to choose between half/full precision data Added regId: Scalar physical register index to write result to. Added writeMask: Which components are ultimately written to regId. Added vpcId: VPC Index to export the data to after fetching. postrapseudosCreate Garbage Collector Module MetadataNumber of rematerialized defs for spillingi + Count <= M && "Invalid source range"show-mc-instNumber of conditional branchesUNKNOWNRegFixedFirst terminator was: Instruction loads from dead spill slotLive segment doesn't end at a valid instructionAfter codegen peephole optimization passBefore greedy register allocatorAvoid short-syncs due to war hazards for efu/tex/ldst instructions.RegAliasInterferenceMap.find(LI.reg)==RegAliasInterferenceMap.end() && "LI is not expected to be RegAlias root"Number of cross class joins performedNumber of CSR spills+restores reduced.vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/SplitKit.cppEliminate PHI nodes for register allocation, intelligentlyNumber of source copies insertedtail-dup-limitNumber of tails duplicatedNumber of dag nodes combinedDisable cycle-level precision during preRA schedulingDisable scheduler's two-address hackRC && "RC is NULL!"setltCould not match memory address. Inline asm failure!__lshrhi3__divdi3__fixunsdfdi__floattisf__eqdf2Make an absence of debug location information explicit.frametableInvalid STRUCT type recordError at end of value symbol table blockMalformed global initializer setInvalid RESUME recorddisable-fast-opt-modeDo not run BB vectorization pass as part of vectorizationnextNodeEnable unified RA (Global RA for DX)llclib: error: module does not contain a target triple 'a6x_64HR9_bHUR1_dHUR7_aHW_AL4IR55IR58IR84IR99IR122R10_dR26_bR31_cR36_dR37_dSAM8SAM14SAM29SR1_cUAV6UAV28UR0_bUR1_dUR7_dHWRC], Modifier are not allowed on this operand.(InstIndex < vecLength) && "InstIndex errors!"false && "operand type is incorrect!"QGPU::fminlastInstrMBB && "Exit Block does not post dominate all blocks"false && " Jump to an empty block is not expected "LastMI && "LastMI null in mergeNop !"!E->DstNode->IsMem && !E->SrcNode->IsMem && "Invalid transfer graph node"CurrMapSize <= 16 && "Cannot have more than 16 bits in half reg"Callers.size()<=1 && "More than 1 caller requires merging of buckets of all callers"false && "insertelement must have dummy mov instructions"false && "srcVectorType/dstVectorType should not be NULL"load.component.Valfalse && "Need either CDV or CV"false && "Unexpected type for GV initializer"literal-loweringTM && "TargetMachine cannot be null for CL/RS code"NextI && "Expect instructions after the current vec instruction"safe-mode-nopAfter Two Address Instruction_CL_private_mem_end0 && "Pointer type expected in addrspacecast"F != NULL && "Function cannot be NULL"false && "Non-32-bit data should not be promoted to constant memory"false && "NumRetEles exceed 4"FuncInfo.CanLowerReturn && "A function without sret pointer?"!"Invalid opcode"(DestVT == MVT::i32) && "Unsupported bswap data type"SamplerWidth && "Shuffle width is not present"CalledFn && "Unexpected failure in getting called function"false && "pipe argument not lowered correctly"Src0Reg && "failed to get src0 reg for shift mask/merge"false && "Unknown mode in absneg intrinsic"NumRegs == 8 && "Incorrect return type for qgpu_rtu".???.ssdmax.ucat.u32sel.f32getcyclegather4bgetfiberidYield_TexBaseID < 8 && SamBaseID < 8 && "BaseID must be 0-7"false && "Unsupported architecture in encoding"qgpu.has.atomic(numDefs % 16) == 0no_subgroup_ifp((uintptr_t)KArg & (alignOf() - 1)) == 0 && "misaligned access"DstRegRelNotAllowedError: is expected.# of const regs or immediates must be < sGPRVsFspost-sched-combiningmax-yield-countCastIQGPU Instruction Selection Prepareenable-global-load-combine-hintfixMRI->getRegClass(MI->getOperand(0).getReg()) == &QGPU::FullRCRegClassAccumulationInsertPt && "AccumulationInsertPt is nullptr"isLoadlFold || RelMovMI->getOperand(1).isReg() && "Problematic MOVra"DefMI0 && "Unable to find definition of vreg"FakeInstrInfo::isIFAKEMOV(MI->getOpcode())!(IsPrivMemType && IsPerWavePM == QGPUTargetMachine::PerWaveMustEnable && Rpt>0) && "Cannot have rpt set for private mem op if per-wave mode is forced"NumEdges > 0 && "Negative # of edges?"dummyMov != NULL && isDummyMovInst(dummyMov) && "A dummy mov is expected here"(vecSize > 0) && "vecSize and bitSize errors"Emulate Oxili BC instructionsreuse-stack-slotLI && "Interval not found"0 && "fi reuse detected"false && "Unexpected branch pattern?"MDT && "No dom tree info!"Sorted[i]->succ_size() == 1Shifting LDST: Out of Range Offset with ldthr.a instruction. Allowed Range is 13bits, |0 - 8191| LDST: Out of Range Offset with ldx.a instruction. Allowed Range is 13bits, |0 - 8191|LDC: for src mode1/2/5/6 src2 should be GPR for a6x and abovethe ldc.a instruction not allowed in a6x and above STIB: for src mode1/2/5/6 src2 should be GPR for a6x and aboveSTIBBLK: LDIBBLKL length is out of range. Allowed range is 4 .STIBA: Valid Data Types are u32/s32/f32/u16/s16/f16LDIB.A: Source2 should always be Immediate/GPR Value LDST: Out of Range Offset with stlW instruction. Allowed Range is 13bits, |0 - 8191|LoadStore: GetSPID instruction not supported in a4x and below STSC: src1 is out of range. Allowed Range is 1 - 160ALU3 - SHIFT MASK: b16 is for 16 bit sources src[1]ALU3 - SHIFT MERGE: b32 is for 32 bit sources src[2]ALU3 WMM: src2 has to be immediate value.mova.r is only supported from A8xcan be only NAN, INF and NEGINF Texture: PairID must be specified before A8xINT32 Invalid Data type for dcl_cl_arg instruction INSTANCEIDTHREADGROUPIDUINTmemory exhaustedMAXUINSTRLOADGU16INSTRLOADGAF32INSTRLOADGENS32INSTRLOADTHRCCHES16INSTRSTXS8INSTRLOADGBAU3DU32INSTRSTGBT2DINSTRSTGBT1DTYPEINSTRDCINVALLINSTRCCINVINSTRATOMINCGENSOCU32INSTRATOMDECGGPUS32INSTRATOMDECLNGENSOCU32INSTRATOMMAXGSOCU32INSTRATOMBMINGU323DINSTRATOMBMAXGU321DINSTRATOMBAANDGS32INSTRATOMBAANDGS322D1LINSTRATOMBAXORGS323D1LINSTRATOMBAXCHGGU323D1LINSTRATOMBXCHGGS32INSTRATOMBAINCGU322D1LINSTRATOMBAINCRGGU323D1LINSTRATOMBADECLNGS32INSTRSELF32INSTRISAMLINSTRAROMDECLNLU32INSTRLDIBS321DTINSTRBUFINFO3DINSTRRESBASE0DINSTRMOVSU32F16INSTRMOVSF32S32INSTRATOMMINGENU32INSTRLDIBTYPEDU321DTINSTRSTIBTYPEDF163DINSTRSTIBF161DINSTRSTIBAU161DTINSTRLDIBU161DINSTRGATS32F32INSTRSCTS16F16INSTRGETGPRBASEU16INSTRSHFLRUPINSTRSHFLRDOWNW4U16INSTRSTCINSTRDCL_CL_PRIVATEMEMBASECONSTREGID_TOKENDCL_16BSDIMEN_3DMBREGDCL_ALL_CTRL_POINT_SIZE_TOKENDCL_PS_TEX_ENTRY_SAMPLEIDDCL_PS_TEX_ENTRY_DSTMASKDCL_KERNEL_CSSTATESIZESIGNBITDECLARE_STEREORENDERINGMODEFLOW_INSTR_4GETWIDINSTRSTIINSTRG2LINSTRMGENINSTRMOVSINSTRSAMPLEINFO_INSTRSDCL_GL_DATA_TYPEDCLICBVAL22DCLICBVAL33 ALU2: Predicate registers cannot be source operand. ALU2: Invalid Float Value for Source1 Operand. Refer to ISA for valid Float Values. ALU2: Out of Range offset in Relatively addressed Source0 Operand. Max Offset value can be 1023ALU2: destination convert is not supported for this instructionMOV/COV: Atleast one operand of MOVS should be sGPRelementssubStatesgeneratedInputsclipCullInfo_A4XADRENO_CBCACHEADRENO_MS_VSPASSTHRU_LISTshaderTyper24UnormTexturesgsMergedShaderDescoutputDesctfImageMAX_ATOMIC_COUNTER_BUFFERSMAX_PROGRAM_TEXEL_OFFSETMAX_GEOMETRY_TEXTURE_IMAGE_UNITSMAX_TESS_EVALUATION_ATOMIC_COUNTERSMAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTSMAX_NUMBER_VIEWSTEXTURE_CUBE_MAP_ARRAY============ MaxProgramTexelOffsetMaxComputeWorkGroupSize_Z Value : componentGL_INTGL_INT_VEC4QGL_INT_TEXTURE_2D component = %dbaryInst && "Assert Index:[47] bary instruction expected"$YUVConversionMat4Array$TFBuffer1BasePtr64$TFBuffer3BasePtr64$BinCoordHelperIvec4PointCoordRotationMat2$FragCoordFovOffsetVec2Array$ShadingRateKHRRotationUint32$TextureFovSubsampledOffsetConstantsAtomic counter buffer base pointers (array of uint64)FalsesampleGroupSizerotationShaderPatchingenableEarlyPreambleenableFastColorBypassenableFSFovPatchingnumViewsllvm.qgpu.dsy.v2f32llvm.qgpu.global.scalar.alloc.reg.p0i32.p0v4i32llvm.qgpu.stlw.v2i32llvm.atomic.load.min.i32qgpu.need.reserve.primitiveIDmetaGSGV && "metaGV is null"NOTE: elementTyqglnext_gs_iosrcElem && "incompatible casting in assigning variable"false && "vector load need to be scattered"false && "impossible unary operator"gl_ViewID_OVRi32!srcTy->isPointerTy()srcTy->getVectorNumElements() == dstTy->getVectorNumElements()(dstPtr != NULL) || (dstTy != NULL)getWorldRayOrit.maxw2otmatrixType->isMatrix()ptrType->isPointerTy() && "pointer type expected"false && "retType is NULL!"get_intersection_typeget_intersection_primitive_index__RTfalse && "Counter val too much possible inf loop"this->isArray()tcsHSGV && "tcsHSGV is NULL!"entryPos && "No getreg instructions!"insertBefore != NULLstanchorIntr && "Didn't find coupling anchor intrinsic"vRelPatchIdPtr != NULL && "Couldn't get vRelPatchIdPtr!"LayoutQualifierInLayoutQualifierOutsamplerExternalOESsamplerShadowQGLitexture2DMSutexture2DArrayYUYV textureExternalOESNV21 textureExternalOESuimage3D(symSection->type == SO_SECTION_SYMBOL) && "No symbols after ISA oject section"dstTy->isVectorTy() && srcTy->isVectorTy()trueMe->getSize() == falseMe->getSize() && "selection TRUE operand and FALSE operand have different size!"biNode && biNode->getOp() == EOpIndexDirectStructError: array indexing out of boundarysmoothstep# InfoLog: *=Interpolation qualifiers mismatch l-value of swizzle cannot have duplicate componentscan't modify gl_VertexIndexcan't modify gl_MaxDrawBufferscan't modify gl_MaxComputeAtomicCounterscan't modify gl_MaxGeometryOutputComponentscan't modify gl_MaxGeometryTextureImageUnitsredefinition'%s'gl_LastFragStencilARM or gl_LastFragLastDepthARM cannot be declared as arrayarray is not allowed for function returnGL_ARB_tessellation_shadermediumpDiv /Indirect IndexLogical XordPdxCompare Less Than or EqualRefractTexture2DArrayShadowImageLoad2DMSArrayImageStore1DImageStore2DMSImageStore2DRectMemoryBarrierAtomicCounterBranch: Unknown BranchConstant Folding cannot be done for matrix multiplyInvalid declaration of 'invariant'TEXTURE1DITEXTURE1Dnon-void function must return a valuealloc && "alloc is Null" supported in pack/unpack shaders only requireifdef needs an identifierInvalid Floating point exponentphi_hole21$paramSampler(srcME->getSize() ==4) && (srcOperand->isUint()) &&(srcTy == codeGenHelper->getInt32Ty()) && "Value must be a unsigned vec4 of 32 bit integer type"OpEntryPointOpTypeSamplerOpTypeArrayOpConstantCompositeOpVectorShuffleOpCompositeInsertOpFModOpAllOpFUnordLessThanEqualOpBitwiseOrOpGroupNonUniformBroadcastOpRayQueryGetIntersectionPrimitiveIndexKHRhasNoAnyHitLoadFromInPLCD!inst->getType()->isPointerTy() && "Can not save pointers"_tmpret.stateId.ptrEXITscheduleContpNumRaysCompletedlaunch.idmailbox.counts.ptrgetOutFloatsf && "For AnyHit shaders, scheduleCont() should have been built"prev.frame.base.offsetcall && "expect CallInst"(IVI->hasIndices() && IVI->getNumIndices() == 1) && "nested structure not supported yet"dst.flags (Flat) (Int32) (Uint16) (MultiViewCB) (UAV) (QGLNEXT_NAMED_CONSTANT_UBO_INDEX)preferPerFiberMode: hasRelativeAddressingInBranch: numEFUInst: compMasks: [A4X_HS_MERGED_SHADER_DESC] (Ver cbSlot: viewportArrayIndexVirtualRegAndComp: rtArrayIndexVPCIndex: ]: shaderType: needsWGID: constantExpressions[[ADRENO_BINDLESS_GROUP_MAPPING_RANGE][useMultiPositionOutput: [ADRENO_INPUTS] (Ver unsizedArrayOffset: isSmooth: parentUBOSlot: dualSrcBlendingIndex: [ADRENO_MESH_PAYLOAD_DESC] (Ver ([ADRENO_REGISTER_USAGE_PER_FIBER]*) [ADRENO_SHADER_COLLECTION_SHADER_INFO][[ADRENO_SHADER_COLLECTION_DATA] (Ver skipTriangles: numScreenCoordTexUsages: .numUsedRegs.instanceIDRegID[ADRENO_DS_DESC].stencilOutputRegID[ADRENO_RT_DESC].constantS[ADRENO_INITIAL_TEXTURE_DATA].endOfQuad.numGathers[ADRENO_UAV_DESCRIPTOR_FORMAT][ADRENO_VSDS_OUTPUTS][ADRENO_INPUT_TARGET_INFO].dynamicCBCacheEntries.samplerInfo.blockMemberIndex.bindlessIndex.numDescriptorGroupsInRendering============ HW .uint64Bits - Half ALUs : %8d,%8d (rpt), ratio %5.2f efu - Half MOVs : %8d,%8d (rpt), ratio %5.2f - FLOOR : %8d,%8d (rpt), ratio %5.2f - dsy : %8d lockR - getspid : %8d,%8d (rpt), ratio %5.2f - stgbasize : %8d preamble_half_alu_rptmem.stp_rptmem.getwidOptionListShaderCRCGLIRShaderSpecializationInfoBufferRefDumpMetadataToDebugASICIDSkipBackEndEnableLMSpillingEnableSingleRegisterPoolMultipleBBRTIndexValuesBGEBindlessIndexPtrBGEElementInfoPtrABGEElementOffsetPtrDisableArrayRoundingEnableDefaultUBOBracConstantRAMModeEnableRobustBufferAccessForceHighpMatrixFunctionsEnableInstrumentationEnableComparableLogFreeSystemMemoryCallbacknumDescriptorsQGLC_COLORSPACE_FORMAT_BITDEPTHisBindless="Error parsing specialization tag data: Unable to parse ProgramBinary value 'Unable to parse EnableSafeModeNop value 'Unable to parse ClientID value 'Unable to parse InputSignature value 'Unable to parse ForceHighpExpFunctions value 'Unable to parse ForceHighpInput value 'Unable to parse UseVRSFoveationQuality value 'Unable to parse AllCompilerOptions2 value 'Unable to parse EnableScratchBindlessBase value ' GLAPIType (__null): GL API type (ESX or Vulkan) ASICFamily (TargetData::ASICFamilyA4x): Which ASIC family to compile for Enable3rdCoordForInitTex (false): (a7p) Enable third coordinate from constant for initial texture EnableASTBlobCaching (false): Enable AST blob caching DisableGatherPatching (false): Disable gather patching DisableSingleRegisterPool (false): Disable sharing of full/half registers UsePerPixelDerivative (false): Generate higher quality derivative instructions EnablePackSmallWorkGroup (false): Pack small workgroups TFDataVaryingCount (0): Number of varyings to write to TF (GL) IsRayPipeline (): Whether or not the compile is for a ray pipeline. A630A680A620A621 A540 A616 A618 A662 A663 /Offset:No shader stats desc pEntryPtr + pEntryDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"Invalid initial texture destination register, error in compiler-generated metadata. Invalid Const color bypass enable but num of initialTexture is non-zero!, error in compiler-generated metadata. Information necessary for shaders that use clip/cull distances. For the masks, 0xf refers to the mask for RegIDs[0] and 0xf0 refers to the mask for RegIDs[1]. Version 1.0: Added clipUsageMask: 8 bits, which components are clip distances. Added cullUsageMask: 8 bits, which components are cull distances. Added numRegs: The number of vector registers containing clip/cull data. Added regIDs: The scalar register IDs of the vector registers containing clip/cull data. Version 1.1: Added virtualRegAndComps: Virtual register locations for the clip/cull outputs (vreg * 4 + comp). Version 1.2: Added compMasks: Virtual register masks for the clip/cull outputs. Version 1.3: Added vpcIndexes: The VPC index of the vector registers containing clip/cull data. Information about the number of potentially non-uniform branch instructions that could be nested. Version 1.0: Added maxRCLevel Gives information for substates of a shader. Version 1.0: Added shaderHandles: Shader bytecode/dcb buffers shared across substates. Added bindlessBaseUsage Added bindlessUsage Added shaderType: What type of shader this is Added numSubStates: How many substates are created for the shader Added stackSize: How much stack this shader requires Added subStates: Per-substate information Added shaderCRC: The driver assigned identifier for this shader. Added hwCRC: CRC value used to detect duplicated shaders. Added reuseGPRMode: Whether registers are shared between SP threads. Added preferredWaveSize: True if compiler thinks shader can benefit from running twice as many pixels per wave. Added fixedSubstateID: If non-zero, this shader's base substate is fixed to the specified value. Added hasCrossWaveCommunication: Used for the RESOURCEALLOCATION hw register, always set to 0 for now. Added reserved Compute Shader found, use LoadObjectFileDXCS ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789!"#$%&'()*+,-./:;<=>?@[\]^_`{|}~ circumflexinvalid backreference numberrepetition-operator operand invalidUnknown errorBitWidth && "Bitwidth too small": for the -versionrequires a value!DW_TAG_subprogramDW_TAG_variableDW_TAG_lo_userDW_LANG_Cobol85,timer!memory_used! ---Wall Time---!path.empty() && "Can't replace missing root"Tex1D" sgt umin; Materializable __ugpr undefrs_input kernel_arg_type_restrict _bvh_image_ of type exagon.S5.asrhub.rnd.sat.goodsyntaxllvm.arm.neon.vpmaxsllvm.arm.neon.vqdmlalllvm.arm.neon.vqrshiftnsullvm.arm.neon.vst4lanellvm.atomic.load.andllvm.hexagon.A2.addh.l16.sat.hlllvm.hexagon.A2.subh.h16.hlllvm.hexagon.A2.subh.h16.lhllvm.hexagon.A2.vminuwllvm.hexagon.A5.vaddhubsllvm.hexagon.F2.dfminllvm.hexagon.F2.dfmpyllvm.hexagon.F2.sffmallvm.hexagon.M2.mmpyul.s0llvm.hexagon.M2.mpyd.hh.s0llvm.hexagon.M2.mpyu.ll.s0llvm.hexagon.M2.mpyu.upllvm.hexagon.M2.mpyud.lh.s1llvm.hexagon.M2.vrcmpyr.s0cllvm.hexagon.M4.mpyri.addrllvm.hexagon.S2.clbpllvm.hexagon.S2.interleavellvm.hexagon.S2.lsl.r.vwllvm.hexagon.S2.lsr.i.p.andllvm.memory.barrierllvm.opencl.get.group.idllvm.opencl.read.image2aullvm.opencl.read.image.no.sampler.2ullvm.opencl.write.image2llvm.ppc.altivec.mfvscrllvm.ppc.altivec.vadduhsllvm.ppc.altivec.vavgswllvm.ppc.altivec.vcmpequhllvm.ppc.altivec.vminsbllvm.ppc.altivec.vrlwllvm.ppc.altivec.vsumswsllvm.qcom.s162s16llvm.qgpu.fcombine13llvm.qgpu.fcombine46llvm.qgpu.fcreate.map13llvm.qgpu.fcreate.map34llvm.qgpu.fget.sc.regllvm.qgpu.get.gpr.basellvm.qgpu.icombine41llvm.qgpu.icombine6llvm.qgpu.icreate.map41llvm.qgpu.icreate.map6llvm.qgpu.icreate.map8llvm.qgpu.image.queryllvm.qgpu.ldthrllvm.qgpu.rtullvm.qgpu.subgroup.exclusive.floatllvm.qgpu.vkptr.cast.to.workgroupllvm.qgpu.yieldllvm.setjmpllvm.spu.si.addxllvm.spu.si.clgthllvm.spu.si.fnmsllvm.x86.3dnow.pfsubllvm.x86.3dnow.pi2fdllvm.x86.avx2.maskload.qllvm.x86.avx2.pminu.bllvm.x86.avx2.psrli.qllvm.x86.avx.maskload.ps.256llvm.x86.rdgsbase.32llvm.x86.sse2.mfencellvm.x86.sse2.psad.bwllvm.x86.sse2.psll.qllvm.x86.sse41.pminsdllvm.x86.sse.comige.ssllvm.x86.ssse3.phadd.swllvm.x86.xop.vpcomleqllvm.x86.xop.vpcomleubllvm.x86.xop.vphaddwdllvm.x86.xop.vphaddwqllvm.xcore.freerllvm.xcore.getedllvm.xcore.mjoinsubmulsremfenceremark: llvm.module.flagsNone'!Module Pass ManagerInterfaceInfo->getNormalCtor() == 0 && "Default implementation for analysis group already specified!"I != Impl->Listeners.end() && "PassRegistrationListener not registered!"blockaddress may not be used with the entry block! does not apply to the function!Instruction has null operand!Load operand must be a pointer.Store cannot have Acquire orderingcmpxchg instructions must be atomic.atomicrmw instructions cannot be unordered.FPToUI source must be FP or FP vectorllvm.gcroot parameter #1 must be an alloca.Only global variables can have appending linkage!FK_GPRel_8 .lcomm .save {' (at offset 'Range StartPGOT_PAGE__apple_objc__debug_pubtypesexpfiprintfsinhfvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/IREmitter/BCTool.cppMainProcessingBlockmCurrentLLVMContextDominator treeNumber of Mul insts ScalarNumber of AtomicRMW insts ScalarNumber of Trunc instsNumber of BitCast insts ScalarNumber of ExtractValue instsNumber of InsertValue insts ScalarUndefined behavior: Load from block addressDelta successesrb: data packet truncated! Profile file loaded by -profile-loaderexitview-regionsmax-cg-scc-iterationsCallGraph Pass ManagerNumber of blocks inserted.exit.split-lpunr.cmpNumber of speculative executed instructionsNumber of IV operands folded into a useprependInst != NULL && "Did not find instruction to prepend to\n"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/SPVKillPatch.cppThe size of the native vector registersAttempt to vectorize horizontal reductionsbb36-vectorize-no-mem-opsTrue && "True is NULL"qgpu.symbols.interpolate.atNumber of instructions removedNumber of stores deletedNumber of blocks mergedattrConst && "Attributes argument should be const value"Enable canonical induction variable rewritingNumber of terminators foldedNumber of branch blocks duplicated to eliminate philoop-interchangeInnerLoopLatch && "InnerLoopLatch is NULL"unroll-allow-partialNumber of memcpy instructions deletedfalse && "GEPIdxTy is not a struct"mergeMin number of instructions to consider tail mergingNumber of simple (F) if-conversions performedSize < N && "branch node overflow"variable sized, align=Number of copies hoistedMBB live-in list contains non-physical register (BB#Illegal virtual register for instructionForeign valno in live rangeBad start of live segment, no basic blockNumber of dead PHI cyclesNumber of reused lowered phisdisable-machine-licmDisable Machine LICMEnable optimized register allocation compilation path.Disable Copy Propagation passallqgpu-regallocregalloc-min-num-half-regsNewVRegs.empty() && "Cannot append to existing NewVRegs"HintPair.secondenable-aggressive-qgpu-coalescingvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/RegisterCoalescer.cppshrink-wrap-dbgSlot index numberingSP_returnno-stack-slot-sharingtail-dup-sizeValue with legal type was transformed!Number of duplicated nodesGLOBAL_OFFSET_TABLErotrfpowisint_to_fpdynamic_stackalloc__lshrsi3__fixsfdi__floattidf__floatundixf__sync_fetch_and_or_1code_beginMultiple TYPE_BLOCKs found!Invalid METADATA_NODE recordInvalid ALLOCA recordThreshold for inlining functions with inline hint can be inlined into Use the BB vectorization pass from 3.6((rhsType == lhsType) && (rhsType->isVectorTy())) && "Cannot compute dot product of non-vectory types\n"qgpu.emulate.lm.startSinglePoolRegFileSelect the a7x_64 processorHC0_bHR13_cHR17_aHR24_cHR32_cHUR0_cIR10IR33IR67R3_aR7_cR7_dR24_aR29_dSR3_bSR6_bUAV34UAV60SGPRC g[partial parsed instruction: [Mod: idx < NumElems && "idx is out of range"QGPU::faddQGPU::load8zfalse && "Broken vector found!!"_CL_sp_ex_lock_ptrvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUInstrInfo.cppfalse && "loadInst is invalid"false && "dstTy/srcTy must be a vector type"c && "operand must be a constant!"Number of kernel args promoted to constant ram_cCBIdentifyMD->getOperand(3) && isa(CBIdentifyMD->getOperand(3)) && "incorrect MD layout"disable-post-ra-combinerfalse && "Invalid register class"VReg_Curr == (VReg_Prev+1) && "Non consecutive registers"_CL_combined_global_offsetValReg && "Invalid register for create.map source operand"(IsBindless || (Src2Imm < maxSlotID)) && "src2(slot ID) exceeds maximum allowed index range"0 && "opencl_reqd_work_group_size without enough parameters"false && "Unknown sync intrinsic"per_wave_const?.g.untypedccr(clamp)mul.fsel.s16mad.f32.mul2dp4accchshldgstxatomic.addatomic.dec.rgavgs.e(OP_IMG == tex.OpCode) && "Weight texture ID is only used for TPIP img inst"__qcom_HSMetaInfopMD != NULL && "Unexpected AS metadata operand"opnd && "Operand is NULL"SrcModUndefinedError: Source modifier is undefined.InvalidProgramEndError: MVnCVT16No OperandQGPU Instruction ValidatorVS=MinRegs, FS=Balanced, Others=Defaulttrack how many instrins in the sync queueblackQGPUInstrInfo::isTextureInstruction(A) && "A should be a tex!"0 && "Wrong type of shader in scheduler!"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUBreakComplexExpr.cppQGPU Machine IR Converterenable-atomic-fiber-reduction(QIC != QIC_TEX && QIC != QIC_LDST) && "TEX LDST instruction still needs rematerialization"((TrimLow+TrimHigh) <= VecLen) && "bad partitioning"CoordMI && "Coordinate Precision Promotion: Nodef for FMOVrr"mirverifierTurn on MIR verification.MF->size() == 1 && "This local allocator takes only a single-basicblock function."no-cmdisable convert metadataprint-activeCoalesce phi operands and try to reduce move instructionsfalse && "No mem-to-mem copy allowed"EvictionResult.first && "failed to free up regs": !Inserted && "mi is active"Reading a token: LDST: Out of Range Offset with ldg instruction. Allowed Range is 13bits, |0 - 8191|. LDST: Out of Range Offset with ldg.a+ instruction. Allowed Range is 9 bits, |0 - 511|the ldg.a instruction should use g with source 0. Usage g[c8.x+r4.x+32] LDST: Out of Range Offset with ldl instruction. Allowed Range is 13bits, |0 - 8191|LDIB: For ldgen Source1 should always be Immediate Value LDST: Out of Range Offset with ldgen instruction. Allowed Range is 13bits, |0 - 8191| LDST: Out of Range Offset with stl instruction. Allowed Range is 13bits, |0 - 8191|RESINFO: for src mode 3/7 reserved for a6x and aboveSTIBBLK: for src baseid 6/7 reserved for a6x and aboveSTIB: STIB length is out of range. Allowed range is 4 .LDIBBLK(L|C): for src mode1/5 src2 should be GPR for a6x and aboveLDIBBLK(L|C): for src baseid 5 is only for src mode 5/6 for a6x and abovethe stgen instruction should use g/l/p with dst. Usage glp[r4.x+32] LoadStore: for Getwid instruction dst .dt and GPR precision should be same the destination should be Full Register onlyALU3 DP4ACC: Only 32 bit registers allowed.MOVA - Source operand0 cannot be other than Immediate, constant, GPRDestination operand1 cannot be ImmediateValueSource Operand Out of Range for 32Bit Half Signed DataType.Only allowed Range is -32768 - 32767 EFU: Only 16 bit Operand ALLOWED Texture: (UINT16) and (UINT32)are valid destination data types with RGETINFOTexture: should specify with .rck options if dest data type (dt) not be specifiedISAM: .1D modifier cannot be used for A5x and below archtype with ISAM A5Xunsupported Data Type provided with DCL_CONSTCOLORNONPERSP_CENTERFOVEATION_QUALITY**************** %s ************** STRUCT_BUFCOVU32S16INSTRCOVF32F16INSTRLOADGU32INSTRPREDTINSTRLOADTHRF32INSTRLOADLU16INSTRSTGU16INSTRSTGAF32INSTRLOADGBU2DS32INSTRLOADGBAU1DF32INSTRSTGBAT1DINSTRATOMADDGENS32INSTRATOMSUBGENSOCU32INSTRATOMDECGENGPUU32INSTRATOMCMPXCHGGENSOCS32INSTRATOMMINGENGPUS32INSTRATOMMINGENSOCU32INSTRATOMINCRGGGPUU32INSTRATOMBASUBGS321D1LINSTRATOMBMINGU321DINSTRATOMBAMINGS322D1LINSTRATOMBAMAXGS323D1LINSTRATOMBANDGU32INSTRATOMBAINCGS322DINSTRATOMBAINCLNGU323D1LINSTRMADSHM16INSTRSELF16INSTRQUADSHFLMODEBRCSTU32INSTRQUADSHFLMODEVERTU16INSTRQUADSHFLMODEDIAGU32INSTRATOMXORGS32INSTRATOMMAXLS32INSTRPREFINSTRLDIBS321DRCKINSTRLDIBAF321DINSTRLDIBAU323DINSTRMOVSU8S32INSTRLDIBTYPEDS321DTRCKINSTRLDIBUNTYPEDF322DRCKINSTRSTIBUNTYPEDS161DINSTRSTIBUNTYPEDS163DINSTRSTIBUNTYPEDS161DTINSTRLDIBBLKGS162DINSTRLDIBBLKCF162DINSTRLOADLBLKS32INSTRSTIBU162DINSTRSTIBF162DINSTRLDIBU163DRCKINSTRLDIBAU163DRCKINSTRGATS16INSTRSCTF16F32INSTRPIPCREADINSTRHOF_ENABLESHFLRDOWNW4INSTRHALFLOG10ETOKENTS_TYPEMONO_TOKENDECLARE_RENDERTARGETDECLARE_HS_PATCHCONSTSIZEINBYTESDCL_KERNEL_CSSTATECONSTREGIDDECLARE_DEFINE_CONSTORDERBITSDECLARE_DX_UAVALIAS_RT_DTLDCCOMPIDLOADTHRAINSTRLOADLVINSTRMOV_IMM_VALUE1SOURCE_REGISTER2SOURCE_OPERAND3ALU3: Source0/Source1/Source2 modifier can not be absneg. TEXTURE: DSX/DSY Destination be 32 bit.dynamicReadsuavUsageconstRegUsagedescvsdsgsmergedShaderDesc_A5XADRENO_PS_BARY_INPUTSADRENO_BINNING_INFOfsDescfsOutputsfs" value="X-e-p:32:32-f16:16:16-f32:32:32-i32:32:32-i8:8:8-i16:16:16-n8:16:32-v96:128:128MAX_TESS_CONTROL_ATOMIC_COUNTER_BUFFERSMAX_GEOMETRY_ATOMIC_COUNTER_BUFFERSMAX_COMBINED_ATOMIC_COUNTER_BUFFERSTEXTURE_BUFFERMaxCombinedShaderOutputResourcesMaxComputeAtomicCounterBuffersMaxComputeBufferBlocksisSSOisBindlessTexture enableBindlessImage="true"" packedImage="nameGL_FLOAT_MAT3x2GL_FLOAT_MAT4x3GL_SAMPLER_3D_OESGL_INT_SAMPLER_2D_MSGL_UNSIGNED_INT_SAMPLER_2D_MSGL_INT_IMAGE_CUBE_ARRAYQGL_TEXTURE_EXTERNAL_YUYV_AMDQGL_TEXTURE_2D_ARRAY_SHADOW sampler4Belending, uavSlot = %d index = %d matrix layout mismatch with other stage.$TessControlPointCountUint32============ ASIC Info ============ disableCBCachingenableASTBlobCachingdisablePreambleForMRTsimulateVariableRateShading-binllvm.qgpu.global.fget.reg.f32.p0f32llvm.qgpu.global.scalar.alloc.reg.p0f32.p0v3f32llvm.qgpu.fcombine3.f16llvm.qgpu.fstlw.f32Too many shaders output from compilerinput/outputisRhsPtr2ArrayrowSize <= QGLC_NUM_CHANNELS && colSize <= QGLC_NUM_CHANNELS( ( srcOP->isFull() || srcOP->isHalf() ) && ( destWidth != E_WIDTH_QUARTER ) ) && "Unsupported Source or Dest Bit width"matrixMe->getRowSize() == matrixMe->getColSize() && "Invalid determinant matrix size"drawParamGV != NULLpAddrSpaceMD != NULLgetHitKinddestME && "destME is Null"$memberdefaultUBO->isSymbolDefaultUBO()srcFn && "OpRayQueryTerminateKHR is not suppported"qgpu.trace.ray.shader!TraceRayFunc && "two instances of TraceRay"SetupTraversal(SBTIndex->isInt() || SBTIndex->isUint()) && "int/uint expected"$setupBaryP_one_over_wval != NULL!needReplace && "sampler can be constructed once"false && "combine.texture.sampler is expected"(elementSize == 2) || (elementSize == 4) || (elementSize == 16)LI && "expect a LoadInst"Error: Compute shader didn't specify fixed local group sizeLoadSRBcomponent && "All components expected to be constant index\n"offset != NULLstoreHitAttrisMatrix()FullyCoveredEXTgl_FragInvocationCountEXTgl_MaxFragmentInputVectorsisampler2Dsampler2DMSisampler3Dimage1DimageCubeArrayiimageCubeArrayuimageCubeArraydstTType->getTypeName() == srcTType->getTypeName()!"GL Tessellation levels not valid in non-tessellation shaders!"!"GL Tessellation levels should always be an array!"retVal && "return value can not be NULL"fragCoordVar && "fragCoordVar is NULL!"(node->getOp() == EOpIndexDirect) || (node->getOp() == EOpIndexIndirect)opnd->getLLVMOperand()->getAddrPointer() && "matrix without address pointer setup"sSCAiimg1aiimg2dstruct-distanceInvalid #version Empty shader. No code generated. &=%>illegal vector field selectionillegal - vector component fields not from the same setcan't modify a uniformcan't modify gl_FramebufferClockQCOMcan't modify gl_SamplePositionqualifier not allowed with function name expectedOnly consts and uniforms can be used in a global initializercan't redefine built-in functions!floatPrecision.size() > 0gl_Position vector size is wrong!Not a correct geometry shader output primitive type.invalid local_size_x of 0var && "can not find builtin varirable gl_MaxDrawBuffers"structure == __null && "can not call on struct"Left shift Assign <<=arc cosineAtomicCounterQueryImul result in 64 bitsTexture2DShadowProjLodOffsetBranch: Killvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/opengl/gl_parser/MachineIndependent/Intermediate.cppvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/opengl/gl_parser/MachineIndependent/Initialize.cpptexture2DProjmemoryBarrierSharedgl_MaxSamplesOESvertex spacing already specified and it is not equal_spacingtextureExternalXXXduplicated function declarations.#if requires a target identifier.#extension must be followed by an extension identifier$ioblkptrType != NULL && "PtrType cant be NULL"argVal && "acclerationstructure arg is expected to be non-empty"symArg && "sampler/texture arg is expected to be non-empty"gl_WorkDimbasePtrTyOpImageTexelPointerOpAccessChainOpImageQueryOrderOpShiftRightArithmeticOpLabelOpGetKernelLocalSizeForSubgroupCountOpGroupNonUniformInverseBallotOpRayQueryGetIntersectionWorldToObjectKHRcombined imagesRayGenscheduleAHitpayloadStackPtr != NULLval && "No value to store"stack.store.restore!ty->isAggregateType() && "we don't support nested aggregate types"mailboxOffsetWDir != NULLtMax != NULLvalCall && "expect CallInst"CI && CI->getBitWidth() <= 32 && "invalid val to get i32 from"lower32stbl.dispstbl.base (ijNonPerspCenter) (GreaterEqual) (TCS)uavWriteMask: needsDrawID: inputVertexCount: [ADRENO_PS_BARY_INPUTS] (Ver ijUsageMask: packFactorX: gsOutputs[needsWGSize: constantS: [ADRENO_INITIAL_TEXTURE_LOAD][staticReads: numGroups: mappings: emulatedGroups[renderTargetIndexIncr: allocationType: useBindlessTexture: primSize: fbFetchMask: ssboInfo: shaderHandle: imageAttachmentIndex: regId: outputTopology: fixedSubstateID: .majorVer.metadataStaticSize[ADRENO_SHADER_SAMPLER_USAGE][ADRENO_SHADER_BEHAVIOR].virtualRegisterIndex.needsPrimitiveOrder.outputsShadingRate.needsInstanceID.outPrimType.viewIDVirtualRegID.zOutputRegID[ADRENO_BOOLEAN_CF_MASK_INFO].bindlessSamplerSupport.objSize.enableSPMLMode[ADRENO_HS_PSO_MERGED_SHADER_DESC].imageInfo.name[ADRENO_MS_VSPASSTHRU][ADRENO_BINDLESSBASE_USAGE_INFO].viewDependentVisibilityStream.rcInfo.bindlessBaseUsage ============ No shader code specified .NumConstantsSECT_DEF_CONST_BUF_TABBinningMeshFragmentShaderpreamble_texld - gpixel : %8d - non-preempt st: %8d - stc : %8d,%8d (rpt), ratio %5.2f - stgen : %8d,%8d (rpt), ratio %5.2f - ray_int : %8d,%8d (rpt), ratio %5.2f - Barriers : %8d - ccinv : %8d syeipreamble_lsync - Half Registers : %8d num_of_output_componentsalu_rpttexld_rpttex.rcktex.sadmem.ldlwmem.atomicg_rptmem.reslayoutmem.stsc_rptSkipGarbageCollectDisableDynamicCBCachingGLAPITypeGenerateTraceRayShaderNumViewsEnableA7pLDGASTGABGESubsampledCBPtrDoBinningVSEnableSafeNormalizeIsDynamicConstRangeSubgroupSizeModeEnableCBUAVWriteSWASOGECountSOBGECountShutdownQNGC_MajorVersionIDRESOURCE_SIGNATURE_STATIC_SAMPLERresourceConstantIdSPECIALIZATION_VALUESresourceValue="index=" Dxx Unable to parse ShaderDumpFlags value 'Unable to parse Nv12RenderTargetMaskWA value 'Unable to parse ForcePerWavePvtMemLayout value 'Unable to parse Enable3rdCoordForInitTex value 'Unable to parse EnableUseTextureForROImage value 'Unable to parse BGECount value 'Unable to parse ResourceHeapBindlessBase value ' ShaderBinary (__null): load shader from shader binary DisableMinPrecisionOps (false): Disable minimum precision instruction support for DX11.1 ASICRevision (TargetData::REV0): Which revision of the ASIC to compile for EnableConstColorBypass (false): Enable Const Color Bypass for PS in A6x+ EnableLiteralPreloadViaPreamble (false): (a6x+) Use premable to load literal(DCB) EnableDispatchBaseForWorkgroupID (false): [Vulkan1.1] dispatch non-zero workgroupID ForceHighpCommon2Functions (0): Force highp for more common functions EnableVKPreRotationPatching (false): For Vulkan, enable rotation patching of gl_FragCoord. This option and enableFSFovPatching can't be simultaneously on. EnableVPCDecoupling (): Decouple the VPC index from the virtual register (previously it was hard-coded to 4*VReg+Comp). EnableConditionalMsaaForFbFetch (): Enable conditional MSAA for framebuffer fetch (ESX only) EnableFP16DenormPreserve (): Preserve denorm of half precision floating point operations End of comment not found. A615 ProfileMask:0x" varName="Symbols with same virtual register index have different vpc indices, error in compiler-generated metadata. pExtractsPtr + pExtractsDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"Unable to read object file, compilation failed? Too many symbols found in table, expected a single symbol entry. This gives information about a device memory allocation made during compilation. Version 1.0: Added allocationHandle Added allocationSize Shader stage independent information about features the shader uses. Version 1.0: Added stackNestingLevel Added usesKillInstruction: true if the shader uses kills (PS, GS) Added dynamicallyIndexesConstantBuffers Added dynamicallyIndexesTextures Added dynamicallyIndexesSamplers Version 1.1: Added usesPushConstants: true if shader uses push_constant blocks Version 1.2: Added useRasterizerAccessOrderUAV: true if shader uses rasterizer order access UAV Version 1.3: Added numTexSamInst: number of texture sampling instructions Added numTexSamInLoop: number of texture sampling instruction inside loops that aren't unrolled Version 1.4: Added usesUAVs: true if shader references UAVs Added usesCBs: true if shader references constant buffers Version 1.5: Added fpDominate: true if full precision ALU2, ALU3, and MOV >= half precision Version 1.6: Added numFullALUInst: number of full ALU instructions Added numHalfALUInst: number of half ALU instructions Added numEFUInst: number of EFU instructions Added numLoadStoreInst: number of load/store instructions Added numFlowInst: number of control flow instructions Version 1.7: Added usesRelativeAddressing: true if shader uses relative addressing Version 1.8: Added hasRelativeAddressingInBranch: true if there is relative address ALU instruction inside branch block Version 1.9: Added numVectorALUInst: number of vectorized (repeated) ALU instructions Added numScalarALUInst: number of scalarized ALU instructions Version 1.10: Added usesBlockMatchInst: true if the shader uses block match instruction Version 1.11: Added fetchFrameBuffer: true if the shader fetches the frame buffer Version 1.12: Added hasAtomic: true if Shader has atomic operations. Information about generated HW shader. Version 1.0: Added shaderType Added isBinning: true if the shader is to be used for binning Data describing special inputs for the CS. Updated for A5x to reflect the fact that constants have moved into uGPRs. Version 1.0: Added needsWGID: true if the shader uses the workgroup ID Added needsWGSize: true if the shader uses the workgroup size Added needsWGOffset: true if the shader uses the workgroup offset Added needsLocalId: true if the shader uses the local id Added localIdRegID: Temporary register where hardware stores the group thread ID (3 components). Added wgIDUGPRIndex: UGPR where hardware stores the ID for the thread group (3 components). Added wgSizeUGPRIndex: UGPR where hardware stores the size of the thread group (3 components, unused for dx). Added wgOffsetUGPRIndex: UGPR where hardware stores the offset of the thread group (3 components, unused for dx). Version 1.1: Added needsLocalLinearId: true if the shader uses the local linear id Added localLinearIdRegID: Where to store the local linear ID. Too many virtual registers with clip/cull distances. getType(), CoordVT){Errata#70}bf16.o(-inf)sign.faddh.u32mad.f16mad.m32.f32f32f16mad.m32.f32f16f32shrg.b32shlg.b16exp2hgetonergetinfol2gldgenshfl.rupatomic.b.dec.rgatomic.b.xorQTM->get_stack_size(CallerFunc) && "evaulated stack sizes in wrong order"SO steamout entry field is not a constantpMD != NULL && "Unexpected MS vertex attribute metadata operand"qgpu.as.metadataImmMulOnly || QTM->getConstSlotID() != ~0U && "Trying to use constSlotID before initializing it"qgpu.symbols.unsignedinitLocTobeMod <= UINT32_MAX && "Program scope pointer offset exceeds max supported"ReqdMinFootPrint >= NetFootPrint && "Cannot achieve target number of waves by increasing footprint"SamID <= 15 && "The sampler index to use for sampling (0-15)."MinNopsPreserveMinRegsBalancedUnifiedEnable unified schedulerssMatchDstTy && "must have dstTy for new intrinsic"Enable cl constant optDisable relative LM broadcasti < 4 && "failed find dest reg in LDC"CondSrcDstType!=QGPU_DT_INVALID && "condition dst has unexpected type"_op1_lo_5bitsllvm.qgpu.vec.Ldx.v2i32.p1v2i32.i32.i32llvm.qgpu.vec.stthr.p1v2i32.v2i32.i32.i32false && "getEmulatedOperand errors"idxOp && "idxOp null !"ptrTy && "get.reg address is not a pointer type"fi#DNode->NumInEdges > 0 && "Negative # of edges?"false && "Live interval not found"missing temp vector hintRedundant vector hint, type: i < Length && "Invalid index!"Slots away a use must be from the promotable def to use the original defDefMI && "DefMI can't be null"Erased && "mbb is not active"0 && "key tagged as more uniform"itex-countenable-backedge-fixupsfatal flex scanner internal error--end of buffer missedthe ldx.a instruction should use g with source 0. Usage g[c8.x+r4.x+32] LDST: Out of Range Offset with ldx instruction. Allowed Range is 13bits, |0 - 8191|.WARNING: STX.a with RRI form only allowed from a7p for STI, if Source Operand1 is GPR, it should be Half RegisterLDIB: LDIB length is out of range. Allowed range is 4 .LoadStore: for pipr instruction src0 should be full GPR or full ConstantMemory LoadStore: GetFiberID instruction not supported in a5x and below LoadStore: for stc instruction allowed only from a6x the Source1 Operand should be Full Register onlyALU3 - SHIFT MASK: b32 is for 32 bit sources src[0]Only .y component is allowed with address register a1 SWZ - Relative addressing not allowedSource operand3 cannot be ImmediateValueTexture: quad.shuffle instr dst type should be a GPRTEXTURE: Source0 operand can not be predicate/IMM Value.Only GPR (r/R) Relative Address Mode can be used with DestinationpipePATCH2 Invalid topology Type with dcl_output_topologyBARYPERSPCENTERVIEWIDPERSP_CENTERPERSP_CENTROIDTEXCUBEAMINSINSTRMULFMUL2INSTRLOADGAU16INSTRLOADGENU8INSTRSTGAS32INSTRSTXAS8INSTRSTPF16INSTRLOADGBT1DU32INSTRSTGBT1DINSTRSTGBAT2DINSTRMEM_TYLOADLVSPINSTRRGETPOSINSTRATOMXCHGGSOCU32INSTRATOMINCRGGSOCS32INSTRATOMDECLNGSOCS32INSTRATOMBADDGU32INSTRATOMBAADDGU322DINSTRATOMBADDGS32INSTRATOMBADDGS323DINSTRATOMBSUBGU321DINSTRATOMBSUBGS32INSTRATOMBAANDGU32INSTRATOMBANDGU323D1LINSTRATOMBCMPXGU642DINSTRATOMBACMPXGU32INSTRATOMBAXCHGGU32INSTRATOMBAINCGS321DINSTRATOMBDECGS323D1LINSTRATOMBDECRGGS323DINSTRSUBSINSTRGATHER4GINSTRSAMLDP2INSTRATOMXCHGLS32INSTRATOMORLS32INSTRATOMMINGS32INSTRSTIU16INSTRSTIBF323DINSTRSTIBAS321DINSTRSTIBAU323DINSTRLDIBF321DTINSTRLDIBS322DRCKINSTRLDIBF321DRCKINSTRLDIBAS321DTINSTRSTIBU321DTINSTRRESBASE1DTINSTRRESLAYOUT3DINSTRSWZU16U32INSTRSWZS16U32INSTRSWZU32S16INSTRATOMDECLNGENS32INSTRLDIBUNTYPEDS323DINSTRLDIBTYPEDU322DRCKINSTRLDIBTYPEDS321DRCKINSTRLDIBTYPEDF321DRCKINSTRLDIBTYPEDF322DRCKINSTRSTIBUNTYPEDU161DTINSTRLDIBBLKGS322DINSTRSTIBAF162DINSTRLDIBF163DINSTRSTIBBLKF323DINSTRGATS16F16INSTRGATU32F32INSTRSCTF16INSTRSCTF32S32INSTRSHFLRDOWNINSTRSHFLUPU16INSTRSHFLDOWNW4U16INSTRRAYINTINSTRPLUSFLOAT32TOKENDECLARE_TESS_DOMAINDCL_PS_TEX_ENTRY_UIDDCL_PS_TEX_ENTRY_DSTIDRENDER_TARGET_TOKENGETFIBERIDINSTRLDIBAINSTRBUFINFOINSTRATOMGINCDECSTRATOMGENINCDECSTRSTLINSTRUAVTYPEDIMSHRINSTRMADM32INSTRDEST_REGISTERSOURCE_CHANGE_PARAM3DCL_SYMB_REGADDR_QUALIFRETURN_TYPEsyntax error, unexpected %s, expecting %s or %s or %sALU2: last-use-if-source-is-a-GPR is allowed only for General registerALU2: Predicate registers cannot be source operand.LDST: Destination operand type cannot be mailboxSTIB.BLK: src1 has to be sGPR.LDST: dst can not be sGPR.registerUsagePerFibershaderAllocationscbufferUsageinputsmergedShaderDesc_A6XADRENO_SHADER_BINARYADRENO_GS_OUTPUTSADRENO_CS_INPUTS_V2ADRENO_MS_OUTPUT_ATTR_STRIDESADRENO_SCREEN_COORD_TEX_USAGE_INFOtesPrimSizetesBinningvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/Context.cppMAX_FRAGMENT_ATOMIC_COUNTERSMAX_FRAGMENT_ATOMIC_COUNTER_BUFFERSMAX_COMPUTE_ATOMIC_COUNTER_BUFFERSMAX_SAMPLESTESSELLATION_POINT_SIZEEXT_FRAGMENT_INVOCATION_DENSITYMaxDrawBuffersMaxCombinedImageUniformsMaxTessEvaluationUniformComponentsMaxUniformLocationsTF Varyings:============ Specialization Info ============ specializationCountindexGL_SAMPLER_CUBEGL_INT_SAMPLER_CUBEQGL_TEXTURE_EXTERNAL_YV12_AMD readonly, Struct Idx = %d numScalarRegisters = %d parentUBO = %s$GLComputeNumWorkGroupsUVec3Tessellation Patch Const SizeGL_ViewID_OVR in multi_view modeVertexRay GenerationClosest HitMisssampleGroupSizeInSameTextureenableSafeModeNopenableLegacyCBPreloadViaPreambleforceOutputQGLC optimize setup((waveSize == 1) || (waveSize == 2)) && "incorrect waveSizeMode picked up"llvm.qgpu.global.fset.reg.p0f32.v2f32llvm.qgpu.global.scalar.alloc.reg.p0i16.p0v3i16llvm.qgpu.global.scalar.alloc.reg.p0f16.p0v4f16llvm.qgpu.icreate.map2.v2i16.i16gl_PositionfsIndex > 0ERROR: matrixMe->getRowSize() == 3 && matrixMe->getColSize() == 3 && "matrix column/row size is not three!"(gvTy == mInt16Ty) || (gvTy == mInt32Ty) && "subgroupInvocationID is expected to be a scalar int type"false && "vec8/10 is expected"yuv_testi16false && "invalid implicit casting"qgpu.glsl.addrspace.coherent.volatile.setgl_WorkGroupIDstructRetTypeID != QGLC_INVALID_INDEX_VALUE && "struct type return is expected"sourceOver((subgroupSize == 16) || (subgroupSize == 32) || (subgroupSize == 64) || (subgroupSize == 128)) && "Invalid subgroup Size Specified "fn && "Unable to insert trace ray impl"$setupBaryN_j_over_w(opnd->isInt() || opnd->isUint()) && "int/uint expected"component < 4false && "get.sym.loc intrinsic ID expected"gl_CombinedClipCullDistances0setReg != NULL(((llvmType == LGT_BUILTIN_INPUT) || (llvmType == LGT_BUILTIN_OUTPUT)) && "Incorrect global type for creating semantic variable \n")cat != LGT_UNKNOWN && "category must be known"Error: Compute shader declared shared variable exceed limitError: Tessellation control shader specify invalid out vertices numbervTessFactorGlobalLocation64intToPtrInst && "Invalid Index for tess factor index"Positiongl_VertexIndexgl_MaxGeometryAtomicCounterBufferssampler2Dsampler2DMSArrayfalse && "unsupported symbol type"Mismatch between IRShader compiler architectures.(samplerVar != NULL) && "sampleVar == NULL"srcAddr->getType()->isPointerTy() && dstAddr->getType()->isPointerTy()node->getOp() == EOpParametersfalse && "matrix constructor can't take another matrix as an argument!"us2iimg2dmsisinfnotEqualumulExtendedtextureLodCall to undefined function!^^elselineno operation '%s' exists that takes a left-hand operand of type '%s' and a right operand of type '%s' (or there is no acceptable conversion)It is an error to have no statement between a label and the end of the switch statementcan't modify gl_MaxFragmentUniformVectorscan't modify gl_MaxGeometryAtomicCounterscan't modify gl_MaxGeometryAtomicCounterBufferscan't modify gl_ShadingRateFlag4HorizontalPixelsEXTtoo many argumentscannot declare arrays of this qualifierrequires extension cannot construct sampler type with the constructorcan't convertubo/ssbo member type can only be int/uint, float, vector, or matrix. It can not be: left of '[' is not of type array, matrix, or vector blockTypeList != __nullcertain layout qualifiers are allowed only for incompute shader is only supported in GLES 3.1 or aboveMul Assign *=Compare Equal ==Compare Not Equal !=Compare Less Than or Equal <=Bit field reverseTexture2DShadowProjImageStore2DImageAtomicOrBad aggregation opEquality operators are only allowed on arrays of equal size and typenewCstUnion && "OOM"gl_DepthRangeParameterstexture2DLodtexture2DProjLodmemoryBarrierimageAtomicAndimageAtomicCompSwapgl_PrimitiveShadingRateEXTisamplerBufferIdentifiers can't be more than 1024 characters.can only define identifiers.extension name not specifiedExtended instruction UnpackDouble2x32 not supportedNonSemanticonly 16 bit denorm preserve is supported$SSBO_ is allowed only in an codeGenHelper->getMainEntryBB() && "The main entryBB does not exist!"OpFunctionParameterOpGroupDecorateOpIAddOpUDotKHROpLessOrGreaterOpSLessThanOpFUnordLessThanOpGroupReserveWritePipePacketsOpGetDefaultQueueOpImageSparseSampleDrefExplicitLodOpTypeNamedBarrierOpGroupNonUniformQuadSwapOpReportIntersectionKHRfalse && "Atomic Counter should have binding set"val && "val is Null"spivModule != NULL && "Can't get Spiv module from shader binary!"isa(op) && "expect Alloca instruction"storeValue != NULLsubstate.to.mailbox.ptrgetCommittedAttrsAddrsrb.data (TriangleCW) (ijNonPerspCentroid) (Disabled) (ITU_601_FULL_RANGE) (ITU_709) (Geometry) (UBO)[ALLOCATION] (Ver metadataDynamicSize: words: useWithoutFormatUAVMask: dynamicallyIndexesTextures: hasAtomic: ]: domainType: needsDomainV: needsFragCoord: needsZrhW: outputsZ: globalOffsetConstID: hasBarrier: [ADRENO_GS_OUTPUTS][hwShaderSizeWithoutGlueCode: logString: isBindlessLoad: constantT: constColorBypass: initialIJCoordinate: [ADRENO_ASTC_PATCHING_STATIC_READ][apiBindlessGroup: hwBindlessGroup: numMappings: [ADRENO_SHADER_DEBUG_INFO] (Ver HWCodeCRC: unsizedArrayStride: sizeInBytes: structName: pSymbols: virtualRegIndex: [ADRENO_DESCRIPTOR_GROUP] (Ver vpcId: startVaryID4PA: [ADRENO_BINDLESSBASE_USAGE_INFO] (Ver shaderCRC: ]: .allocationSize.scratchSizeInDWORDs.textureUsageMask.needsVertexID.localLinearIdRegID.disableTiledWIRasterization.localMemoryUsedBytes.shaderType.sourceTextureSlotIndexBase.baseTextureIndex.numDynamicReads.originalComponent.numTextureMappings[ADRENO_HW_SPECIFIC].arraySize.bindlessSamplerOffset.hwCRC ======== non-NULLSECT_CONST_TABMeshAmplificationShader - All Instructions: %8d,%8d (rpt), ratio %5.2f flat_bary - inittex : %8d wavesynclsyncsya0half_move_rpttex.imm_atex.dsylockR_rptmem.shflmem.ldga_rptmem.preamble_bindlessiShort latency sync instruction countEmulateSBufUAVAsRawSpecializationResNamePtrOutputMetadataNamedOutMetadataListVerifyAsmQuietOutputCompileStatsDisableCentroidBGEIsUsingSingleBasePtrEnableASTBlobCachingDisableGatherPatchingForceConstantRAMModeUseMSAARenderTargetStreamOutDataSRefEnableFP16DenormPreserveBindGroupElementsUnrecognized context option 'rangeTypeRootSRVcolorSpaceTransformInvaildROImageError parsing resourceValue data ' Unrecognized output name, metadata request failed Shutdown (false): Call llvm_shutdown on context destruction (used for statistics/pass timers A5xUnable to parse EnableEarlyPreamble value 'Unable to parse DumpObjToDebug value 'Unable to parse ForceBinningShader value 'Unable to parse EnableRootConstBrac value 'Unable to parse EnableMultiPositionOutput value 'Unable to parse InputPrimitiveType value 'Unable to parse EnableStateCacheWarmInPreamble value 'Unable to parse BGESize value 'Unable to parse EnableUseTextureForROSSBO value 'Unable to parse EnableUseTextureForLargeUBO value ' ReservedLocationsBufferRef (__null): reserved location buffer array location EnableMultiChannelUAVLoads (false): Enable full 4-channel loads for typed UAVs instead of just 32-bit data VPIndexValues (__null): Viewport array index output value per view EnableEndOfLocalMem (false): (a7p) Enable end of local memory access RelaxExtensionPPCheck (false): Relax extension preprocessor checks DisableImplicitConv (false): Disable implicit conversions ForceHighpMatrixFunctions (0): Force highp for matrix functions EnableVRS (false): (a6x+) Enable VRS AllCompilerOptions2 (0): Encoding of a subset of compiler options specified in the interface SOGEData (__null): Array of stream out elements Preserve32bDenorm (): Preserve 32bit denorm EnableAliasForLDST (): Enable alias for LD/ST to support bindless descriptors MaxRecursionDepth (): from maxPipelineRayRecursionDepth. ShaderCollection A405A615 A505 A710 ,Len:0x,Size:No group example passed in, wrong function called? pStreamOutElePtr + pStreamOutEleDesc->m_ElementSize * i && "memcpy dest pointer is NULL!", structure verification failed. This includes information about new HW features. Version 1.0: Added disableInstancePacking: true if Shader use instance based per-wave uniform Added enableSharedConstant: true if Shader enable shared constant for push_constant UBO. Added constantRAMMode: Compute shader constant ram mode, only valid for compute shader. Version 1.1: Added hasEarlyPreamble: true if Shader has early premable section. Version 1.2: Added usesDCB: Whether or not the shader references the DCB. Version 1.3: Added enableSPMLMode: new HW execution mode to enable ALU/SALU/SEFU read data directly from LM. primitive size (both patch buffer and tess factor buffer) in a HS in pipeline. Version 1.0: Added inputControlPointCount: The number of vertices feeding into the HS.(DX only) Added outputControlPointCount: The number of vertices written by the HS. Added patchConstTessFactorSize: The size in bytes of tessellation factors written by the HS. Added primSize: The size of a primitive in bytes. Version 1.1: Added primSizePerVertex: This value will be passed as a name constant to the TES for address calculation purposes in SSO mode. Added patchConstantSize: This value will be passed as a name constant to the TES for address calculation purposes in SSO mode. Compilation failed to complete (id= SUBhyphentwoREG_EBRACK-Inf0APInt(= *unknown option value* error: Write -stats and -timer output to stdout instead of stderr (iosopenbsd;MultisampleFeedbackMaskvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/ADT/ilist.hugt addisa(Val) && "cast_or_null() argument of incompatible type!" memory_scope_deviceinreg nest noredzone fast N < NumContainedTys && "Element number out of range!" bit offsetgpu.get.rt.stbl.baseaddr.callablellvm.arm.mcrllvm.arm.mrcllvm.arm.neon.vld1llvm.arm.neon.vpaddllvm.arm.vcvtrullvm.atomic.load.uminllvm.atomic.load.xorllvm.eh.return.i64llvm.gcrootllvm.hexagon.A2.andirllvm.hexagon.A2.sxtbllvm.hexagon.A2.vavgwllvm.hexagon.A4.rcmpneqllvm.hexagon.A4.vcmpheqillvm.hexagon.F2.conv.sf2dllvm.hexagon.F2.dfaddllvm.hexagon.F2.dffixupdllvm.hexagon.F2.sfclassllvm.hexagon.M2.cmaci.s0llvm.hexagon.M2.mpy.nac.ll.s0llvm.hexagon.M2.mpy.rnd.lh.s1llvm.hexagon.M2.mpyu.acc.lh.s0llvm.hexagon.M2.mpyud.acc.hl.s1llvm.hexagon.M2.vdmpys.s0llvm.hexagon.M2.xor.xaccllvm.hexagon.M4.mpyrr.addillvm.hexagon.M4.vpmpyhllvm.hexagon.S2.asr.i.p.rnd.goodsyntaxllvm.hexagon.S2.asr.i.r.rnd.goodsyntaxllvm.hexagon.S2.lsl.r.pllvm.hexagon.S2.lsl.r.vhllvm.opencl.get.image.width2llvm.opencl.read.image1u.illvm.opencl.read.image.no.sampler.1ullvm.ppc.altivec.vaddubsllvm.ppc.altivec.vpkuwusllvm.ppc.altivec.vsubshsllvm.ppc.altivec.vsububsllvm.qcom.s162f16llvm.qgpu.fcombine31llvm.qgpu.fcombine32llvm.qgpu.fcreate.map3llvm.qgpu.fsample16.packedllvm.qgpu.get.asptrllvm.qgpu.get.mesh.global.group.idllvm.qgpu.get.stack.pointerllvm.qgpu.global.fget.regllvm.qgpu.icombine50llvm.qgpu.icreate.map60llvm.qgpu.imaxllvm.qgpu.uav.resinfollvm.spu.si.cgxllvm.spu.si.fcmeqllvm.spu.si.fmllvm.spu.si.mpyhllvm.spu.si.xorllvm.x86.3dnow.pfmaxllvm.x86.aesni.aesenclastllvm.x86.avx.storeu.pd.256llvm.x86.avx.vbroadcast.sd.256llvm.x86.avx.vextractf128.si.256llvm.x86.fma4.vfmsubadd.pd.256llvm.x86.mmx.punpckhdqllvm.x86.sse2.cvtsd2sillvm.x86.sse2.pmovmskb.128llvm.x86.sse41.pminsbllvm.x86.sse41.pmovsxbwllvm.x86.sse.cvttpd2pillvm.x86.sse.max.ssllvm.x86.sse.rcp.psllvm.x86.sse.rcp.ssllvm.x86.sse.ucomigt.ssllvm.x86.ssse3.phadd.sw.128llvm.x86.ssse3.phsub.d.128llvm.x86.ssse3.phsub.w.128llvm.x86.xop.vpmadcswdllvm.xcore.getstllvm.xcore.outshrOffset.getBitWidth() == DL.getPointerSizeInBits(getPointerAddressSpace()) && "The offset must have exactly as many bits as our pointer."DetailsTy && "Value defined with a null type: Error!"chAttribute sret not on first parameter!PHI node has multiple entries for the same basic block with different incoming values!Duplicate integer as switch caseIt should have at least one range!Range types must match load type!Atomic store must specify explicit alignmentatomicrmw instructions must be atomic. is not an integral vector type.FK_SecRel_2__text .type .secrel32 \b, value: expected assembly-time absolute expressionunable to write nop sequence of R.data<>(target1)GOT_CALLABS_HIINVALID.data.rel.rodata.cst8\\progbitsS_LAZY_DYLIB_SYMBOL_POINTERSthread_local_zerofill (ignoring processor) invalid natural stack alignment (S-field), must be a positive 8-bit multipleisVirtualRegister(Reg) && "Not a virtual register"atanfcopysignexp2fmExitBBmodModRefprint-no-aliasesvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Analysis/IVUsers.cppNumber of FDiv insts ScalarNumber of AtomicRMW instsNumber of SExt insts ScalarNumber of FPToUI instsNumber of FPExt instsNumber of pairs with independent accessesExact RDIV applicationsNatural Loop Informationloop-weightno-profileprint-region-styleRegion tree: Node && "MDNode is Null"CtrlDepGraph analysisCurPHI && "CurPHI is NULL".unr-lcssa.unr2-lcssanotunwindNumber of alloca's promotedNumber of IV comparisons eliminatedUnify function exit nodesemit_counterbb-vectorize-splat-breaks-chainAttempt to vectorize horizontal reductions feeding into a storeCombine redundant instructionsTI && "TI cannot be NULL"qgpu.allow.fp.conv.foldingNumber of blocks eliminatedNumber of GEPs converted to castsNumber of instructions simplified or DCE'denable-preNumber of instructions simplifiedDepSI->getParent() == L->getParent()Number of loads deletedNumber of memory locations promoted to registersNumber of loops deletedloop-reducepost-incNumber of registers demotedNumber of scalar allocas adjusted to allow promotionfalse && "Invalid GEP iterator"Number of allocas broken upReassociate Scalar Vector expressionRemove dead machine instructionsdisable-ifcvt-triangle-revifcvtNumber of triangle (F/R) if-conversions performedS < E && "Cannot create empty or backwards range"-phikillLevel && "Cannot erase root node"Number of virtual frame base registers allocatedADDRESS TAKEN BB#Number of dead copies deletedMachine Module InformationMBB exits via conditinal branch/branch but there's no condition!- basic block: Instruction inside bundle has a slot indexInvalid register class for subregister indexInstruction index out of orderdisable-tail-duplicateAfter ExpandPostRAPseudosLI_Info->VecInfo == NULL && "VectorIntvInfo object is already created?"&SA->getParent() == &VirtReg && "Live range wasn't analyzed"LI_Info != NULL && "Null interval"Ret && "Inconsitent result for eviction test"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/RegisterClassInfo.cppgc_savedheadlsda_gepunreachableblockelim WidenedVectorsdisable-dfa-scheddisable-sched-reg-pressureUse jump table with low range saturation to speedup switch <= FIRST_MEM_ORDER && AtmOrdering <= SequentiallyConsistentNumExt <= 64 && "Coord more than 64!"false && "Abs not supported for type"BitCasttb.mmmin.ftrunc.fmad32.u16covballgetinfoatomic.b.addgetspidF != NULLMI->getOperand(0).isMBB() && "GETONE target is not MBB!"LastOne <= CIndex2OpIndexMap[Val].NumElements && "More component than vector declartion?"qgpu.ms.prim.attr and < UImmNotAllowedValError: The register relative offsetmust be within [-512,512).DstModNotAllowedError: Choose scheduling heuristic rulemax-moveenable-a1-commoningfalse && "Invalid dst type of sampler instruction"CachedMI->getOpcode() == MI->getOpcode() && "Mismatching instruction opcodes in SimpleCSE"enable-fold-imm_hi_2_bigDo not emit code that uses the red zone.this->RegFileMode == QTM->getRegFileMode() && "Inconsistency in register file mode"LI_WithRegAlias->getChild() == NULL && "RegAlias interval must not have any child interval"isSpillable(LI) && "This live interval cannot be splitted"TBB!=NULL && "Broken CFG?"isDefined() && "undefined"Optimize QGPU vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUUGPRPromote.cppITex check killvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUBackedgeFixups.cppCond.size() == 0 || FBB != NULL.1D option is allowed only for ISAM instruction.out of dynamic memory in yy_get_next_buffer()Next token isthe ldthr.a instruction should use g with source 0. Usage g[c8.x+r4.x+32] LDGB: No LDGB length required for TYPED UAV.the ldgb.a instruction not allowed in a6x and above LDIB: For stx.a Source1 should always be Immediate Value the stgb instruction .len is 2 bits with range |1-4| LDST: Destination offset Out of Range with g2l instruction. Allowed Range is 13bits, |0 - 8191|Src0ARRESINFO: for src baseid 5 is only for src mode 5/6 for a6x and aboveLoadStore: for stc instruction dst should be constant memory address LDG.k: Out of Range Offset with ldg.k instruction. Allowed Range is 13bits, |0 - 8191| the Source2 Operand should be Full Register onlyALU2 ADDH: DST can be 32 bit only.HIGHALU3 MAD: DST is 32 bit but all source operand are not 32 bitALU3 - SHIFT MASK: b16 is for 16 bit sources src[2]ALU3 WMM: src1 gpr range is between 0 to 47.GAT - This instruction cannot be repeated Texture: .l options are only allowed for texture gather4x instructions in a6xFLOAT16dcl_constpointerPATCH6INPUTBARYNONPERSPCENTERTESSFACTOR$endADDFINSTREND_INSTRLTOPCODECOVS16U32INSTRENDQUADTOKENLOADGAS32INSTRLOADTHRCCHEU16INSTRLOADTHRS16INSTRLOADLS16INSTRSTGS32INSTRSTGF16INSTRSTGAU32INSTRSTXAS32INSTRLOADGBT4DU32INSTRBANYINSTRBRAXINSTRSTKRINSTRATOMDECGENSOCS32INSTRATOMMINGGPUU32INSTRATOMBMAXGNU321DINSTRATOMBSUBGS321DINSTRATOMBSUBGS321D1LINSTRATOMBMINGS322DINSTRATOMBAMINGS323D1LINSTRATOMBORGU321DINSTRATOMBAXORGU32INSTRATOMBXORGU323DINSTRATOMBACMPXGU321DINSTRATOMBCMPXGS32INSTRATOMBXCHGGU321D1LINSTRATOMBAXCHGGU323DINSTRATOMBAXCHGGS321D1LINSTRATOMBINCGS321DINSTRATOMBAINCGS322D1LINSTRATOMBAINCLNGS322D1LINSTRATOMBDECGS321DINSTRATOMBADECGU322DINSTRATOMBDECLNGU322D1LINSTRSELS32INSTRLOGINSTRVECLENVALATOMORLU32INSTRATOMORGU32INSTRATOMMINGU32INSTRAROMDECLU32INSTRBUFINFO2DINSTRSWZS32U32INSTRGETCYCLEINSTRATOMMAXGENU32INSTRATOMINCRGGENU32INSTRLDIBTYPEDU322DINSTRLDIBTYPEDF322DINSTRLDIBUNTYPEDF321DTRCKINSTRLDIBUNTYPEDS161DRCKINSTRSTIBTYPEDU322DINSTRLDIBBLKCU163DINSTRSTIBBLKU163DINSTRSCTF16S16INSTRTCINVINSTRSHFLRUPW4U32INSTRSHFLRDOWNW4U32INSTRUNSIGNED16TOKENHEXADECIMALTOKENDCL_CL_LOCAL_ID_TOKENPCREGDCL_CL_KENTRYOFFSET_TOKENDEC_CONST_REG_COUNTICINV_INSTRLOCK_INSTRATOMGINSTRMOVAINSTRGATINSTRTEX_INSTR_2 ALU3: Source Operand cannot have IMMEDIATE Values until A8x. LDST: Destination operand type can be sGPR only for LDC/LDC.a instructionpositionSymbolsconstantBufferCachevsInputsmergedShaderInputs_A5XADRENO_SHADER_CBUFFER_USAGEADRENO_PS_DESCADRENO_BINDLESS_GROUP_MAPPING_RANGEGL_PROGRAM_DATAGL_SYMBOL_INFO_UBOADRENO_SCREEN_COORD_TEX_USAGEbindlessBasesSSBOArrayMAX_VERTEX_ATTRIBSMAX_VERTEX_UNIFORM_VECTORSMAX_VERTEX_TEXTURE_IMAGE_UNITSMAX_UNIFORM_BLOCKSMAX_BUFFER_BLOCKSMAX_OUTPUT_BLOCKSMAX_TESS_EVALUATION_OUTPUT_COMPOENTSMAX_COMPUTE_UNIFORM_COMPONENTSMAX_TESS_CONTROL_ATOMIC_COUNTERSNON_CONSTANT_GLOBAL_INITIALIZERSEXT_FRAME_BUFFER_FOVEATED shaderEntryPoint = MaxCombinedTextureImageUnitsMaxTessEvaluationAtomicCounterBuffersMaxAtomicCounterBufferSize ResourceValueSize : 0xGL_SHORTGL_INT_SAMPLER_2DGL_SAMPLER_2D_RECTGL_UNSIGNED_INT_SAMPLER_BUFFERYUV Active, SUCCESS.qgpu.invariant.position$VertexSizeUint32$TFBuffer2BasePtr64$SharedMemGlobalBasePtr32$BinScaleIvec2Screen Bottom-Left LocationAdvanced Blending Equations Mask (uint32)SupportRotationModeInTPenablePackSmallWorkGroupmatrix_functionsllvm.cos.f32llvm.exp2.f16llvm.qgpu.imad.i16llvm.qgpu.global.iget.reg.i16.p0i16llvm.qgpu.fcombine3.f32llvm.ctz.i16output(entry.size() == 3) && "combined sampler using bindless cb needs 3 bindless group entries"extractInst && "Unexpected user of Layer ldlv"qgpu_mediump(entryInsertPos && exportInsertPos) && "Terminator inst is expected"0 && "TCS I/O with unhandled qualifier"false && "Operator not handled yet in generateOneOpndIntrinsic"false && "wrong struct compare opcode"inst && "Instruction is expected"fiberID && "FiberID cant be Null"0 && "other types are not supported yet"0 && "wrong dst type"src && "src is Null"astType->getStruct()index < objSizeray_initialize__RTget_intersection_t__RTAcceptHitAndEndSearch__qcom_BARY_Coordinate_sample_j$setupBaryN_i_slope_dytessFactorNamedMD != NULLload->getPointerOperand()mCBufferLocationMD != NULL && "Unable to add constant buffer location metadata to module"indexVal && "constant expression is expected for indexing YUV samplers"(indexC < cstArray.size()) && "access out of bound of cst array"setRegInst && ".setreg expected"texCoordOperandType->isVectorTy() && "tex coord must be a vector type"$dummySampleMaskInenable-shared-to-localcheck.sync.for.global.fenceelementTy->isArrayTy()buildIntInputAddr((m_container)->getFlags().bitfields.isRootUniform)attributegl_MinProgramTexelOffsetusampler2DMSArrayutextureCubeuimage2DArrayiimage2DRectE031.41.03.64leftNode->isMatrix()srcTType->getTypeName() == srcTType->getTypeName()false && "unary operator not handled yet"((uap->getType() == EbtInt) || (uap->getType() == EbtUint)) && "case value is not integer!"builtinIndex != -1container->getQualifier() != EvqUniformBuffer && "UBO Array Handling is moved out from this function."s2uimgbfloatBitsToIntconv_standardimageSizeGeometry is only available in ES3.2 or ES3.1 with extension<%can't modify an attributecan't modify gl_MaxTessControlAtomicCounterscan't modify gl_MaxTessEvaluationOutputComponentsInvalide unsized array declaration!varying struct cannot contain an array/structvarying struct or ioBlockstruct that has arrays is not allowed for function returnOnly one push_constant block is allowed per stage.const or precise qualifiers must stay before parameter qualifiersInvalid atomic counter binding/offsetinvalid local_size_z of 0false && "Incorrect symbol type"Mod %Convert Int to FloatAbsolute valueConvert highp to mediump/lowpCompare Greater ThanMaxEmitStreamVertexImageLoad1DArrayImageLoad2DArrayImageAtomicExchangeNo loop condition cstUnion && "cstUnion is NULL"compoffsetsblockInfoatomicCounterISAMPLER1DARRAYpremature EOF"(" expected after 'debug' keywordHexadecimal constant overflow0 && "unsupported type"gl_in[].fragcoordSym && "fragcoordSym is missing."false && "unreachable"OpSourceContinuedOpTypePipeOpConvertFToUOpBitcastOpMatrixTimesMatrixOpUnorderedOpSLessThanEqualOpBitwiseAndOpAtomicUMinOpReturnOpUnreachableOpGroupBroadcastOpImageSparseReadOpGroupNonUniformAllOpGroupNonUniformBallotBitCountOpGroupNonUniformShuffleDownOpGroupNonUniformFMulresN->in.size() > 1 && "expect more than one incoming edges"getBaseShaderID$qgpu.stable.const.missdummyStackFrameSizecurr.frame.basecurr.stinewIdxtotal.rays.for.contextstv0stack.loadvecrcgetRayInfoMissIndexcur.frame.baseprev.offsetdst.ptrindex && "should have a unique call instace to load the shader table index"Unable to initialize target features, unexpected target or already initialized with other target QCC cleanup (Zero) (Sample) (TriangleCCW) (DescriptorTable) (PI2Color) (SampleB)[ADRENO_SHADER_BINARY] (Ver usesSingleRegisterPool: creditVgsDis: [ADRENO_GENERIC_SYMBOL] (Ver numUsedRegs: constantMask: [ADRENO_INPUT_SYMBOLS] (Ver ]: needsRelPatchID: primitiveIDVPCIndex: needsCenterW: localSizeY: isBinning: elements: [ADRENO_INITIAL_TEXTURE_LOAD] (Ver bindlessIndexTexture: [ADRENO_PATCHED_STATIC_ASTC_TEXTURE] (Ver [ADRENO_PATCHED_STATIC_ASTC_TEXTURE][numReads: viewportIndexIncr: [GL_SYMBOL_INFO_SSBO] (Ver uboInfo: isFlat: isIOBlock: ioBlockName: ([ADRENO_MS_VPCPASSTHRU]*) registerUsagePerFiber: rayDataSize: [ADRENO_SHADER_BINARY].numHalfScalarRegsUsed.vGPREn.hasRelativeAddressingInBranch.vertexSize.needsBaryCentricCoord.ijRegIDs.outputsStencil.numOfAttr[ADRENO_CS_INPUTS].needsWGSize.opcode[ADRENO_ASTC_PATCHING_STATIC_READ].instructionOffset[ADRENO_GATHER_SWIZZLE_PATCHING_INFO].extracts.constantExpressions.hasEarlyPreamble[ADRENO_INPUTS].isFlat[ADRENO_DESCRIPTOR_GROUP][ADRENO_MS_VSPASSTHRU_LIST].maxAttributeSizeInBytesShader Source CRC: 0x - MAX : %8d,%8d (rpt), ratio %5.2f - shadow : %8d - getpos : %8d - sampck : %8d - l2g : %8d,%8d (rpt), ratio %5.2f - stl : %8d,%8d (rpt), ratio %5.2f - ldcsize : %8d uvgsconst_reg_compiler_defunified_reg_footprinttex.msaatex.lodmem.g2l_rptmem.bindlessiEnable16BitStorageVerboseEnableBindlessCBPreloadViaPreambleBGEPackedImagePtrEnableNamedConstBracUsePerPixelDerivativeABTexDescriptorBaseGlobalRootSignatureEnableEnhancedPredictionDriverManagedResourcesResourceHeapBindlessBaseDebugStringCallbackQCC_ResourceSignature_DescriptorTypeunsigned intoffsetInDescriptorsFromTableStartpDescriptorTablesQCC_HardwareBufferLocationUAVelementType=" resourceIdentity.resourceName format="Unable to parse SpecializationSize value 'Unable to parse VerifyBC value 'Unable to parse GenerateTraceRayShader value 'Unable to parse EnableSampleShading value 'Unable to parse ValidateLinkResult value 'Unable to parse ForceHighpCommonFunctions value 'Unable to parse ForceHighpCommon2Functions value 'Unable to parse EnablePreloadDrawParam value ' CompilePipeline (false): Compile pipeline of shaders AvailableConstLimits (__null): Set available full vec4 constant registers for each shader stage. Note that each value must be at least 8. If NULL, then defaults are VS: 96, HS: 80, DS: 80, GS: 128, PS: 64, CS: 192 DisableHSPrimWriteCheck (false): Make HS Primitive ID write unconditional ForceHighpTempVariables (false): Force temp variables to use high precision EnableMul2Div2FloatDestMod (): Enable floating point destination modifier for Mul2/Div2 OptStrings parsing is unsupported A540Currently available ASICIDs are: A420 A504 A620 TessOutputPrimitive != QGPU_OBJ_TESS_OUT_PRIM_TRIANGLE_UNKNOWN Which samplers are referred to in the shader. Note that this data is not valid for shaders using bindless, since the indexing used for bindless has no analog here. The driver has the actual resource layout in this case. Version 1.0: Added samplerUsageMask Information about statically indexed textures returned from the shader patching interface for the R24_UNORM patching performance improvement. Version 1.0: Added numTextureMappings: How many texture resource slots were patched. Added textureMappings Data describing special outputs used by the VS/DS. Version 1.0: Added outputsRTArrayIndex: True if the shader writes to the Render Target Array Index. Added outputsViewportArrayIndex: True if the shader writes to the Viewport Array Index. Added rtArrayIndexVirtualRegAndComp: Virtual register location for the render target array index output (vreg * 4 + comp). Added viewportArrayIndexVirtualRegAndComp: Virtual register location for the viewport array index output (vreg * 4 + comp). Version 1.1: Added rtArrayIndexVPCIndex: VPC index for the render target array index output. Added viewportArrayIndexVPCIndex: VPC index for the viewport array index output. vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/QCC/Instrumentation/Instrumentation.cpp vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/QCC/PackPSInputs.cppgetMinSignedBits() <= 64 && "Too many bits for int64_t"may only occur zero or one times! [options] stringDW_TAG_set_typeDW_TAG_catch_blockDW_LANG_ObjCfalse && "Buffer size too large" ---User Time---unknownalignstack }!NodePtr->isKnownSentinel()} > reassoc releasedllexport nounwind uniformwgsize is variable Unknown mangling in datalayout string [Scope: ] llvm.arm.neon.vhaddullvm.arm.neon.vqmovnsullvm.arm.usatllvm.clzllvm.hexagon.A2.subh.h16.sat.hlllvm.hexagon.A2.vcmphgtllvm.hexagon.A2.vsubuhsllvm.hexagon.A4.rcmpeqillvm.hexagon.A4.vcmphgtillvm.hexagon.A4.vcmpwgtuillvm.hexagon.C4.cmpltellvm.hexagon.F2.conv.sf2uwllvm.hexagon.F2.conv.w2dfllvm.hexagon.M2.dpmpyss.acc.s0llvm.hexagon.M2.mmpyh.rs0llvm.hexagon.M2.mpyd.ll.s1llvm.hexagon.M2.mpyd.rnd.hl.s1llvm.hexagon.M2.mpyd.rnd.ll.s0llvm.hexagon.M2.mpyillvm.hexagon.M2.mpyu.nac.hl.s0llvm.hexagon.M2.mpyud.hh.s0llvm.hexagon.M2.vrcmacr.s0llvm.hexagon.M4.vrmpyoh.s0llvm.hexagon.S2.asr.i.p.orllvm.hexagon.S2.extractu.rpllvm.hexagon.S2.lsl.r.p.andllvm.hexagon.S2.lsr.i.rllvm.hexagon.S2.vcneghllvm.hexagon.S2.vsathubllvm.hexagon.S2.vsatwh.nopackllvm.hexagon.S4.addaddillvm.opencl.get.image.channel.order2dllvm.opencl.get.local.linear.idllvm.opencl.read.image.no.sampler.1allvm.ppc.altivec.vavguhllvm.ppc.altivec.vcmpgtuw.pllvm.ppc.altivec.vmsumubmllvm.ppc.altivec.vrlhllvm.ptx.read.nctaid.xllvm.qgpu.atomic.xor.oobllvm.qgpu.dsyppllvm.qgpu.fcombine11llvm.qgpu.fcombine21llvm.qgpu.fcreate.map46llvm.qgpu.get.subgroup.sizellvm.qgpu.globalatomic.opt.WaveSizeMinusOnellvm.qgpu.gpu.atomic.lock.ptrllvm.qgpu.icombine2llvm.qgpu.icombine64llvm.qgpu.icreate.map37llvm.qgpu.icreate.map52llvm.qgpu.ishufflellvm.qgpu.ldcllvm.qgpu.texture.getlodllvm.sinllvm.spu.si.clgtbillvm.spu.si.shlqbillvm.spu.si.xorbillvm.x86.3dnowa.pfnaccllvm.x86.3dnowa.pi2fwllvm.x86.avx2.pmulh.wllvm.x86.avx2.pmulhu.wllvm.x86.avx2.psad.bwllvm.x86.avx2.psll.dqllvm.x86.avx.cvt.ps2dq.256llvm.x86.avx.hsub.pd.256llvm.x86.avx.sqrt.pd.256llvm.x86.avx.vextractf128.pd.256llvm.x86.avx.vextractf128.ps.256llvm.x86.avx.vpermilvar.pdllvm.x86.fma4.vfmsubadd.pdllvm.x86.mmx.padd.qllvm.x86.mmx.pslli.qllvm.x86.mmx.psrli.qllvm.x86.sse2.cvttsd2si64llvm.x86.sse2.ucomile.sdllvm.x86.sse2.ucomineq.sdllvm.x86.ssse3.psign.dllvm.x86.xop.vpcomequbllvm.x86.xop.vpcomfalsewllvm.x86.xop.vpcomledllvm.x86.xop.vpcomleudllvm.x86.xop.vpcomneqllvm.xcore.syncrllvm.xcore.testctinvokesextuitofpA list of OPTs to be disabledscalarrepl.has.aggre.allocav16f16compilation terminated. getInstruction() && "Not a call or invoke instruction!"Integer arithmetic operators only work with integral types!trunc source and destination must both be a vector or neitherFPTrunc only produces an FPBitcast type must not be aggregateAddrSpaceCast requires global/local/private <--> genericllvm.gcroot parameter #2 must be a constant.LandingPadInst not the first non-PHI instruction in the block.Alias should have external or external weak linkage!.subsections_via_symbols\rdiscriminator .seh_startchained, @unwindDW_CFA_def_cfa_register==(PLT)Expr:(.debug_pubtypesregularS_ATTR_SELF_MODIFYING_CODEwsqrtltanhf__cxa_guard_acquiremust aliasrefBoth ModRef partial alias responses mod responses Fview-domdomfrontier (post-inc with loop Number of ICmp instsNumber of UserOp2 instsNumber of UserOp2 insts Scalarvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Analysis/InstructionSimplify.cppBanerjee successesdot-regions llvm.workgroup_count_limit_y.split2resource_usageqgpu.variable_infotoBeRemovedbb36-vectorize-local-memoryDon't try to form non-2^n-length vectorsbb36-vectorize-no-cmpEnable early scalarizationNumber of constant foldsenable-vload-optextract.tNumber of call instructions CSE'dNumber of equalities propagatedNumber of loop exit tests replacedNumber of jumps threadedreroll-thresholdunroll-countNot unrolling loop with more than 2 Texture Read/Write callsllvm.loopunroll.countReassociate expressionsNumber of intra loop branches eliminateddisable-ifcvt-simple-falseNumber of spills inserted@show-mc-encodingNumber of copies coalesced after commutingFunction Live Ins: vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/MachineFunctionAnalysis.cpp= 65536. (unknown type in type tableInvalid INVOKE recordenable-bc-uselist-preserveNot inlining. Cost of inlining A file containing list of basic blocks to not extractword && "ConstantInt expected"nextSlotNum[resType] < getTargetFeatures().getValue(QV_MAX_TEXTURE_SLOTS)resIDMap.find(&arg) == resIDMap.end()vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/HLCUtils/UnifiedExpansionPass.cppqgpu.subgroupsize_log2.shflenable-qgpu-iselkrait2Support sGPRsSelect the a5x processorHR0_dHR22_cHR25_dHR27_cHR32_bHUR4_bIR53IR70IR76IR85IW0IW1IW2R3_cR23_aR27_cR31_aR35_cR38_aSAM0SR0_cSR1_aSR7_cltVLoadMI && VLoadMI->getDesc().getNumDefs() == (unsigned)(VECTOR_LIMIT)endPos || mergedShaderPosisOREGInstr(MI) && "Invalid instruction"xyzwfalse && "Unhandled case"i < NUM_SCALARS && "QInstMapEntry query out of bound"lastInst != NULL && "no instruction in this map entry?"qgpu.constant_store.useddoubleCfalse && "Unimplemented type for lowering to DCB"false && "Unable to lower extract element to DCB"JPNode && "No Join Point?"I != NULL && "Instruction cannot be NULL"nonbindlessenable new vectorizeenable-auto-vec-hintNo destination conversion folding_CL_profiling_buffer_reg(isFsample || isIsample || isGather4) && "fsample, isample, & gather_4x are _currently_ the only support intrinsics for this function"{Errata#292}.??.unpacked.ackrt(low)0.5log2(10)rndaz.fcmps.umad.u16.lomad.s24rcphsamimgqgpu.dummy.gsDstReg != 0 && "Invalid destination register for initial texture"use the same register.Full precision GPRQGPU Scalar Evolutiondir-schedpost-sched-sync-coloringfalse && "Invalid shufflevector mask operand"sgpr-tholdAtomic.getOperand(6).isImm() && "TODO: handle register case for src2_uav_slot"false && "unhandled move opcode"!(StackUsed && FakeRegRenameCtx.RealStackPtrReg == QGPU::NoRegister) && "No available registers to map SP register"false && "must be imm LDCK" use has no definition.enable-qgpu-lra-outmov-optvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUFrameLowering.cppllvm.usub.with.overflow.i32_ashr16loadInst && "Load instruction is NULL"idx <= UseMI->getNumOperands() - 1 && "Unexpected PHI operand"0 && "resolution has deadlocked"LI != NULL && "Invalid vector?"isSpillable(LI_Cur) && "This live interval cannot be splitted"uppf-bad-tolfacuppf-cov-num-blocks!Inserted && "mbb is active"false && "Expected GV for const".pn option n=0-3 only allowed for conv instruction.the ldthr instruction should use g with source 0. Usage g[r4.x+32] atomic.inc|.dec with .rg option should have .t = u32 only LDST: Source offset Out of Range with prefetch instruction. Allowed Range is 13bits, |0 - 8191|STIB|LDIB: offset modified cannot be used for A5x and below archtype with STIB or LDIB ALU3 - AND MERGE: b32 is for 32 bit sources src[2]Texture: .mode option should be given with src2 always.PATCH27NONELINE_LENGTHTEX2DMSADDFMUL2INSTRCOVF16U16INSTRCOVF16F32INSTRSYNCSLOADGS8INSTRSTGENF32INSTRSTGAS8INSTRSTTHRS32INSTRSTTHRAS8INSTRSTXU8INSTRG2LS8INSTRLOADLWF16INSTRLOADLWS8INSTRLOADGBT2DF32INSTRLOADGBAU2DF32INSTRBARLINSTRFENCELWINSTRUVGS_OPALIAS_CTRLSTPU8INSTRATOMXCHGGENSOCU32INSTRATOMANDGENSOCU32INSTRATOMBINCGNU321DINSTRATOMBADDGU323DINSTRATOMBASUBGU32INSTRATOMBASUBGU322DINSTRATOMBSUBGS323D1LINSTRATOMBMAXGU322D1LINSTRATOMBAMAXGS32INSTRATOMBAMAXGS322DINSTRATOMBAMAXGS323DINSTRATOMBAORGU323D1LINSTRATOMBCMPXGU641D1LINSTRATOMBCMPXGU32INSTRATOMBXCHGGU64INSTRATOMBXCHGGF322D1LINSTRATOMBINCLNGU323D1LINSTRATOMBINCRGGS32INSTRATOMBINCRGGU32INSTRATOMBINCRGGU322DINSTRATOMBDECGS322D1LINSTRATOMBADECGU321D1LINSTRATOMBADECGU323DINSTRATOMBDECLNGU323DINSTRORBINSTRASHRBINSTRSAMP3INSTRCOVS32F16INSTRBRCSTACTIVEW2INSTRSTIBAU322DINSTRINETOKENMOVSS16INSTRLDIBUNTYPEDU161DTINSTRLDIBTYPEDS162DINSTRLDIBTYPEDU162DRCKINSTRSTIBUNTYPEDF322DINSTRSTIBUNTYPEDU161DINSTRLDIBBLKGF163DINSTRLDIBBLKCU323DINSTRLDIBBLKCU162DINSTRLDIBAS163DRCKINSTRSTIBBLKS162DINSTRGATF16U16INSTRGATF32S32INSTRSCTS16U32INSTRRESIDENCECHKFB_ENABLEDOTDECLARE_SHADER_TYPEDCL_CL_KERNEL_TOKENDCL_SYMBOL_TOKENUNIFORMTOKENDECLARE_CL_LocalMemoryUsedBytesDECLARE_CL_ResumeCounterLimitADDRESS_REGGETSPIDINSTRLOADLINSTRCEILINSTRASHRINSTRCBITSINSTRDSPP_INSTRSDCLICBVAL11 Out of Range offset in Relatively addressed Destination Operand. Offset value can be in [0, 255]shaderHandlesADRENO_UAV_DESCRIPTOR_FORMATADRENO_CONST_COLOR_OUTPUTtesInputsconstantColorOutputMAX_INPUT_BLOCKSMAX_TEXTURE_IMAGE_UNITSMAX_VIEWPORTSMaxFragmentImageUniformsMaxFragmentAtomicCountersisBindlessCBuffer============ Reserved Location Infomation ============ GL_BOOLGL_UNSIGNED_SHORTGL_BOOL_VEC2GL_SAMPLER_EXTERNAL_YUYV_AMDGL_SAMPLER_2D_ARRAYGL_UNSIGNED_INT_SAMPLER_2D_MS_ARRAYGL_UINT_IMAGE_CUBEQGL_TEXTURE_CUBEQGL_INT_TEXTURE_2D_MSQGL_SAMPLERRGBA16F restrict, sampler4BlockMatch, blendingMask = 0x%xModuleCache - RetrieveparentUniform && "Assert Index:[15] parentUniform expected" offset mismatch with other stage.pos2 != llvm::StringRef::npos && "Assert Index:[27] Invalid TF name"RWBuffer:Derivatives Rotation MatrixTessellation ControlTessellation EvalifCvtThresholdrelaxExtensionPPCheckenableDefaultUBOBracenableSingleRegisterPoolMultiBBllvm.qgpu.absneg.f32llvm.qgpu.imad.i32llvm.qgpu.global.scalar.alloc.reg.p0i32.p0v3i32llvm.qgpu.fcombine2.f16llvm.qgpu.fcombine2.f32llvm.qgpu.selge.f32(tcsHSGV != NULL) && (tesDSGV != NULL)-setup.bcqglnext_has_spec_constqglnext_default_ubo_size__qcom_BARY_Coordinate_center_non_perspvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/codegen/CodeGenHelper.cppmGSIOMD != NULL && "Unable to add GS IO metadata to module"accessing a write-only variablemHelperInvocationGV && "no __qcom_is_HelperInvocation GV in current module or could not create new GV"matrixType->isArrayTy()baseType->isArrayTy() && "dynamic indexing a non-array type"!isSrcInt && !isSrcUint && "Operands must be a scalar or vector whose component type is floating-point"matrixMe->getColSize() == vecMe->getSize() && "matrix and vector have different size for multiply!"(sampleIDGV != NULL) && (pAddrSpaceMD != NULL)(namedConstantGV != NULL) && "Can't find named constant global variable!"llvm.qgpu.image.load.v4%s.p0i32.v%d%snamedConstantGV && "namedConstantGV is Null"getObjRayOrigetRayTMaxcompare && compareME && "Compare can't be null for AtomicCmpXchgInst"gl_FragCoordVH_ && "OpRayQueryGetIntersectionInstanceIdKHR" " is not supported"VH_ && "OpRayQueryGetIntersectionGeometryIndexKHR" " is not supported"bb->getTerminator() && "Terminator inst is expected"$setupBaryP_j_slope_dymAddrSpaceToSymbolMD != NULL && "Unable to add named address space metadata to module"gl_outunrollSize <= maxImage && "Image Array Size is bigger than Max Image units"false && "Unknown named pointer type or missing metadata"tesBuiltInInputAddrmIsTCS && "Only TCS stores outputs to global memory!"false && "Invalid Tessellation I/O stores"false && "incorret data type for LDG.A instruction"gl_VertexIDgl_MaxFragmentUniformVectorsgl_MaxImageUnitsgl_MaxTessEvaluationCounterBufferstexture1Ditexture1Dtexture3Diimage1DArray!isCompared && "subpass is expected to have no depth"false && "setGlobalTessInfo called on invalid object"((theOp == EOpIndexDirect) || (theOp == EOpIndexIndirect)) && "unexpected opcode"(isSrcInBlock || isDstInBlock) && "neither src nor dst is in UBO/SSBO!"0 && "Wrong Operator"false && "unsupported type in constant construction"node->getOp() == EOpConstructStructidxCnstNodeopnd && "Top operand is Null"absstepatomicWrong symbol table levelgl_LastFragStencilARM not accessible when early_fragment_tests specifiedInvalid Index on TCS Per-Vertex Output^=can't modify gl_MaxTessControlInputComponentscan't modify gl_ShadingRateFlag2HorizontalPixelsEXTgl_PrimitiveShadingRateEXT cannot contain gl_ShadingRateFlag2HorizontalPixelsEXT and gl_ShadingRateFlag4HorizontalPixelsEXT simultaneously, only one horizontal flag is allowedillegal use of type 'void' or no matching overloaded function foundcan not redefine gl_LastFragStencilARM as a non-int typecan not redefine gl_LastFragDepthARM as a non-float typeinterpolateAtSampleunsupported format on read/write imageinvalid atomic op on WO or RO imagegl_in[] can only be defined in GS/TCS/TESgl_FragDataGL_KHR_blend_equation_advancedhyperbolic cosineFractionConstruct uintConstruct mat2x2ModMinTexture3dTexture2DShadowProjLodconstruct samplergl_DepthRangecoordmust be declared flatordering already specified and it is not ccwSubpass is for Vulkan api only is not a valid layout specifier. Should be one of: YUYV, UYVY, YV12, NV21, NV12 or NV12Tiled.mat4: duplicate symbol.spurious tokens trailing an #undef300$specConst_%dloadInst && "Load instruction is expected"!(objectDataType->isArray() || objectDataType->isStruct()) && "Invalid type array/struct type."condMe->getSize() == 1 && "Unexpected condition size"gl_GlobalLinearIdOpConstantSamplerOpImageReadOpImageWriteOpPtrCastToGenericOpSGreaterThanOpFOrdGreaterThanEqualOpDPdyCoarseOpAtomicLoadOpGroupUMinOpGetMaxPipePacketsOpAtomicFlagTestAndSetOpConstantPipeStorageOpRayQueryGenerateIntersectionKHROpRayQueryGetIntersectionObjectRayDirectionKHROpImageBoxFilterQCOMLinker - Module ConstructdummyRayId$qgpu.stable.const.hitgroup$qgpu.stable.fb.missisOpaqueupdateCurrHitStoreIntoPLCDcalledFunc != NULLgeneric.stack.loadmailbox.buffer.ptrrayid != NULL && thrid != NULLfunc && "setDispatchLocation() should have been inserted in init()"getCommittedHitGroupAddrrd.lbasecommittedHitGroupfunc && "For AnyHit shaders, scheduleCont() should have been built"framesizeori.y (Centroid) (FracEven) (QGLNEXT_DEFAULT_UBO_INDEX)metadataSize: hwShaderPointer[textureUsedInTexelFetchMask: sourceSlot: ]: outputsRTArrayIndex: needsDomainU: [A4X_PS_INPUTS] (Ver gsOutputs: [SHADER_STATS] (Ver sourceTextureSlotIndexBase: inputTargetInfo: declaredSize: (NULL) arrayDimensions[samplerSlot: infos: constColorOutputEntries: imageAttachmentDataEntries[stackSize: [VERSIONED_STRUCTURE_INFO][ADRENO_SHADER_UAV_USAGE].nonBufferUavWriteMask.usesRelativeAddressing.targetVecReg.outputsViewportArrayIndex.rtArrayIndexVPCIndex.enablePostDepthCoverage.bindlessIndexSampler.loads.maxRCLevel.is8BitIntWA[ADRENO_BINDLESS_EMULATION_MAPPING_RANGE].numEmulatedGroups[ADRENO_STEREO_RENDERING_INFO][ADRENO_BINDLESS_USAGE_INFO].readBindlessNonBufferUAV.writeBindlessNonBufferUAV[ADRENO_VSDS_PSO_PRIMITIVE_SIZE].atomicCounterInfo.isBoundedToTF.locationOffset.layout[ADRENO_IMAGE_ATTACHMENT_INFO].elementType.vertexAttrViewStride.hwInfoFS >llvm.arm.neon.vpminullvm.arm.neon.vqaddullvm.arm.neon.vqshiftsllvm.arm.neon.vrecpellvm.arm.neon.vshiftlsllvm.arm.neon.vshiftnllvm.fmallvm.hexagon.A2.addh.h16.sat.hhllvm.hexagon.A2.andpllvm.hexagon.A2.subh.h16.sat.lhllvm.hexagon.A2.tfrllvm.hexagon.A2.vmaxhllvm.hexagon.A2.vsububsllvm.hexagon.A2.vsubwsllvm.hexagon.A4.round.rrllvm.hexagon.C2.bitssetllvm.hexagon.C4.cmplteillvm.hexagon.F2.conv.sf2dfllvm.hexagon.M2.mmpyh.s1llvm.hexagon.M2.mpy.acc.hh.s0llvm.hexagon.M2.mpy.acc.lh.s1llvm.hexagon.M2.mpy.acc.sat.hh.s1llvm.hexagon.M2.mpy.sat.hl.s1llvm.hexagon.M2.mpyd.acc.hl.s0llvm.hexagon.M2.mpyd.nac.ll.s1llvm.hexagon.M2.mpyud.acc.ll.s0llvm.hexagon.M4.and.xorllvm.hexagon.M4.cmpyr.whllvm.hexagon.M4.or.xorllvm.hexagon.M5.vdmacbsullvm.hexagon.M5.vmacbsullvm.hexagon.S2.asl.r.r.andllvm.hexagon.S2.asr.i.r.rndllvm.hexagon.S2.ct1llvm.hexagon.S2.lsr.i.r.xaccllvm.hexagon.S2.lsr.r.p.nacllvm.hexagon.S2.lsr.r.p.xorllvm.hexagon.S2.vzxtbhllvm.objectsizellvm.opencl.get.global.sizellvm.opencl.read.image3llvm.ppc.altivec.dssllvm.ppc.altivec.vaddswsllvm.ppc.altivec.vcfsxllvm.ppc.altivec.vmsumshsllvm.ppc.altivec.vmsumuhsllvm.ppc.altivec.vmulesbllvm.ppc.altivec.vpkshssllvm.ppc.altivec.vsrllvm.ptr.annotationllvm.ptx.read.ctaid.yllvm.qcom.s322s16llvm.qgpu.absnegllvm.qgpu.dp4llvm.qgpu.dsyllvm.qgpu.fcreate.map54llvm.qgpu.fcreate.map59llvm.qgpu.fractllvm.qgpu.get.cyclellvm.qgpu.get.rt.miss.stbl.stridellvm.qgpu.get.sym.descriptor.infollvm.qgpu.icmpxllvm.qgpu.icombine35llvm.qgpu.icombine57llvm.qgpu.icreate.map57llvm.qgpu.icreate.map59llvm.qgpu.nop.with.syncllvm.qgpu.rayidllvm.qgpu.set.mesh.attrllvm.qgpu.smad24llvm.qgpu.uminllvm.qgpu.umull16llvm.smul.with.overflowllvm.spu.si.andllvm.spu.si.mpyuillvm.stacksavellvm.trapllvm.x86.3dnowa.pf2iwllvm.x86.aesni.aesimcllvm.x86.avx2.pavg.bllvm.x86.avx.blendv.pd.256llvm.x86.avx.blendv.ps.256llvm.x86.avx.vpermilvar.ps.256llvm.x86.fma4.vfmsub.sdllvm.x86.mmx.pcmpeq.dllvm.x86.mmx.pmulhu.wllvm.x86.mmx.psll.qllvm.x86.mmx.psub.wllvm.x86.sse2.cvtsi642sdllvm.x86.sse2.max.pdllvm.x86.sse41.round.psllvm.x86.sse42.pcmpistrm128llvm.x86.sse.sqrt.ssllvm.x86.xop.vpcomgewllvm.x86.xop.vpmadcsswdllvm.xcore.bitrevllvm.xcore.clrellvm.xcore.getidllvm.xcore.intPass Manager overheadglue# formal arguments must match # of arguments for function type! only applies to the function!FPToSI source and dest vector length mismatchInvalid operand types for ICmp instructionGlobal variable initializer type does not match global variable type! .cfi_endproc__TEXT .seh_endchained .fnstart' is not a divisor of padding size 'pcrel udata4DW_CFA_def_cfa_offsetDW_CFA_restore_state__apple_names.debug_info.drectve .linkonce same_contents ,comdatliteral_pointersS_SYMBOL_STUBSS_16BYTE_LITERALSno_dead_stripUse +feature to enable a feature, or -feature to disable it. For example, llc -mcpu=mycpu -mattr=+feature1,-feature2 invalid pointer ABI alignment, must be a positive 8-bit multiplei < getNumRegClasses() && "Register Class ID out of range"atan2lloglog2nearbyintroundl Alias Analysis Mod/Ref Evaluator Summary: no mod/ref! no mod/ref responses View CFG of function (with no function bodies)Writing ''...Error: Number of FDiv instsInterval Predecessors: Undefined behavior: Write to read-only memoryUndefined behavior: Write to text sectionUndefined behavior: Call argument count mismatches callee argument countWeak-Crossing SIV independenceWeak-Zero SIV successesWeak-Zero SIV independencevendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Analysis/MemoryDependenceAnalysis.cppVerify region info (time consuming)Nodebackedge-taken count is scevgepsmaxisa(V) && "Unexpected instruction"uniformity CS<basiccglcssaCOMPLETELY UNROLLING loop with trip count notnullvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/SimplifyCFG.cppisa(use)OpenGLKillWorkaroundfalse && "not supported yet"offset && "Invalid offset!"bb-vectorize-no-intsDon't try to vectorize select instructionsDon't try to vectorize loads and storesvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cppdisable-cgp-branch-optsenable-load-preNumber of exit values replacedexitcondlftr.limitMax block size to duplicate for jump threadinglicmNumber of call insts hoisted or sunk.promotedDisabled Nimbus3.0 Loop Unroll on OpenCLqgpu.tex.sam.in.loopScalar Replacement of Aggregates (DT)vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Scalar/ScalarReplAggregates.cppfalse && "GEP iterator invalid"scalarvector-reassociateNumber of dead blocks removedNumber of triangle if-conversions performedNumber of folded loadsNumber of instructions deleted by DCEShow encoding in .s outputblock-placement2machinedomtree# ...Unpack machine instruction bundlesBad instruction parent pointer given. Explicit definition marked as implicit is not live in Disable Machine Global Code Hoisting/Unificationdisable-lsrAggressive extension optimizationqgpu-regalloc-avoid-short-syncsenable-aa-sched-miShrink wrap the specified functionIterationspers_fn_geplpad.val non-existing BB#********** REGISTER MAP ********** loBit < numBits && "loBit out of range"disable-2addr-hackConstantFPBUILD_VECTORTargetJumpTableftrunccttz_zero_undefsettrue2 [TF=DAG Combining after legalize typesNumber of blocks selected entirely by fast isel}}__divdf3__fixunssfdi__fixunsdfqi__lesf2__sync_fetch_and_and_1__sync_fetch_and_xor_8Invalid CE_GEP recordInvalid CAST recordInvalid INSERTELT recordfalse && "Constant promotion limit not set"false && "blendingOp not handled"false && "undefinded image dimension."enable-pointer-to-imagellclib: invalid optimization level. got Supports Generic Address SpaceSupports Shared Virtual MemorySelect the a7x processorHR9_aHR16_aHR16_dHR25_aHR33_bIR30IR61R1_dR5_cR17_dR18_aR23_bR33_aR38_dSAM27UAV5UAV37UR0_af32unexpected token in operandinvalid instructionQGPU::moveQGPU::loadpLastNopInserted != NULLNumber of instruction-level predication performedOpcode != QGPU::GETLAST && "can't remove getlast"0 && "no such type for cvt"llvm.qgpu.interpolate.fEnable preamble transformationDebug messages from preamble transformation and dump CFG in dot formatisInlined && "Preamble function not inlined!"preamble.bbuniform.loadqgpu_cbusagedatasharedConstants_cEnable automatic vector hint settingRegFileMode == M && "Inconsistency in register file mode"false && "Unexpected instruction feeding into get_reg intrinsic"_CL_divided_num_groups__qcom_rs_local_rand_seedfalse && "These intrinsics are not lowered yet"!relativeAddress && "Relative address using A0 is not possible for local_linear_id"false && "Unsupported opcode in pattern\n"false && "We don't currently expect textureID stored in GPR."isTypeLegal(II.getType(), DstVT)!IsFloatCoord && "LST_SAMPLER_MULTI is only for integer coordinate"u24.l.rck1/picmps.sshrg.b16mova1ldxatomic.inc.rgatomic.maxldib.blk.lmldc.kdcclntex.OpCode != OP_IMG && "Currently tex.Src2En cannot be handled for TPIP IMG instructions"false && "Cannot apply prediction in the BB with alias"Register ID '&' must with a variable. (double &)ramModeNode->getNumOperands() == 2numDefs == 0false && "couldn't parse MD"RegClassUndefinedError: register Too large RPT. SamID <= 65536 && TexID <= 65536 && "Bindless offset S/T too large"Non-predicateWindowMinRegsdisable-unifiedpost sched combininggreenandgenable-dche-allow-dead-in-the-middleDefInst && "Cannot find IFAKEMOV"SwapTo == -1 && "VectorBegin/VectorEnd and SwapTo cannot be set simultaneously"!isSGPR || (isSGPR && isUGPR) && "sgpr-only case is not supported yet"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUCallGraphSCCPass.cppvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPULocalRegAlloc.cppTargetRegisterInfo::isVirtualRegister(VReg) && "Not a virtual registeR"_tmp_hineg_lolo, Priority: Unhandled->empty() && "unhandled set is not empty"LI_Child && "Result of LI split cannot be NULL"false && "No spillable register?"NextUseSlot.isInstSlot() && "SlotIdx must be an instruction slot."LI->isParent() && LI->getChild() == NULL && "This live interval cannot be splitted"Invalid hint on input instructionsFrameIdx != InvalidFrameIndex && "Invalid frame index"qgpu-globalregallocuppf-sbb-durT.UseMI->getOperand(T.OperandIndex).getReg() == getGPR() && "alien target"DefMI && "No Def?"QGPU LI Optmizer Passfatal error - scanner input buffer overflow LDST: Out of Range Offset with stg.a instruction. Allowed Range is 13bits, |0 - 8191|the stx.a instruction should use g with dst. Usage g[r4.x+32] the destinaltion should use l with dest operand. Usage: l[r0.x]STIB: for src baseid 5 is only for src mode 5/6 for a6x and aboveLDIB: for src baseid 5 is only for src mode 5/6 for a6x and aboveLDIB: for legacy src2 should be IMM for a6x and aboveLoadStore: for GetGPRBase instruction dst should be uGPR ALU2 CAT32: Only allowed in a6x and above. SHIFT MASK: Only 32 bit Operand ALLOWEDALU3 - AND MERGE: Only 32 bit Operand ALLOWEDEFU: Destination Operand cannot be relatively Addressed TEXTURE: src1 can be GPR/sGPR when Src2Enabled.WTTexture: img pcmn/sad/ssd s34 should be enabled The GPR number should be between 0 and 47Texture: quad.shuffle instr src1 type should be a GPR the half float value should start with h. USAGE: h(float value)UINT16POINTTRIANGLESTRIPBARYNONPERSPCENTROIDTESSELLATION_PATCH_CONSTANT_LOCATIONTESSELLATION_TESS_FACTOR_LOCATION_64BITTEX1DMINFINSTRSIGNFINSTRFLOORFINSTRLOADTHRCCHEAU16INSTRLOADXU16INSTRLOADXAS16INSTRLOADLS8INSTRSTGENF16INSTRL2GF16INSTRL2GF32INSTRLOADGBAU3DS32INSTRLOADGBAT4DF32INSTRATOMADDGGPUS32INSTRATOMORGENGPUS32INSTRATOMCMPXCHGGGPUU32INSTRATOMORGSOCU32INSTRATOMBXORGNU32INSTRATOMBAADDGS323DINSTRATOMBSUBGU322DINSTRATOMBMINGS321DINSTRATOMBAMAXGU322DINSTRATOMBAANDGU322D1LINSTRATOMBAANDGS322DINSTRATOMBXCHGGU323D1LINSTRATOMBINCGU321D1LINSTRATOMBINCLNGS321D1LINSTRATOMBINCLNGS322D1LINSTRATOMBINCLNGU322DINSTRATOMBINCRGGS322DINSTRATOMBADECLNGU323DINSTRATOMBADECRGGS32INSTRBARYFINSTRSELB16INSTRD3TOKENCOVS32U16INSTRCOVS32S16INSTRBRCSTACTIVEW8INSTRATOMXCHGGU32INSTRATOMMINLU32INSTRMAD32F16INSTRLDIBAU321DTRCKINSTRMOVPCINSTRSWZU16S32INSTRMOVSF16S32INSTRLDIBUNTYPEDF322DINSTRLDIBTYPEDU321DRCKINSTRLDIBUNTYPEDS321DTRCKINSTRLDIBTYPEDF323DRCKINSTRLDIBTYPEDU161DINSTRSTIBTYPEDU163DINSTRLDIBBLKGF162DINSTRLDIBBLKCS323DINSTRSTIBAS162DINSTRSTIBBLKF322DINSTRSCTS16INSTRSCTU8S32INSTRSCTS32F32INSTRSRC2MODEGETSPIDU16INSTRPCMN_ENABLESTSCINSTRHASHLSQBRACEDCL_CL_LOCAL_SIZE_TOKENDECLARE_UAV_DESC_STORE_MAPDECLARE_HS_PATCHCONSTTESSFACTORSIZEDCL_EXTRA_LOCAL_MEM_TOKENFULL_GEN_REG_NAMEDUMMY_REG_NAMELOADIBINSTRMAD16INSTRMOV_SOURCE_OPERAND1IMM_VALUESOURCE_MODIFER1ALU2: Both sources should be of same precision.readsBITMASKADRENO_PATCHED_STATIC_GATHER_TEXTUREADRENO_DYNAMIC_CBCACHE_ENTRYGL_UBO_LOCATIONGL_SYMBOLLISTADRENO_SHADER_COLLECTION_SHADER_INFOastcPatchingasX-e-p:32:32-f16:16:16-f32:32:32-i32:32:32-i8:8:8-i16:16:16-n8:16:32-v96:32:32MAX_ATOMIC_COUNTER_BINDINGSMAX_UNIFORM_BLOCK_SIZEMaxVaryingVectorsMaxAtomicCounterBuffersMaxGeometryImageUniformsMaxSamplesisBindlessRWBufferGL_SAMPLER_601Y2R_QCOMGL_UNSIGNED_INT_SAMPLER_3DQGL_TEXTURE_709Y2R_QCOMQGL_INT_TEXTURE_CUBEQGL_UNSIGNED_INT_TEXTURE_2D_ARRAYLOCATION_OUTLow notUsed, sizeInBytes = %dNULL != ptr && "Assert Index:[69]"false && "Assert Index:[53] invalid hw slot type"$TessFactorGlobalBasePtr32$PatchGlobalBasePtr64$IsNextShaderStageTessControl(packSize <= QGLC_NUM_CHANNELS) && "Assert Index:[32] packSize must be less than or equal to 4"Any HitCallableenableUserUBOBracllvm.qgpu.imax.i16llvm.qgpu.interpolate.f16llvm.qgpu.fceil.f16llvm.qgpu.stlw.v3i32llvm.qgpu.atomic.imin.oob.i32llvm.qgpu.atomic.xor.oob.i32llvm.atomic.swap.i32vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/codegen/Linker.cppINTERNAL ERROR: Input && "Input Cant be Null"GV != __nullnumCol <= QGLC_NUM_CHANNELS && numRow <= QGLC_NUM_CHANNELSindex < QGLC_NUM_CHANNELSptr && "indexing a NULL pointer"false && "Unexpected LLVM type used for array access"srcTy->getArrayNumElements() == dstTy->getArrayNumElements()o.ray.dirldib_i32get_intersection_type__RTStorePLCDOffsetCallIndirect(resultTy->isIntOrIntVectorTy() || resultTy->isFPOrFPVectorTy()) && "Unexpected result type for load from Vulkan pointer"indexVal && "unknown usage pattern"_BindlessCBqgpu.global.scratch.mem.usedError: Tessellation evaluation shader didn't specifiy primitive type(cst.model - QGLC_COLORSPACE_MODEL_YUV_BT709) < numS1gl_FramebufferClockQCOMgl_MaxComputeAtomicCounterBuffersgl_MaxPatchVerticesgl_ShadingRateFlag2HorizontalPixelsEXTitexture2Dimage2Dfalse && "setClipCullInfo called on invalid object"[*]!isLeafNode && "a[1]/a[i] cannot be leaf node"!isLeafNode && "array indexing node a[1] cannot be a leaf node!"modfinversemsb!stack.empty() || !inUseListcan't modify gl_Layercan't modify gl_MaxDualSourceDrawBuffersEXTcan't modify gl_MaxGeometryOutputVerticescan't modify gl_ShadingRateFlag4VerticalPixelsEXTcan't write gl_FragColor or gl_SecondaryFragColorEXT while gl_FragData or gl_SecondaryFragDataEXThas been writtenarray size must be a positive integercannot declare arrays of arraysgl_SampleID cannot be used with GL_QCOM_shader_framebuffer_fetch_rate extensionfield selection out of range '%d'struct that has array is not allowed for per-patch input/outputstruct member may not contain qualifiers other than precision qualifierinterpolateAtSample cannot be used with GL_QCOM_shader_framebuffer_fetch_rate extensioncan't redefine/overload built-in functions!gl_PerVertex redeclared multiple timescannot declare fixed and variable work group sizes at the same timevar && "can not find builtin varirable gl_SecondaryFragDataEXT"GL_OES_shader_multisample_interpolationGL_QCOM_shader_framebuffer_fetch_rateCompare Greater Than >arc hyperbolic sineConstruct bvec4Construct ivec4ReflectWrite Outputtested first interpolateAtOffsetcomparereadPixelusamplerBufferdiscard#version 300 must be followed by es identifierInvalid DirectiveStruct/IO of this type is not supported. !matrixPtrInfo->isRowMajor() && "row major cases are not supposed to handle here"OpDecorationGroupOpImageDrefGatherOpUDivOpSDivOpIsFiniteOpBitFieldInsertOpSwitchOpLifetimeStopOpGroupFMaxOpCommitWritePipeOpCreateUserEventOpNamedBarrierInitializeOpGroupNonUniformShuffleXorInvalid SPIR-V module: ID boundvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/raytracing/DxrFallbackCompiler.cppm_ElementSize * i && "memcpy dest pointer is NULL!"pConstantExpressionsPtr + pConstantExpressionsDesc->m_ElementSize * i && "memcpy dest pointer is NULL!" Holds miscellaneous information about the shader compiled Version 1.0: Added shaderVersion Added castUniformsToFloat: True for GLES 2.0 shaders where integer uniforms are unsupported. This is a text log of information recorded during compilation. This can be helpful to the end-user in debugging compilation failures, or may be helpful for driver debugging. Version 1.0: Added logString Version 1.1: Added metadataHandle A list of constant buffer cache entries used for working around MSFT bug on CB size mismatch. Version 1.0: Added numDynamicCBCacheEntries Added dynamicCBCacheEntries Used to program the vertex fetch (VS input) and interpolator fetch (FS input) registers. Version 1.0: Added vertexStride: How many bytes between vertices in the vertex attribute buffer. Added primStride: How many bytes between primitives in the primitive attribute buffer. reinterpret_cast(pData) && "memcpy dest pointer is NULL!"> = Print debug info in human readable form is function llvm.convertusllvm.eh.typeid.forllvm.hexagon.A2.addh.h16.hlllvm.hexagon.A2.vmaxuhllvm.hexagon.A4.cround.rillvm.hexagon.A4.vrminwllvm.hexagon.C2.any8llvm.hexagon.C2.cmpeqpllvm.hexagon.C2.cmpgeillvm.hexagon.C2.cmpgeuillvm.hexagon.C2.cmpgtpllvm.hexagon.F2.conv.df2sfllvm.hexagon.F2.conv.sf2w.chopllvm.hexagon.F2.sffixupnllvm.hexagon.M2.dpmpyss.nac.s0llvm.hexagon.M2.mmachs.s0llvm.hexagon.M2.mpy.acc.sat.hl.s0llvm.hexagon.M2.mpy.hh.s0llvm.hexagon.M2.mpy.rnd.hh.s1llvm.hexagon.M2.mpyd.nac.hl.s0llvm.hexagon.M2.mpyu.acc.hl.s0llvm.hexagon.M2.mpyu.acc.hl.s1llvm.hexagon.M2.mpyu.hh.s1llvm.hexagon.M2.vrcmpys.acc.s1llvm.hexagon.M2.vrmpy.s0llvm.hexagon.M4.cmpyi.whcllvm.hexagon.M4.vrmpyeh.s0llvm.hexagon.S2.asl.i.vwllvm.hexagon.S2.asr.i.r.accllvm.hexagon.S2.cl1pllvm.hexagon.S2.lsr.r.r.accllvm.hexagon.S2.vrndpackwhsllvm.hexagon.S2.vsplatrhllvm.hexagon.S2.vsplicerbllvm.hexagon.S2.vtrunewhllvm.hexagon.S4.or.andillvm.hexagon.S4.subaddillvm.opencl.get.num.groupsllvm.opencl.read.image1aullvm.ppc.altivec.dsttllvm.ppc.altivec.vctsxsllvm.ppc.altivec.vrfizllvm.ptx.read.nctaid.zllvm.ptx.read.ntid.xllvm.qcom.atomic.incllvm.qcom.f162s16llvm.qgpu.Stxllvm.qgpu.dcclnllvm.qgpu.dumpallgprsllvm.qgpu.fcombine55llvm.qgpu.fcreate.map42llvm.qgpu.fsamplellvm.qgpu.get.vpc.for.ptrllvm.qgpu.icombine14llvm.qgpu.icombine56llvm.qgpu.icombine62llvm.qgpu.icreate.map14llvm.qgpu.icreate.map49llvm.qgpu.isub.satllvm.qgpu.msadllvm.spu.si.fceqllvm.spu.si.shlqbyllvm.x86.avx2.maskstore.d.256llvm.x86.avx2.paddus.wllvm.x86.avx2.pbroadcastd.128llvm.x86.avx2.psubs.wllvm.x86.avx.vperm2f128.pd.256llvm.x86.fma4.vfmaddsub.pd.256llvm.x86.mmx.pcmpeq.bllvm.x86.mmx.psll.wllvm.x86.sse2.psrl.wllvm.x86.sse41.blendvpdllvm.x86.sse41.phminposuwllvm.x86.xop.vpcomneuqllvm.x86.xop.vphsubwdllvm.x86.xop.vppermllvm.xcore.initdpllvm.xcore.initpcfaddvector select condition element type must be i1select condition must be i1 or Instruction operands must be first-class values!fence instructions may only have acquire, release, acq_rel, or seq_cst ordering.DestTy too big for TruncSExt only produces an integerFPToSI result must be integer or integer vectorUIToFP source must be integer or integer vector is not a floating-point type.Invalid extractelement operands!Global is external, but doesn't have external or dllimport or weak linkage!@@@ .byte .uleb128 .local .balignw .cfi_adjust_cfa_offset encoding: [ bytesCIE Return Address ColumnFDE LengthFDE initial locationDTPREL_LO__cstring__debug_locS_LITERAL_POINTERSlive_supportinvalid pointer preferred alignment, must be a positive 8-bit multipletargetdata!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."tanh AliasSet[block-freq<>Induction Variable UsersNumber of FAdd instsNumber of FAdd insts ScalarNumber of SDiv insts ScalarNumber of Or instsNumber of AtomicCmpXchg insts ScalarNumber of expansionsInterval Contents: Undefined behavior: va_start called in a non-varargs functionSeparable subscript pairsstyle = solid; --> Number of loops with predictable loop countspick-all-pershaderqgpu.symbols.ro.buffersplitCanonicalize natural loops.loopexit.outerCompareBB && "CompareBB is NULL!"false && "Unhandled Case"1.0BundleMember && "no ScheduleData for bundle member (maybe not in same basic block)"bb36-vectorize-no-floatsbb36-vectorize-no-fmabb36-vectorize-no-selectbb36-vectorize-aligned-onlyenable-early-scalarizationfor.cond.memset_vNumber of [s|z]ext instructions combined with loadsNumber of trivial dead stores removedvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Scalar/LoopInterchange.cppunroll-no-outerWill not try to unroll because threshold = 0.phiqgpu_gluecodepost-callAnalyze Machine Code For Garbage CollectionNumber of single use loads folded after DCEdead Constant Pool: machinemoduleinfoMachineModuleGenForce bottom-up list schedulingMachine instruction scheduler to use machine code errors.MBB has more than one landing pad successorMBB exits via conditional branch/fall-through but doesn't contain any instructions!MBB exits via conditional branch/branch but the CFG successors don't match the actual successors!Explicit definition marked as use is not a Block ends before last instruction indexprint-isel-input!VRM->hasPhys(VirtReg->reg) && "Register already assigned"Optimize for speedvectorize mayvec.qgpu-enable-mischedsimple-register-coalescinggc_frame.mapslotindexesinlineDestVNIMachine Branch Probability AnalysisNumber of dead insts removed on failureFast suboptimal list schedulingmulhusraumulofp16_to_fp32cvt_suvastartcttzDAG Combining 2__ashlti3__muldi3__multi3__addxf3__muldf3__trunctfdf2__floatsixf__floatunsitfConsider warnings as errorinvalid type in function typeInvalid metadata BasicBlock #Malformed CST_SETTYPE recordMultiple MODULE_BLOCKs in same streamNumber of global variables removeddisable-localize-init-globalsno-bb-vectorizerRun SROA after loop unroll passverify-gl-postinitial-xfrom-bcReplaces fadd, fsub and fmul instruction with software versionsfalse && "Gradient with int coords are not supported for sampler"cbgetone_trueBlockqgpu.local.scratch.mem.used.pusha6x-regfile-layoutEnables QGPUIsel GL/DX/CL.llclib: error: invalid target 'HR12_bHR31_aHR44_cHUR1_cHW_NULL3IR3IR14IR69IR82IR109R9_cR17_aR26_dR30_aR30_bSAM1SAM23UAV18UAV30UAV33UR5_dUR7_bImageReadRC = PSEUDO_SUBG_ARITH dtypedVectorMI->getDesc().getNumDefs() == (unsigned)(QGPUVectorize::VECTOR_LIMIT)QGPU::getoneQGPU::branchNop Inserter for QGPU ILast == mods.asUint64 && "This Modifier value should match for MOVSW"MF && "MF null in handleMovsToOregs"Opcode != QGPU::BALL && "can't remove ball"false && "invalid qcc_constantexpressionopcode"NumMachOpds >= 2 && "Memory operand must have two or more components"MI.getOperand(NumDefs).isSymbol() && "No asm string?"scalarValue && "This is a scalar instruction"qgpu.dcb.scsLowering literal operands in Oxili BC instructions!isa(I) && "No control flow when adding to preamble"lbCI && ubCI && "Wrong dyn ldc intrinsic format!"CBIdentifyMD->getOperand(0) && isa(CBIdentifyMD->getOperand(0)) && "incorrect MD layout"no-instr-validationCheck if instructions are correct before encodingno-dcvt-foldingfalse && "Need to investigate when and why this code is needed"false && "Unsupported shift operation\n"_CL_divided_global_offset_CL_combined_num_groups_CL_globalatomic_log2OfWaveSizeII && "cannot get IntrinsicInst from Instruction for TexSrc2Mode"Dim && "Unknown dim in qgpu_atomic_op_uav"intrinsicinst && "wrong ldc"UavCoordValfalse && "Arugment expected in get.pipe.info"MemOrder && "Constant memory order and scope expected in post.atomic.rmw intrinsic"false && "Constant expected as operand for barrier intrinsic"SaveFuncSym && "No yield save routine"false && "expecting load".a.loadesub.uabsneg.smad.f32.div2shrm.b32jumppredfgather4rbrcst.activesleepMO->isImm() && "Invalid pixel ID for SAMGPx"TRC==&QGPU::UGPRCRegClass && "Only UGPR allowed for src1 of shuffle"false && "Should not be encoding an IBARY on this triple!"ENCODE FATAL ERROR (%s:%d: %s AddrModeImmRangeError: Full precision constantDMOD.CVTOnly schedule up to instructionsINumISADstOpds == 1 && "Expect only one dst operand"SrcInst &&"SrcInst is Null"GV && "Invalid __ugpr use"Enable folding relative addressingEnable commoning of mova1 instructionsSet a threshold for input sGPRs.Pos && "bad position in bb"(TrimLow || TrimHigh) && "no dead channels?"Def && "Expecting a valid definition"CoordMI && "Coordinate Precision Promotion: Nodef for CoordReg"QGPU Post RA fixupsProgram level conversion of mayvecs for QGPUdisable-I64Emulation_32_sub_op1_lo_5bitsinst->getType()->isHalfTy() && "Unsupported fp width"_smlgra-remat-cifalse && "Too many input registers beyond register budget"SI->PrevLI->endSlotIdx() == SplitSlotIdx && "Inconsistent split location"!PerAllocCtx->isVectorReg() && "Must be scalar"SlotIdx.isInstSlot() && "SlotIdx must be an instruction slot."map == RHS.map && "Cannot compare iterators from different maps"Admit mustvecsQGPU uGPR Propagate, Promote and FoldEntering state %d LDST: Out of Range Offset with stg.a+ instruction. Allowed Range is 9 bits, |0 - 511|ATOMIC.b: for src mode0/1/2, baseid ignored for a6x and abovethe source0 should use Src0AR for holding source data with src0AR operand. Usage: Src0AR[r0.x]ATOMIC.b: src0 not allowed for a6x and aboveRESINFO: for src baseid 6/7 reserved on a6xLDIB: for src mode0/1/2, baseid ignored for a6x and above LDST: Out of Range Offset with stgen instruction. Allowed Range is 13bits, |0 - 8191|LoadStore: GetWID instruction not supported in a4x and below Only address register a1 is allowed for mova1 instructionINFTEXTURE: Source2, if enabled, only for .mode6 and .mode7, Immediate value is allowed.PARTITIONING_INTEGERPARTITIONING_FRACTIONAL_EVENdcl_Extra_LocalMemory_Size is allowed with HS/GS onlyOUTPUTVARYINGRELPATCHIDCBUFFERBASEREGNot a valid Semantic/Interpolation/Sampling Mode for DCL_SYMBOLLOADGAU8INSTRLOADGENF32INSTRLOADTHRCCHEAS8INSTRSTGAS16INSTRSTXS16INSTRSTLWF16INSTRLOADGBAU1DS32INSTRLOADGBAT1DU32INSTRUAV_UNTYPED_3D_TOKSTGBAUT2DINSTRSTGBAT1DTYPEINSTRATOMMAXGENSOCU32INSTRATOMANDGENSOCS32INSTRATOMORGENSOCU32INSTRATOMDECLNGSOCU32INSTRATOMANDGGPUU32INSTRATOMBXORGNU321DINSTRATOMBSUBGU321D1LINSTRATOMBMINGU321D1LINSTRATOMBAMAXGS321DINSTRATOMBORGU323D1LINSTRATOMBCMPXGNU323DINSTRATOMBCMPXGU641DINSTRATOMBCMPXGU323D1LINSTRATOMBINCGS322D1LINSTRATOMBAINCLNGU32INSTRATOMBAINCRGGS322D1LINSTRATOMBINCRGGS323D1LINSTRATOMBAINCRGGU321DINSTRATOMBADECGS322DINSTRATOMBADECGU32INSTRATOMBADECLNGU322DINSTRATOMBDECRGGS322DINSTRATOMBADECRGGS322D1LINSTRATOMBDECRGGU322D1LINSTRMOVF16INSTRSTIS32INSTRSTIBF321DINSTRRESFMT3DINSTRMADF16DIV2INSTRSWZF32INSTRSWZS32U16INSTRMOVSS32INSTRMADM32F32F32F16INSTRLDIBBLKLF323DINSTRLDIBBLKGU163DINSTRSTIBAU163DINSTRLDIBU161DTINSTRATOMINCGENU32INSTRWMMACCUF16F16INSTRGATS32S16INSTRMACROSSD_ENABLESHFLGENU32INSTRLESSTHANLABELENDTOKENDCL_PROGRAM_START_TOKENDCL_CL_NUM_WORK_GROUPS_TOKENDCL_CL_LOCALMEMENDCONSTREGID_TOKENDEFAULT_TOKENDECLARE_TESS_OUTPUT_PRIMDCL_PS_TEX_META_FLAGSDECLARE_CL_FIRST_REG_PIPEFLOWTARGETCOVINSTRDEST_IMM_VALUESOURCE_OPERAND0SOURCE_MODIFER3MODE_TOKENDCL_CL_PREC %d ALU2: Out of Range Immediate Value given for Source0 Operand.It should be in Range -2047 - 2047 ALU3: Out of Range offset in Relatively addressed Source0 Operand. Max Offset value can be 1023 ALU3: Out of Range offset in Relatively addressed Source2 Operand. Max Offset value can be 1023FLOW: Invalid Instruction Repeat Number. It can be in range of 1 - 7 (rpt1-7)TEX: Destination operand of TEX cannot be dummy registerSTIB.BLK.L: src1 has to be sGPR.LDST: src1 can not be sGPR.clipPlanesimageAttachmentDataEntriesmetadataAllocationADRENO_IMAGE_ATTACHMENT_DATA_ENTRYADRENO_SHADER_COLLECTION_SUBSTATE_INFOfsGeneratedInputsMAX_TESS_EVALUATION_TEXTURE_IMAGE_UNITSMAX_PATCH_VERTICESMAX_TRANSFORM_FEEDBACK_BUFFERSMAX_DUAL_SOURCE_DRAW_BUFFERSIMAGE_EXTERNALUnknown_Limit_NameMaxVertexAttribsMaxImageUnits enableBindlessTexture="true"isInterleaved ID : GL_IMAGE_3DQGL_TEXTURE_2D_SHADOW subSampledSampler, IOBlock name = %s bindingStride = %d unsizedArrayOffset = %d location or component conflict with others. name mismatch with other stage.$VertexCountUint32$SharedMemGlobalBasePtr64YUV Conversion Matrix ArrayTessellation Patch Data Base Pointer (32-bit)Tessellation Patch Disable PrimtiveID StoreAn array of scale factors for texture foveation subsampled layout patchingMeshloopUnrollFactordoubleWaveSizeASIC Chip FeaturesforceRotationAlldisableInitialBarysizeOfFoveatedBinDataqglnext_shader_datallvm.sin.f32llvm.qgpu.max.f32llvm.qgpu.global.fset.reg.p0f16.v3f16llvm.qgpu.global.scalar.alloc.reg.p0i16.p0i16llvm.qgpu.global.scalar.alloc.reg.p0i16.p0v4i16llvm.qgpu.fcreate.map2.v2f32.f32llvm.qgpu.fstlw.v4f32curMetaGV && "metaGV bogus Null check"Linker - Glue Codefalse && "dynamic indexing case unhandled for matrices"Opnd1->isMatrix() && " matrix is expected "yuv_test_footerdataME(binding != QGLC_INVALID_INDEX_VALUE) && "invalid atomic counter binding"getGeomIdx(isSrc1Int || isSrc1Uint) && "integer type expected for ldexp argument 1"parentSym && "parentSym is Null"packedFragCoordexitBBasptr.baseasptr.offsetfieldName$setupBaryP_j_over_wallocRegInst && "allocRegInst is Null"ret != -1u && "invalid per-vertex offset"gvIt != CBLocInfo.mUniformGVMap->end()newTexCoords && "FB Fetch Patching: Could not create new texCoord"false && "Invalid get.sym.loc user!"false && "Invalid symbolType"mdNodes && "namedMDNode should not be Null here"(intrinsicID == llvm::Intrinsic::qgpu_global_fget_reg) && "getreg for bary coord is expected"false && "Wrong dynamic index intrinsic."insertPos && "BB needs a terminator"uniformSymbols && "uniformSymbols is NULL!"OpenGL Specialization PassFragCoordgl_LocalGroupSizeimageCubefalse && "initBUVSymbols called on invalid object"false && "setFbFetchStencilSampler called on invalid object"symNode && symNode->isArray()me->getSize() == 1condVal && "condVal to StoreInst is Null"UBO size exceeds the max size allowedsrc_modulatearg->getType()->isSingleValueType() && parmLLVMType->isSingleValueType() && "failed casting complex expression in parameter passing"node->isInSSBO() && "Only SSBO can contain an unsized array"cst && "cst is NULL"numComponentsSet <= numComponentsTotal && "the argument number of matrix constructor is overflow!"s2Aiimg2dmsaacoshminminValbitfieldReversecolortextureGatherOffsetsgl_PerVertex.gl_CullDistance+=>>=can't modify gl_BaseVertexARBcan't modify gl_SampleIDcan't modify gl_MaxVertexUniformVectorscan't modify gl_MaxCombinedShaderOutputResourcesqualifier not allowed on function parameter the initializer is not a valid arrayarray field selection out of range '%d'gl_CullDistance was used but extension is not enable!samplerArrayName && "NewPoolTString returns Null"Patch in is allowed in tessellation evaluation shaders onlyGL_OES_standard_derivativesGL_OES_texture_storage_multisample_2d_arrayAdd Assign +=EndStreamPrimitiveobjectSize == 1type == constant.typetargetTextureatomicMinitu_709can not delare SSBO without struct bodysharedOnly one Default label is allowed supported in vertex/fragment shaders only mat2PROFILE_argument must be an identifier.behavior 'unresolved identifier")" expected to end 'STDGL' pragmapreprocessor command must not be preceded by any other statement in that linefalse && "Pointer type expected for OpCopymemory\n"resultTy->isVectorTy() && "Unexpected OpCompositeExtract into aggregate but non-vector"resultPtrTy && "baseAddr is not pointerType in generateCompositeLoad"OpTypeAccelerationStructureKHROpConstantFalseOpArrayLengthOpImageGatherOpImageQueryLodOpSatConvertUToSOpGroupSMaxOpImageSparseSampleProjImplicitLodOpImageSparseSampleProjDrefImplicitLodOpTypePipeStorageOpCreatePipeFromPipeStorageOpGroupNonUniformBallotFindMSBOpGroupNonUniformFMaxOpConvertUToAccelerationStructureKHRfalse && "Unknown ray pipeline stage"optfinalgetRayDatagetRayStackpopulateRaysrayId.exit0alloc.addrloadRayIndexlower LOAD_BVH_BASEADDR, bvhptr (FracOdd) (Sampler) (TessellationCntl) (QGLNEXT_DCB_UBO_INDEX)metadataName: hwShaderSize: virtualRegisterIndex: vpcIndex: foveationQualityRegID: numIjRegIDs: workgroupSizeConstID: needsLocalLinearId: [ADRENO_RESUMECOUNTER_INFO] (Ver staticTextureMappings: [ADRENO_GATHER_SWIZZLE_PATCHING_READ][reads: numTextureMappings: textureMappings: [ADRENO_BINDLESS_MAPPING_DATA] (Ver [ADRENO_PATCHED_STATIC_GATHER_TEXTURE][patchConstantSize: isPrecise: isSSBOTopLevel: location: binningDescriptorGroups: viewDependentVisibilityStream: primitiveAttrViewStride: indexBufferViewStride: .metadataPaddingSize.word.hwShaderSize[ADRENO_SHADER_DEVICE_ALLOCATIONS].numAllocations.deviceAllocations.numTexSamInLoop.numVectorALUInst.symbols[ADRENO_OUTPUT_SYMBOLS].needsDrawID.cbSlot[ADRENO_DS_INPUTS].primitiveIDVirtualComp[ADRENO_PS_DESC].needsWGOffset.textureIndices[ADRENO_PATCHED_R24_UNORM_TEXTURES].positionSymbols[ADRENO_PATCHED_STATIC_GATHER_TEXTURE].isInsideStruct.shaderSignature[ADRENO_SHADER_COLLECTION_SUBSTATE_INFO].maxRecursionDepth"> HW Code CRC: 0xApplication type mismatch No input object file specified BinningVertexShader - Instruction stats - CMP : %8d,%8d (rpt), ratio %5.2f preamble_half_alu - imm_a : %8d - dyn_a : %8d - msaa : %8d - bias : %8d - sad : %8d - ldl : %8d,%8d (rpt), ratio %5.2f - stiba : %8d,%8d (rpt), ratio %5.2f - addrcalc : %8d,%8d (rpt), ratio %5.2f alias - InstInvalidate: %8d - Loop/backedges: %8d - Compiler Defs : %8d - VPC Indices : %8d half_alu_rpttex.preamble_isammem.ldgbmem.stib_rptmem.stibamem.pipr_rptDisableBindlessCBPreambleEnableHSLocalMemUsageXXXDisableMergedShaderSupportForceSingleWaveSizeBinningAvailableConstLimitsBGEColorSpaceTransformPtrBGEUnsizedArraySizeIndexPtrEnableUseTextureForROSSBOAllCompilerOptions0DisableSamClampOOBEnableConditionalMsaaForFbFetchresourceValueQCC_StageCreateFlagsconst INTERNAL_RTSHADERSTAGEQGLC_COLORSPACE_ENCODINGshaderStageMask="Error parsing bindless color space transform data TexForLargeUBONamereservedLocationEntrycomponent="Unable to parse GenerateSPIRV value 'Unable to parse XXXDisableMergedShaderSupport value 'Unable to parse DisableCentroid value 'Unable to parse EnableDeviceIndexAsViewIndex value 'Unable to parse DisableSamClampOOB value 'Unable to parse MaxAttributeSizeInBytes value ' WireframeMode (false): (QNGC) If true, then all primitives except points are rendered as lines DisableRotationWA (false): Disable rotation workarounds EnableSampleShading (false): Enable sample shading RenderTargetDisableMask (false): Mask of unused PS outputs. InitialTextureThreshold (0): Ratio of Num ALU Inst to Num PI Slot >/ A710 A503 A635 m_ElementSize * i && "memcpy dest pointer is NULL!"Unable to allocate metadata, no callback available. Lets the driver access information about the metadata allocation returned by the compiler. Version 1.0: Added metadataHandle Added metadataSize Added metadataStaticSize: The minimum amount of space for the structure Added metadataDynamicSize: The amount of space used for dynamic structures Added metadataPaddingSize: How much space was wasted as padding A list of input symbols. Note that the mask need not be contiguous for input symbols. Version 1.0: Added numSymbols Added symbols Version 1.1: Changed input symbols to be sorted by virtual register ID and merged symbols with the same virtual register ID. Data describing the layout of local/global memory for a merged HS. Version 1.0: Added isControlPointBypass: True if the HS has no control point phase. Added inputControlPointCount: The number of vertices feeding into the HS.(DX only) Added outputControlPointCount: The number of vertices written by the HS. Added patchConstSizeInBytes: The size in bytes of patch constant data written by the HS. Added patchConstTessFactorSize: The size in bytes of tessellation factors written by the HS. Added extraLocalMemorySize: The amount of local memory needed by the HS. Added vertexSize: The size in bytes of an output control point. A3x does not support clip/cull distances. This extracts data embedded into the D3D11 shader to get clip plane data from constant buffers bound to the shader. Version 1.0: Added numClipPlanes: The number of clip planes embedded. Added clipPlanes: Array of clip planes embedded. This holds all of the data for programming hardware support for stream output. Version 1.0: Added numElements: The number of stream output elements to write. Added numBuffers: The number of stream output buffers used. Added elements: Information about each transform feedback element. Added buffers: Information about each transform feedback buffer. Version 1.1: Added rasterizedStream: The index number of the stream to be sent to the rasterizer stage. Information necessary to patch a gather instruction in the bytecode. The instruction after the gather must be a NOP, so that if the value is swizzled to 0 or 1 the result can be broadcast to all registers in the destination mask. After that, if ASTC patching is required this will have the same requirements necessary for ASTC instructions. The numTextures value is only used for validation that all textures in the array have the same swizzle. Version 1.0: Added instructionOffset: The offset of a texture instruction in the bytecode. Added textureIndex: The index of the texture read in the instruction. Added numTextures: The number of textures in the texture array read in the instruction. Added is8BitIntWA: True if the instruction is part of an 8-bit int workaround Information about statically indexed textures returned from the shader patching interface. The patched texture index will be used to read the .XY component of the texture. The driver will be responsible for duplicating the texture into the new slot using a RG16_UINT format instead of an R24_UNORM format. Version 1.0: Added sourceTextureSlotIndex: The original texture slot index referenced. Added patchedTextureSlotIndex: The texture slot index referenced in the patching code. Enter context failed (id= ENQACKleft-parenthesisfull-stopfivelow-linetrailing backslash (\): can't erase directoryn>0 && "parts should have at least one valid entry": Bad ValueMask flag! CommandLine usage error:DW_TAG_imported_unitDW_LANG_Fortran77%7.4fvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Support/IntervalMap.cpp=ResCheck __ugpr addrspace(u0x x target datalayout = " } memory_scope_workgroup type!"Metadata are incompatible!PHI nodes must have at least one entry. If the block is dead, the PHI should be removed!Function return type does not match operand type of return inst!Referring to a basic block in another function! cannot be used for vararg call arguments!Logical operators only work with integral types!Cannot allocate unsized typeArgument value type does not match pointer operand type!fpext source and destination must both be a vector or neitherInvalid operand types for FCmp instructioninvalid linkage type for global declarationSize expression must be absolute. .symbol_resolver Personality Function||tocGOT16S_CSTRING_LITERALSS_NON_LAZY_SYMBOL_POINTERSthread_local_regularNo open Win64 EH frame function!expflog10fsinfsqrtlhsValno mod/ref ---- Block Freqs ---- dot-postdom-only DomFrontier for BB Enable BC Instruction counter pass for GLNext - counts instr passed to BENumber of SDiv instsNumber of IntToPtr instsNumber of InsertElement instsInterval Partition ConstructionStrong SIV applicationsWeak-Zero SIV applicationsGCD applicationsCoupled subscript pairsfalse && "Not proper child loop?" in block ': Show only simple regions in the graphviz viewerdot-regions-onlyuglygep.lpad-body.nonloopexitstackptrTheJmpBufPTI && "Terminator inst is expected".c.offOpenGL Workarounds Passgs_instance_idpostDomNode && "No mainline BB is found"Replace global load/store BC instructionsvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/InstPatternMatchPass.cppbb-vectorize-no-mem-op-boostUse a fast instruction dependency analysisbb36-vectorize-max-pairs-per-groupThe maximum number of candidate instruction pairs per groupbb36-vectorize-no-bools.cmp!insaneIntVal(Res) && "Insane int value"tmpcast(secondOp >= Instruction::CastOpsBegin) && (secondOp < Instruction::CastOpsEnd)scalar_alignment.t.lhsNumber of load instructions CSE'dLoop Invariant Code MotiontxElemTy &&"ElemTy is Null"vectorIndices.curEltOffset == 0 || numComponents == 1disable-separate-const-offset-from-gep" [ color=lightgray ] Number of reloads insertedbranched() && "Cannot access branch data in non-branched root" EMPTYlivestacksNumber of copies coalesced fi#internalRegPrefswp-max-stagessoftwarepipeSplit critical edges during machine sinkingMBB exits via conditional branch/fall-through but doesn't have exactly two CFG successors!MBB exits via conditional branch/branch but doesn't end with a barrier instruction!Explicit operand marked as defNo largest legal super class exists.PHI operand is not in the CFGVirtual register Live range valno is marked unusedtargetpassconfigdisable-peepholeNumber of move immediate foldedSeed Live RegsOptimize for sizeB < GroupSize && "Array overflow"false && "Failed to allocate vector register"VRM->getPhys(LI.reg)==PhysReg && "Inconsistent double assignment to already assigned aliased LI"CurrIndex < VecInfo->getVecSize() && "No current interval!"false && "No instruction at current slot"TRI && "no register info set"disable-cross-class-joinScheduling-Units Graph for invalidNumber of trivially dead stack accesses eliminatedvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cppLC < RTLIB::UNKNOWN_LIBCALL && "LC out of bound"Do not know how to scalarize the result of this operator! disable-sched-physreg-joindisable-sched-stallsRoughly estimate the number of cycles that 'long latency'instructions take for targets with no itineraryinline asm not supported yet: don't know how to handle tied indirect register inputsMemBarrierRegisterTargetExternalSymboluaddobrindstacksavesetfalse2): __moddi3__fixsfti__fixdfhi__floatditf__gesf2__gtdf2__sync_lock_test_and_set_1__sync_lock_test_and_set_4__sync_fetch_and_sub_1__sync_fetch_and_and_4Function 'Invalid CE_EXTRACTELT recordInvalid CE_SHUFVEC_EX recordinternalize-public-api-filevendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/HLCUtils/LowerHighLevelIntrinsics.cppsamDesValugprllclib: error: unsupported instructions CriticalEdgeCount: NonCriticalEdgeCount: a5x_64HR1_dHR9_cHR12_aHR18_cHR24_aHR38_aHR47_aHUR4_dHUR5_cHW_TREG32HW_WIIDIR73R15_dR29_aR31_dUAV16UAV52SamplerRCPredRC.offset_Missing closing parenthesis on operandQGPU::iaddQGPU::cosQGPU::retqgpu_binningRegister Rewrite for QGPU Const Register Allocation for QGPU false && "LM allocated exceeds architecture limit"AI->getBitWidth() < 8 && "Unexpected size"NewOpcode && "Couldn't find a proper opcode"false && "Null instruction in the middle of scalarized " "vector instruction"qgpu.constant.dcb.dataarg_idfullCLowering literals in Oxili BC instructionsqgpu_cbdyncachedataenable-new-vectorizee-p:32:32-f16:16:16-f32:32:32-i32:32:32-i8:8:8-i16:16:16-n32ATy->getNumElements() == 1Operand0 && "NULL"_CL_scratch_LM_reg_CL_local_linear_id_CL_enqueued_local_sizevendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUIntrinsicLowering.cpp((unsigned)abs(Offset) <= QTM.getConstRegFileSize(mod) * 4) && "Offset too large or too small"II && "Not an intrinsic?"false && "Unhandled return type\n"ty == MVT::i32u8u64(nSH)mad32.bf16mova.usamMadsamlDP2ldthr.aldlwgetTargetFeatureFlag(QF_HAS_A6orHIGHER_ENCODING) && "Can not LD/ST from/to CONST register"ALU3 with 2 const operands can not be relative addressingm_pSectTab[SECT_SRC_CODE_INTERLEAVE].SectSize >= (sizeof(QGPUSrcCodeInterleave) - sizeof(QGPUSrcCodeMapEntry) - sizeof(QGPUSrcCodeFilePath) + m_SrcCodeInfo->numFiles * sizeof(QGPUSrcCodeFilePath) + m_SrcCodeInfo->numMapEntries * sizeof(QGPUSrcCodeMapEntry)) && "Section size too small"LM Broadcast offset must be <= 256Basic block with END instruction is not the last basicblockMDstRegs.size() == SrcRegs.size() && "Unexpected output move instruction"DefMI && "RCMovMap not up-to-date"Run CSE on = this 0 && "no dead channel elimination (combine case)"!"FIXME: implement binary OOB case"QGPU Peephole OptimizerscanPos != entryBlock->end() && "Missing SHPS ?"QTM->getPreamble(MF) != NULL && "STC with no Preamble section?"Hint.first != QGPURI::RegAgg && "Aggregate cannot reach here"neg_hivalME && "Emulated operand NULL for subgroup_broadcast"llvm.qgpu.subgroup.inclusive.int.v2i32valTy->isVectorTy() && "Must be a vector type"_cmpEmulating Oxili BC instructionsgra-bborder-tsort , DstRelAddr: LI_Src != NULL && "No source interval"!(SplitFlowFromPred && JoinFlowToMBB && !IsPreRASSAD) && "Unacceptable control flow. This must be removed by critical edge splitting"!DefSeen && "unexpected multiple defines"PrevMBB == NextMBB && "Live intervals must be split within basic blocks"(FromRCSize >= ForRCSize || (ForRCSize % FromRCSize)==0) && "FromRC and RC are incompatible"AssignedPhyReg == 0 && "Register is already assigned"lm-spillinguppf-preambleDo not promote preamble instructions (a6x)MI.getOpcode() == QGPU::PHI && "expected a phi"TextureArray(.a) option not allowed for conv instruction.the ldthr.a instruction should use g with source 0. Usage g[r4.x+32] the ldx instruction should use g with source 0. Usage g[r4.x+32] LDC: for src baseid 5 is only for src mode 5/6 for a6x and abovethe ldgb instruction should use g with source 0. Usage g[r4.x+32] the stthr.a instruction should use g with dst. Usage g[c8.x+r4.x+32] LDIB: For stthr.a Source1 should always be Immediate Value LDST: Destination Offset Out of Range with g2l instruction. Allowed Range is 13bits, |0 - 8191|ATOMIC.b: for src baseid 5 is only for src mode 5/6 for a6x and aboveSTC: for stc instruction allowed only from a6x STSC: for stsc instruction src0 should be IMM FMA: Only 32 bit Source Operand allowed SCALE: Only allowed in a5xSource Operand Out of Range for 16Bit Signed DataType.Allowed Range is -32768 - 32767TEXTURE: Source2, if enabled, for .mode0 and .mode4, 16bit GPR is only allowed.A6Xint16int32POINTERTRIANGLE_ADJ the maximum instance count allowed is 32INPUTCOVERAGEPATCH_TOTAL_SIZEORIGINREADSINTGEOPCODECOVF32U32INSTRLOADGENF16INSTRLOADXS32INSTRSTTHRAU32INSTRSTXS32INSTRG2LU8INSTRSTLWF32INSTRLOADGBU1DF32INSTRLOADGBT1DF32INSTRLOADGBAU2DU32INSTRLOADGBAT4DU32INSTRVGS_CTRL_EATOMCMPXCHGGENGPUS32INSTRATOMMINGENGPUU32INSTRSHPEINSTRATOMBAORGU322D1LINSTRATOMBAXORGU321D1LINSTRATOMBACMPXGU323DINSTRATOMBAXCHGGS32INSTRATOMBAXCHGGF323DINSTRATOMBAINCLNGS323DINSTRATOMBAINCLNGU323DINSTRATOMBADECLNGS321DINSTRATOMBDECLNGU32INSTRATOMBDECRGGU321DINSTRATOMBDECRGGU321D1LINSTRTRUNCFINSTRCTZBINSTRQUADSHFLMODEHORIZINSTRATOMMINLS32INSTRAROMDECLS32INSTRATOMINCLNGU32INSTRMAD32BF16INSTRLDIBAF321DTRCKINSTRLDIBAF321DTINSTRINVSRINSTRSHLG32INSTRLOG2HINSTRATOMCMPXGU64INSTRMADM32F32F16F16INSTRLDIBUNTYPEDU322DINSTRSTIBUNTYPEDS323DINSTRLDIBBLKGS163DINSTRLDIBBLKCS162DINSTRLOADLBLKU32INSTRLDIBAU163DINSTRSCTF32INSTRSCTF32U16INSTRSHFLRUPW8INSTRSHFLRDOWNU16INSTRCOMPARISON_TOKENDECLARE_HS_ALLCONTROLPOINTSSIZEINBYTESDECLARE_CS_ThreadGroupIdRegDCL_PATCH_CONST_TESS_SIZE_TOKENDCL_STATIC_BR_MSKDCL_CL_CSSTATECONSTREGIDDECLARE_ATTRIBUTES_ADDRREG_NUMHALF_SGEN_REG_NAMESOURCE_LASTEMPTYLINESYNC_INSTRFLOW_INSTR_3XCEPT_TOKENATOMBINSTRSTPINSTRLOADXAINSTRMADFINSTRTEX_INSTR_4SOURCE_CHANGE_PARAM2PACKED_MODELDST: Destination/Source can not be Predicate Register.staticReadsgathersinputTargetInfoinfosADRENO_INITIAL_TEXTURE_LOADADRENO_PATCHED_R24_UNORM_TEXTUREgsDescfsBaryInputsglslSymbolsMAX_COMBINED_TEXTURE_IMAGE_UNITSMAX_COMPUTE_IMAGE_UNIFORMSMAX_GEOMETRY_OUTPUT_VERTICESMAX_TESS_CONTROL_UNIFORM_COMPOENTSMAX_TESS_CONTROL_TOTAL_OUTPUT_COMPOENTSMAX_TESS_PATCH_COMPOENTSMAX_CLIP_DISTANCESMAX_DUAL_SOURCE_DRAW_BUFFERS_EXTQGLC_SHADERLIMIT_NAME_MAX_CULL_DISTANCESFRAME_BUFFER_FETCHEXT_BLEND_FUNC_EXTENDED Shader Metadata ============MaxGeometryTotalOutputComponentsMaxTessEvaluationInputComponentsMaxClipDistancesisBindlessVertex enableBindlessAccelerationStructure="true"" subsampled="GL_UNSIGNED_BYTEGL_SAMPLER_EXTERNAL_OESGL_INT_SAMPLER_3DGL_INT_SAMPLER_CUBE_ARRAYGL_UINT_IMAGE_2D_ARRAY ... (enable QGLC_DUMP_PROGRAMBINARY for complete printout) centroid,RGBA32 fixedTargetRegister = %d built-in variables invariance mismatch.qgpu.invariant.pointsize$TextureFovSubsampledConstants$FragmentSizeUVec2Array$SubpassFragCoordFovOffsetVec2Array$gvQGLC Options:disableSchedulerenableTextureHighpWAenableHWStereoRenderingenablePackedSampleexp_functionsllvm.qgpu.umax.i32llvm.qgpu.min.f32llvm.qgpu.global.scalar.alloc.reg.p0f32.p0v4f32llvm.qgpu.icreate.map4.v4i16.i16llvm.qgpu.fcreate.map5.v5f32.f32llvm.qgpu.fcreate.map6.v6f32.f32llvm.qgpu.clzs.i32llvm.qgpu.atomic.imax.oob.i32llvm.qgpu.atomic.or.oob.i32llvm.qgpu.atomic.and.oob.i32qglnext_preserve_16bit_denormgv_user && "Unexpected user of gl_Layer GV"__qcom_BARY_Coordinate_samplepointerTy && "pointerTy is Null"baseType && "baseType is NULL!"rhsVec->getSize() == 0x3 && "rhs Vector size is not 3!"mSetupInfo.entryPos && "entryPos is null"yuv_test_falsevecTy->isVectorTy()(mCSData->subgroupInvocationID != NULL) && "Oh No! subgroupInvocationID is NULL "prim.idldib_v2i32VH_ && "OpRayQueryGetIntersectionPrimitiveIndexKHR" " is not supported"TraceRayNoneImpl__qcom_BARY_Coordinate_centroid_non_persp_i__qcom_BARY_Coordinate_centroid_non_persp_jptrTy != NULL && "Base GV is not a pointer"(subGV != NULL) && "can't find corresponding sub GV!"errorCode && "Invalid Metadata for link error"store && "no store for output, found load instead\n"position != NULLpConst != NULLelementIndex && "Unexpected null elementIndex"gsFlattenInputLoadAddrlength == 0false && "Certain TessEval load cases not handled yet"(vecTy ||dataTy==mInt8Ty) &&"Wrong Load/Store type"(col < numCols) && (row < numRows)0 && !"Unrecognized basic dimension"gl_BaseVertexARBgl_SampleMaskgl_MaxGeometryOutputComponentsusampler2DYUYV samplerExternalOESitexture2DArraystringSection->type == SO_SECTION_STRINGleftNode->isInSSBO()constUnionNode != NULLlast != Head->begin()arg && "invalid expression cast in paramter passing"dynIndex != __null && "dynamic index can not be null"uimg1duimgcadegreesroundEvenldexpbaseetamatrixCompMult# %s No statements are allowed in a switch statement before the first case statementcan't modify gl_MaxVertexTextureImageUnitscan't modify gl_MaxTextureImageUnitscan't modify gl_MaxAtomicCounterBuffersSizeconstructorsamplers cannot be output parametersindexing into an attribute array using a non-constant expression is not permittedfunction cannot take any parameter(s)Wrong gl_PerVertex field!not a legal layout qualifier idbinding exceeds limit:? Vector * Scalar Assign *=Right shift >>NegateMost significant bit for sign intsinecosineConstruct vec2false case gl_SampleMaskOESarrays used as function arguments must be declared with a sizeType for default precision qualifier can only be float, int, image, atomic counter, or a sampler type is for Vulkan api onlyunbalanced parenthesisBad pragma: integercurrentInput && "currentInput is Null""invariant" expected after 'STDGL' keyword is not permitted in an terminator && "Terminator inst is expected."Not SetOpTypeSampledImageOpConvertUToPtrOpVectorTimesMatrixOpSDotKHROpUDotAccSatKHROpSGreaterThanEqualOpULessThanEqualOpFOrdNotEqualOpGroupCommitReadPipeOpImageSparseSampleDrefImplicitLodOpModuleProcessedOpGroupNonUniformFMinOpTraceRayKHROpImageBlockMatchSADQCOMError: Name checking across different symbol types failed.index <= m_computeLiveAtIndex.size() && "out-of-bound index"dummyStateId$qgpu.stable.fb.callableisRG0stackFrameOffsetFunc != NULLexec.rc.0gep.tmpshader.tablecacheState.updatedSubstateToMailboxOffsettermInst != NULLstateIdcall && "Must be a call"rb_phi (Center (.5,.5)) (Gather4G)usesUAVs: usesCBs: physicalRegisterPrecision: streamIndex: vertexSize: domainVRegID: needsViewID: scratchVec4ConstID: packFactorY: virtualRegisterComponent: numComponents: numBuffers: endOfQuad: loads[[ADRENO_GATHER_SWIZZLE_PATCHING_READRGB10A2_EXTRACT][[ADRENO_BINDLESS_EMULATION_MAPPING_RANGE] (Ver bindlessSamplerSupport: objSize: [ADRENO_PATCHED_STATIC_GATHER_TEXTURE] (Ver [ADRENO_DYNAMIC_CBCACHE_ENTRY][[GL_SYMBOL_INFO_IMAGE] (Ver matrixStrideInBytes: [GL_IRSHADER] (Ver constColorValZ: [ADRENO_DESCRIPTOR_USAGE_INFO] (Ver [ADRENO_DESCRIPTOR_GROUP][[ADRENO_MS_OUTPUT_DESC] (Ver maxRecursionDepth: .hasAtomic.drawParametersRamLocation.regIDs.relpatchIDRegID.needsPackedFragcoordXY.numStreams.elements[ADRENO_PATCHED_SHADER_HANDLES][ADRENO_GATHER_SWIZZLE_PATCHING_READ].isRightShift.bindlessOffset.shaderStageMask.bindlessRWBufferSupport.objData.inputTargetInfo.shaderVersion.YUVIndex[GL_UBO_LOCATION][ADRENO_CONST_COLOR_OUTPUT_ENTRY].constColorOutputEntries.primitiveAttrs.shaderCRC.rayDataSize Unable to read initial Texture desc .Value[3]preamble_half_efu - Texture Instrs: %8d,%8d (rpt), ratio %5.2f - img : %8d - save callstack: %8d - atomicl : %8d,%8d (rpt), ratio %5.2f - bindlessd : %8d,%8d (rpt), ratio %5.2f - stsc : %8d,%8d (rpt), ratio %5.2f - BRAC Instrs : %8d - Uvgs : %8d half_reg_footprinttex.gatherGmem.ldcamem.ldibamem.ldib_b_rptEnableUnSafeMathInputAttachmentFormatPtrHighestBankBitEnableSharedConstantsABGEAuxDescTypeBitsPtrABGESRefUseVRSFoveationQualityEnableVRSEnableUseTextureForLargeUBOSOGERegisterMaskPtrEnableAliasRTEnableOOBCheckForRelConstMemScratchBindlessBasepRootUAVsconst INTERNAL_RESOURCE_SIGNATURE_STATIC_SAMPLERsize_tstageQCC_LibraryExportTypeCIStageRTSHADERSTAGEError parsing reserved location element data: unaligned input attachment elements bufferUnrecognized compiler option 'Unable to parse QCCOptionString value 'Unable to parse DriverData value 'Unable to parse EnableDynamicCBCaching value 'Unable to parse FragDataSize value 'Unable to parse DumpMetadataToDebug value 'Unable to parse EnableFastColorBypass value 'Unable to parse ShutOffUAV value 'Unable to parse GLViewMask value 'Unable to parse EnableBindlessVertex value 'Unable to parse RenderTargetDisableMask value 'Unable to parse EnableEnhancedPrediction value 'Unable to parse EnableConditionalMsaaForFbFetch value ' GLSLShader (__null): GLSL Shader to compile LLVMDebugType (__null): LLVM stage to debug GenerateTraceRayShader (false): Generate Trace Ray Shader PSAALineWidth (3.0f): Line width for AA lines EnableTiledUAVs (false): Enable partially resident resource support for UAVs ForceConstantRAMMode (false): Force constant RAM mode IsSSO (false): the shader(s) to be linked will be treated as separate shader object XXXEnable10Level9Support (false): Enable compilation for a limited subset of DX11 features for targets that don't support DX11, but do support DX9. Implies: EnableDynamicCBCaching, ForceConstantBufferCaching, DisableMergedShaderSupport, and sets the default for AvailableConstLimits to VS:320, PS: 192 A505A623A741 A680 Invalid Fast color bypass: writeMask for InitialBary is not 0x3 or 0xc, error in compiler-generated metadata. pGathersPtr + pGathersDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"pInputTargetPtr + pInputTargetDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"Provided metadata buffer was too small, unable to write metadata. Major version mismatch, unable to fill out metadata. Data describing the layout of local memory for a merged GS. Version 1.0: Added inputVertexCount: The number of vertices feeding into this GS. Added maxOutputVertices: The maximum number of vertices written by this GS. Added extraLocalMemorySize: The amount of local memory needed by this GS. Data describing special outputs used by the GS. Version 1.0: Added outputsMiscFlags: True if the shader outputs misc flags (required by the GS). Added outputsRTArrayIndex: True if the shader writes to the Render Target Array Index. Added outputsViewportArrayIndex: True if the shader writes to the Viewport Array Index. Added miscFlagsRegID Version 1.1: Added rtArrayIndexVirtualRegAndComp: Virtual register location for the render target array index output (vreg * 4 + comp). Added viewportArrayIndexVirtualRegAndComp: Virtual register location for the viewport array index output (vreg * 4 + comp). Version 1.2: Added rtArrayIndexVPCIndex: VPC index for the render target array index output. Added viewportArrayIndexVPCIndex: VPC index for the viewport array index output. Information about bindless resources defined on a per-type basis. Version 1.0: Added slotType: The HW slot type being allocated Added shaderStageMask: Which shader stages this mask applies to Added numEmulationHWSlots: how many HW slots are allocated for emulating this resource type Added numEmulatedGroups: how many groups are using emulated support Added numBindlessRanges: how many ranges of bindless groups are using HW support Added emulatedGroups: list of emulated groups Added bindlessRanges: list of bindless ranges Tells the driver about the memory layout of a mesh shader's outputs. Version 1.0: Added maxVertexCount: How many vertices the shader can write. Added maxPrimitiveCount: How many primitives the shader can write. Added outputTopology: Primitive type for mesh shader results (line or triangle). Added writesVisibilityStream: True if the mesh shader uses SV_CullPrimitive. Added reserved Added vertexPayloadSizePerWorkgroup: The total amount of memory needed per workgroup. Should be the sum of the next 4 values. Added vertexAttrSizePerWorkgroup: How many bytes each workgroup can use for vertex attributes. Added primitiveAttrSizePerWorkgroup: How many bytes each workgroup can use for primitive attributes. Added indexBufferSizePerWorkgroup: How many bytes each workgroup can use for index buffers. Added visibilityStreamSizePerWorkgroup: How many bytes each workgroup can use for the visibility stream. Added vertexAttrViewStride: How many bytes to advance to next view in vertex attributes (if 0, not view dependent). Added primitiveAttrViewStride: How many bytes to advance to next view in primitive attributes (if 0, not view dependent). Version 1.1: Added indexBufferViewStride: How many bytes to advance to next view in index buffer (if 0, not view dependent). This can be view dependent because it holds vpi/rti/vrs data per-primitive. Added reservedVisibilityStreamViewStride Version 1.2: Deprecated visibilityStreamViewStride Added viewDependentVisibilityStream: True if the mesh shader writes view-dependent SV_CullPrimitive. Unexpected Fixup type, unable to fill out metadata. Print regions of function to 'dot' file { Number of loops without predictable loop counts.iv.nextType-Based Alias Analysisenable-uniformbranch-probWeight of the branch likely to be taken (default = 64)ssretNumber of IV remainder operations eliminatedfalse && "unexpected GV usage"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/SimplifyVectorAlloca.cpp!newNamedMD->getNumOperands()slp-vectorize-hor-storeBundle && "Bundle is NULL!"Ignore target informationbb36-vectorize-no-mathop && "Aggregated operand is Null"offsetsubasadValue PropagationNumber of loads PRE'dNumber of congruent IVs eliminatedIV.S.next.Loop Size = .gepscalarrepl-ssaenable-ir-taildupBundle Machine CFG EdgesPrint Garbage Collector Information Live Ins:SSA # End machine code for function +:[??RegMustVecUndoneNumber of hoisted machine instructions CSEedMachine Module AnalysisMaximum stages allowed in the generated scheduled.Modulo Software PipeliningUsing an undefined physical register last instruction was at Live segment ends at B slot of an instructionLive segment ending at dead slot spans instructionsAfter PreSched2 passespeephole-optverify-regallocVRM->getPhys(VirtReg.reg) == PhysReg && "Inconsistent unassign"fix min half regs!VRM->hasPhys(LI_Info->Intv->reg) && "Must be the first assignment"false && "No definition of virtual register"Number of times interval joining abortedfpexn_selector_valNumber of copies inserted for splittingssc-dce-limitlive-debug-variableslivedebugNumber of DBG_VALUEs insertedValue in multiple maps!Disable regpressure priority in sched=list-ilpAtomicSwapEH_SJLJ_LONGJMPCopyToRegfsqrtfp_round_inregbrcondctlzMem:fast-isel-abortDAG LegalizationInstruction Scheduling Cleanup__divqi3__gcc_qsub__gcc_qdiv__fixxfti__sync_fetch_and_or_8Invalid MODULE_CODE_ASM recordA file containing list of symbol names to preservesort functions per-kernel call chain__qcom_DSMetaInfo(subgroupSizeVal==16 || subgroupSizeVal == 32 || subgroupSizeVal == 64 || subgroupSizeVal==128) && " Only subgroupsizes of 16 32 64 128 are Supported"Op && "Op is NULL!"inst-coveragePASSED (HR1_cHR7_dHR13_bHR14_aHR23_cHR30_bHW_R63IR16IR56IR95R13_cR23_cR24_cR33_dR41_cR44_dSAM13SAM19SR0_dSR2_cUAV1UAV20UAV49FPGPRRCQGPU::move.i16QGPU::rsqQGPU::fsel32WF::unknown!GenPredT || !GenPredF || TrueMBB->isLayoutSuccessor(FalseMBB) || FalseMBB->isLayoutSuccessor(TrueMBB)MFI->getParent() == MF && "Ensure we only visit curent function"isPhysicalRegister(reg) && "reg must be a physical register"instScalarizing Oxili BC instructionspreamble_cfg-preamblevendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUPreambleTransform.cpp.dot.txt0 && "Expecting instruction uses only"false && "Unknown function attribute"false && "Unsupported type in select \n"_CL_SP_CL_gpu_atomic_lock_ptrfalse && " Constant expected as operand 2 for interpolate intrinsic"0 && "opencl_vec_type_hint without enough parameters"(eq).gpucmpv.fmad.s16movrcppredegetpossamgp0stgatomic.inc.lnldib.kldcqgpu.amplificatilon.shadervendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPUInstructionValidator.cppFImmNotAllowedError: : out of range.: Indirect register access not allowed for sourcea memory locationDstAndSrcHaveSameRegError: ISAOpcodeUndefinedError: LDSTDMOD.SHRBackward for ESX and forward for othersgrey0 && "Unexpected num of outpus for LDST instruction"defMIBreak Complex Expressions for QGPUterminator && "Malformed basic block lacks a terminator"enable folding andgdisable-relative-lm-broadcastRun CSE on <= this false && "unhandled target class for folding negative float"QTM->getPreamble(MF) != NULL && "STSC with no Preamble section?"false && "opdInstMapEntry is NULL"sum_loz_flagsel_hivalME && "Emulated operand NULL for subgroup arithmetic intrinsic"VSegPos.value() == LI && "Inconsistent LiveInterval"LI_Alias_Child && "LI_Alias_child is Null"false && "No child interval"!IsStorageAssigned && "Interval is assigned a storage"uGPR promote/fold after instruction schedulinguppf-lqQGPU Pixel Interpolator Optimizer Passout of dynamic memory in yyensure_buffer_stack()FLOW: ENDQUAD is not allowed for predicate instructions with a target LDST: Out of Range Offset with ldg.a instruction. Allowed Range is 13bits, |0 - 8191|WARNING: LDG.a with RRI form only allowed from a7p LDST: Out of Range Offset with ldx instruction. Allowed Range is 13bits, |0 - 8191|LDST: For destination operand type GPR, allowed regNum range 0 to 47 and 63 for atomicsLDST: src2 should be IMM as its legacy LDC instr.the ldgb instruction not allowed in a6x and above LDLBLK: If src0 is immediate type, it should be followed by a uGPR register idthe stg instruction should use g with dst. Usage g[r4.x+32] the stg.a instruction should use g with dst. Usage g[c8.x+r4.x+32] atomic.inc|.dec with .rg option src1 should be GPR and 32LDIB: use g with destination. Usage g[r4.x] LDIB: ldib.k needed if destination is c[a1.x].LDST: src2 should be IMM as its legacy LDIB instr.STIB|LDIB: Valid offset value is between 0 to 127 with STIB or LDIB ALU2 CAT16: Only one SRC can be CONST, not all the two SRC0, SRC1ALU3 - AND MERGE: b16 is for 16 bit sources src[1]ALU3 DP2ACC: Only allowed in a6x and above.ALU3 DP2ACC: Both Src0 and Src1 modifier should be same either low or highALU3 DP4ACC: Only allowed in a6x and above.SWZ - This instruction cannot be repeatedSCT: last-use-if-source-is-a-GPR is not allowed. NANSource Operand Out of Range for 16Bit Unsigned DataType.Only Allowed Range is 0x0 - 0xffffoSAMPLEINDEXPOSITIONCYCLECOUNTCENTROIDCONTINUEDMAXFINSTRCOVU16F16INSTRLOADGU8INSTRSTXAF16INSTRSTLS16INSTRSTPU16INSTRATOMADDGU32INSTRLOADGBAU3DF32INSTRLOADGBAT2DS32INSTRLOADIBINSTR_TOKUAV_TYPED_2D_TOKDCFLUSHRINSTRBRAAINSTRYIELDINSTRATOMINCLNGENSOCS32INSTRATOMDECLNGENGPUS32INSTRATOMDECRGGSOCS32INSTRATOMBMINGNU321DINSTRATOMBANDGNU321DINSTRATOMBASUBGU321D1LINSTRATOMBAMINGU323D1LINSTRATOMBAMAXGU32INSTRATOMBMAXGU322DINSTRATOMBORGU322D1LINSTRATOMBXORGU322DINSTRATOMBINCGU323DINSTRATOMBAINCRGGS323D1LINSTRATOMBADECGS323D1LINSTRATOMBADECRGGS321DINSTRATOMBDECRGGU322DINSTRMOVA1UINSTRCOVS32U32INSTRBRCSTACTIVEW4U32INSTRQUADSHFLMODEDIAGU16INSTRSTIBU323DINSTRLDIBAU321DINSTRBUFINFO0DINSTRSWZU32F16INSTROFLTOKENLDIBUNTYPEDU321DTINSTRLDIBTYPEDU323DRCKINSTRLDIBTYPEDU162DINSTRSTIBTYPEDU321DINSTRSTIBTYPEDF321DTINSTRSTIBTYPEDU162DINSTRSTIBTYPEDS163DINSTRLDIBBLKLF163DINSTRLDIBBLKCF323DINSTRLDIBAF163DRCKINSTRSTIBBLKS323DINSTRSCTU32INSTRSCTU32U16INSTRGETWIDU16INSTRGETFIBERIDF32INSTRRBIINSTRSHFLXORU32INSTRSHFLUPW8U32INSTRRAYTRANSFORMINSTRUNSIGNED32TOKENDCL_CL_GLOBALATOMICOPTWAVESIZEMINUSONE_TOKENHALFLOGETOKENUAV_UNTYPEDIMEN_1DDIMEN_3DDECLARE_CS_LocalMemoryUsedBytesDECLARE_NUMVIEWSLDST_INSTRPIPCINSTRSTLWINSTRANDGINSTRDP4ACCINSTRMOV_IMM_VALUE0ALIAS_SRCSOURCE_CHANGE_PARAM1ICB_STORE_DESTALU2: Both the Operands can not be located in constant memory Out of Range offset in Relatively addressed Source0 Operand. Max Offset value can be 1023In Mov/Cov Instructions, Source Operand can not be Predicate RegisterTEXTURE: Destination cannot be Predicate Register.constantExpressionsmappingsclipCullInfo_A4xinputs_A4xhsglueCodeDesc_A6XADRENO_DEVICE_ALLOCATIONADRENO_SO_DATAADRENO_GATHER_SWIZZLE_PATCHING_READADRENO_SHADER_CREGISTER_USAGEGL_IRSHADERADRENO_CONST_COLOR_OUTPUT_ENTRYallStageInputsglslShaderDatavsPrimSizescreenCoordTexUsageInfoBufferBlockBufferSubElementSubElement_InputMAX_COMBINED_ATOMIC_COUNTERSMaxFragmentTextureImageUnitsMaxComputeImageUniformsMaxCombinedAtomicCountersQGL_TEXTURE_EXTERNAL_NV12_QCOMQGL_UNSIGNED_INT_TEXTURE_3D precision = %s name = %sPositionRotationMat2OpenGL Tessellation Shader gl_PatchVerticesInBin dimension to mod gl_FragCoord uvec2draw parametersConstants for texture foveation subsampled layout patching (ONE_OVER_NORMALIZED_BIN_WIDTH, ONE_OVER_NORMALIZED_BIN_HEIGHT, and BIN_STRIDE_INT16)disableYUVllvm.qgpu.dsy.v2f16llvm.qgpu.umul24.i32Error: shader version mismatch qgpu.tcs.input.controlpointsfalse && "Unexpected intrinsic called with getreg of Layer"!arg->hasStructRetAttr()defaultVal && "Default valued is expected."ptr->getType()->isPointerTy() && "invalid pointer to initialize"dstNumRows == srcNumRowsqgpu.glsl.tes.read.tessfactor.sizegl_LocalInvocationID!isSrcInt && "frexp operates on float point only"bindlessOffsetget_intersection_instance_indexVH_ && "OpRayQueryGetIntersectionInstanceCustomIndexKHR" " is not supported"get_intersection_object_to_world(HitKind->isInt() || HitKind->isUint()) && "int/uint expected"NewPoolTStringTyOfGlPerVertexdummyVertexIDwginit_tailinoutPointSizeFacegl_BaseInstanceARBgl_MaxTextureImageUnitsgl_MaxFragmentAtomicCountersgl_MaxComputeWorkGroupSizebooltexture2DArrayvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/codegen/MultiViewExpansion.cppProgram size: %d, HW size: %d, uboLoc: %8x, %8x outVar && "gl_ViewportIndex is Null"false && "GetGSInfo called on invalid object"dstTType->getBasicType() == srcTType->getBasicType()formalGV != NULL && "Redefined global variable with different type?"idxNode && baseNodenode != __nullsrcElem && "invalid expression cast in construct matrix"idxNode && "right node not found"masinhbitsbitfieldExtractfindLSBmangled && "NewPoolTString returns Null"memory && "could not allocate type list"threadPool != NULL|=boolean expression expectedstructure != __nullblock definitions are allowed only for uniforms/buffersarray index out of range '%d'Vulkan block layout can only be std140 or std430component selection cannot be used for interpolantparameter qualifiers must stay before precision qualifierssmooth/flat should only preceed in/centroid in/out centroid out%d-component vector of Assign =Or Assign |=Convert Int to BoolFunction Call: Read InputTexture3dLodconst float!pragmaTablevendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/include/LA/gl_core/ConstantUnion.h( colNum == 2 || colNum == 3 ) && "only 2 and 3 are allowed for colNum"samplememoryBarrierAtomicCounteratomicMaxatomicExchangeatomicCounterIncrementgl_FrontFacinggl_SampleIDOESsubpassMS^UTEXTURE1DARRAYcontinue statement only allowed in loop statements#undef must have a symbolmax #if nesting depth exceededunexpected tokens following an #if or #elif."(" expected after 'invariant' keywordGL_AMD_flat_varying pragma syntax is incorrect0uTried to define a duplicate symbolgl_GlobalOffsetgl_SubgroupMaxSize0 && "unsupported shader intrinsic version"(srcME->getSize() == 4) && (srcOperand->isUint()) && (srcTy == codeGenHelper->getInt32Ty()) && "Value must be a unsigned vec4 of 32 bit integer type"startIndex < endIndex && "Invalid binary index!"OpStringOpTypeEventOpTypeDeviceEventOpSpecConstantCompositeOpCompositeConstructOpQuantizeToF16OpConvertPtrToUOpIMulOpSModOpIsNormalOpFOrdLessThanEqualOpSelectionMergeOpKillOpGroupCommitWritePipeOpGetKernelPreferredWorkGroupSizeMultipleOpSizeOf((symbol)->getFlags().bitfields.isRootUniform) && "mUniforms list can only have default root uniform"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/opengl/ESXLinker.cppNeed valid shader object handlearrayDimDV && arrayStridesDV && "TF Metadata is not set correctly!"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/raytracing/LiveValues.cppvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/common/raytracing/Reducibility.cppfuncGetBaseShaderID && "getBaseShaderID() must be present"runtimeDataframe.sizecommitHitrcflagrd.lbasecurTableIndexfuncGetRayId && "getRayId() should have been inserted in init()"thrdid != NULLexecuting.rays.ptrnext.stateIdori.xtermInst && "the parent BB should have a terminator" (ijPerspCentroid)[A4X_CLIPCULL_INFO] (Ver [A3X_CLIPPLANE_INFO] (Ver [A3X_CLIPPLANES] (Ver [ADRENO_GS_OUTPUTS] (Ver needsFaceness: [ADRENO_CS_DESC] (Ver numRenderTargets: destMask: constMulTexEnable: [ADRENO_PATCHED_DYNAMIC_ASTC_TEXTURE][[ADRENO_DEVICE_TYPED_ALLOCATION] (Ver dynamicCBCacheEntries[atomicCounterInfo: isPatch: constColorValX: constColorOutputEntries[vertexAttrSizePerWorkgroup: [ADRENO_SCREEN_COORD_TEX_USAGE] (Ver screenCoordTexUsages[ != 0x.minVGSMem.textureUsedInTexelFetchMask[A4X_HS_MERGED_SHADER_DESC].domainType[A4X_PS_INPUTS][A4X_GLUECODE_DESC].samplerID.ConstSwizzleZ.ConstSwizzleW.initialIJWriteDis.patchedTextureSlotIndex.hwBindlessGroup.numBindlessRanges.numInputTargets[ADRENO_DEVICE_TYPED_ALLOCATION].primSize[GL_SYMBOL_FLAGS].hasLocationQualifier.isActive.isRootUniform(non-null).advancedBlendLayoutMask.shaderEntryPoint[ADRENO_SHADER_COLLECTION_SHADER_LIST][ADRENO_SCREEN_COORD_TEX_USAGE_INFO]CSBINNING Unimplemented shader type dumping supportTessControlShader - NOPs : %8d,%8d (rpt), ratio %5.2f - Flat shading : %8d,%8d (rpt), ratio %5.2f preamble_alltexld - img_bdl : %8d - bindlessi : %8d,%8d (rpt), ratio %5.2f - pipr : %8d,%8d (rpt), ratio %5.2f - stgbsize : %8d eolm_pos - Const Registers : %8d const_reg_cbmapping - uGPR Registers : %8d - Wave size mode : %8d tex.ssdtex.preamble_fsammem.ldibmem.stgen_rptmem.ldib_b_c_rptmem.preamble_bindlessumem.preamble_bindlessu_rptOverall register footprint per shader instanceSetInstrumentationShaderDumpFlagsQGLCReturnCodeReservedLocationsCountSpecializationSizeLLVMDebugTypeEnableFullpConstMulTextureEnableMultiChannelUAVLoadsEnableRTAndVPIncrFlagsEnableASTCPatchingTextureFormatForSSBOEnableEmulatedROImageEnableDynamicWaveSize="numDescriptorRangesshaderVisibilityDescriptorTableauxBindlessIndex="location="Unable to parse EnableInstrumentation value 'Unable to parse EnableComparableLog value 'Unrecognized QCC Context option 'DxxUnable to parse ReservedLocationsBufferRef value 'Unable to parse ReservedLocationSize value 'Unable to parse InputAttachmentInfoBufferRef value 'Unable to parse EntryPointName value 'Unable to parse EnableMultiChannelUAVLoads value 'Unable to parse DisableArrayRounding value 'Unable to parse TFDataSize value 'Unable to parse EnableMul2Div2FloatDestMod value 'Unrecognized QCC Compile option ' EnableBindlessCBuffer (false): enable bindless constant buffer PrevStageGLIRShader (__null): GL IR Shader of previous shader stage GenerateSPIRV (false): Generate SPIR-V for offline Vulkan compilation ForceSingleWaveSize (false): True: Use single wave size, overriding compiler determined value for a5x single pool GLViewMask (0): Hard-coded view mask for emulating multi-view EnableUseTextureForROImage (false): (a6x+) For Vulkan, enable using ISAM for read-only storage images. EnableBGPR (false): (a740+) Enable BGPR AllCompilerOptions0 (0): Encoding of a subset of compiler options specified in the interface ValidateASICIDOption (false): Validate ASICID option SOGESize (0): size of one streamout entry ABTexDescriptorBase (0): Vulkan Advanced Blending Texture Descriptor Base ShaderCollectionCurrently available ClientIDs are: A509 A510 A650 Null QGPUMetaData. pOutputSymbolsEntries + pOutputSymbolsEntryDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"Major version mismatch for structure Data describing sterero rendering info. Version 1.0: Added useHWStereoRendering: true if shader uses HW stereo rendering Added useMultiPositionOutput: true if shader output multiple position when use HW stereo rendering Added numViews: number of views. Added positionSymbols Version 1.1: Added numPositionOutputs: number of position outputs. Version 1.2: Added needsViewID: true when the shader requires a ViewID. Added viewIDRegID: Scalar Reg ID assigned to View ID. Version 1.3: Added viewIDConstRamLocation: Constant RAM location assigned to View ID. Version 1.4: remove viewMask Version 1.2: Added renderTargetIndexIncr: request HW to add ViewID to output renderTargetIndex. Added viewportIndexIncr: request HW to add ViewID to output viewportIndex. This gives information about a device memory allocation made during compilation. Version 1.0: Added allocationHandle Added allocationSize Added allocationType Contains information about which texturess are accessed by screend coordinates. DX only. Version 1.0: Added numScreenCoordTexUsages: num of textures Added screenCoordTexUsages ERROR: Improperly formatted data not sent to DebugString callback Leave context failed (id=Shader Type mismatch, using wrong API to load object data? grave-accentout of memoryBitWidth && "bitwidth too small"0x -' value invalid for uint argument!= DW_TAG_shared_typeDW_ATE_unsignedDW_LANG_ObjC_plus_plusle32 ] to sub preds = external , section "dllimport returns_twice _shader_ Ty != 0 && "Invalid indices for GEP!"Zero width native integer type in datalayout stringpass-remarks-analysis' in -pass-remarks: pencl.kernel.argument.samplert.fake.usellvm.arm.f32.to.f16llvm.arm.neon.vld3lanellvm.arm.neon.vrecpsllvm.arm.neon.vshiftsllvm.arm.strexdllvm.atomic.load.nandllvm.eh.sjlj.functioncontextllvm.hexagon.A2.maxllvm.hexagon.A2.vaddhsllvm.hexagon.A4.bitsplitillvm.hexagon.A4.cmpbgtullvm.hexagon.A4.vrmaxhllvm.hexagon.C2.cmpeqillvm.hexagon.F2.dffixuprllvm.hexagon.F2.dfmaxllvm.hexagon.M2.mmacuhs.rs0llvm.hexagon.M2.mmaculs.rs0llvm.hexagon.M2.mpy.acc.ll.s0llvm.hexagon.M2.mpy.hl.s1llvm.hexagon.M2.mpy.nac.ll.s1llvm.hexagon.M2.mpy.rnd.hl.s1llvm.hexagon.M2.mpy.sat.rnd.ll.s1llvm.hexagon.M2.mpyu.nac.ll.s1llvm.hexagon.M2.vdmacs.s0llvm.hexagon.M2.vmac2esllvm.hexagon.M4.and.andnllvm.hexagon.M4.vrmpyoh.acc.s1llvm.hexagon.S2.asl.i.r.accllvm.hexagon.S2.asl.i.r.satllvm.hexagon.S2.lsr.r.r.orllvm.infinite.loopllvm.log2llvm.memsetllvm.opencl.get.image.channel.data.type1bllvm.opencl.get.image.channel.order1bllvm.opencl.get.image.channel.order2allvm.opencl.get.image.width3llvm.opencl.read.image1u.fllvm.powllvm.ppc.altivec.dstllvm.ppc.altivec.vcmpgtsh.pllvm.ppc.altivec.vminubllvm.ppc.altivec.vminuhllvm.ppc.altivec.vmsumshmllvm.qgpu.atomic64.imax.oobllvm.qgpu.atomic64.xor.oobllvm.qgpu.atomic.imin.oobllvm.qgpu.calculateBlockInfollvm.qgpu.eval.pulledllvm.qgpu.fcombine27llvm.qgpu.fcreate.map22llvm.qgpu.fcreate.map27llvm.qgpu.fcreate.map38llvm.qgpu.get.attr.at.vertexllvm.qgpu.get.rt.stbl.baseaddr.callablellvm.qgpu.get.sym.loc.by.enumllvm.qgpu.icombine21llvm.qgpu.icombine25llvm.qgpu.icombine29llvm.qgpu.icombine42llvm.qgpu.icombine52llvm.qgpu.icombine54llvm.qgpu.icreate.map13llvm.qgpu.icreate.map32llvm.qgpu.icreate.map39llvm.qgpu.icreate.map7llvm.qgpu.lastusellvm.qgpu.pre.atomic.rmw.syncllvm.qgpu.resetAllGPRsllvm.qgpu.set.mesh.primitives.vertices.countsllvm.qgpu.stgallvm.qgpu.subgroup.inclusive.floatllvm.qgpu.unroll.endllvm.spu.si.allvm.spu.si.cgllvm.spu.si.cgtbillvm.x86.3dnow.pmulhrwllvm.x86.aesni.aesencllvm.x86.avx2.permdllvm.x86.avx2.pmovzxdqllvm.x86.avx.maskload.psllvm.x86.avx.max.pd.256llvm.x86.avx.ptestc.256llvm.x86.avx.vtestc.pd.256llvm.x86.mmx.porllvm.x86.mmx.punpcklbwllvm.x86.sse2.cmp.pdllvm.x86.sse2.comige.sdllvm.x86.sse2.cvtsd2ssllvm.x86.sse2.cvttsd2sillvm.x86.sse2.max.sdllvm.x86.sse2.pavg.bllvm.x86.sse2.psll.dllvm.x86.sse2.sub.sdllvm.x86.sse41.dppsllvm.x86.sse41.extractpsllvm.x86.sse41.pextrqllvm.x86.sse42.crc32.32.8llvm.x86.sse42.pcmpistriz128llvm.x86.sse.cvtss2sillvm.x86.ssse3.phadd.d.128llvm.x86.ssse3.phsub.swllvm.x86.xop.vfrcz.ssllvm.x86.xop.vpcomequdllvm.x86.xop.vpcomgeqllvm.x86.xop.vpcomgeubllvm.x86.xop.vpshabllvm.xcore.checkeventllvm.xcore.gettsllvm.xcore.testwctvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/VMCore/Instruction.cppprofprint pass name before it is executedprint-before-allvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/VMCore/Type.cppptrInvalid struct return type!Basic Block does not have terminator!Operand is nullInvoke operand is PHI node with bad incoming-BBFPToSI source and dest must both be vector or scalarIntToPtr result must be a pointerIntrinsic functions should never be defined!is_zero_undef argument of bit counting intrinsics must be a constant intllvm.invariant.end parameter #2 must be a constant integerOverloaded intrinsic has incorrect suffix: 'LandingPadInst needs at least one clause or to be a cleanup.Personality function is not constant!.strtab.code64no_type\tDon't know how to emit this value..debug_frame, @exceptCompact Unwind Encoding: 0xDW_CFA_def_cfaTLSLDMha.tdata.rodata.cst16.debug_ranges.debug_macinfonoteS_INTERPOSINGS_DTRACE_DOFS_ATTR_LIVE_SUPPORTIf present, PushMachFrame must be the first UOPmemsettruncf Mod/Ref Analysis Counter Summary: [volatile] Pointers: MS label="dot-domNumber of Unreachable instsNumber of FPToSI insts ScalarUnusual: Returning alloca value Load/store instructions: Print MemDeps of functionno-aaprofile-estimatorEdge BB && "Missing BB in dependence edge".preheadervendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/LoopUnrollRuntime.cppabortunwindJmpBufenableUAInSimplifyCFGmagicptr.critedgeTI && "getTerminator() returned null"PropagatePrecisefalse && "unexpected instruction type in GV replacement"op==Instruction::GetElementPtr && "GEP const expr not used by the const expr"Only generate aligned loads and storesSLPphitmpStrippedDest && "stripPointerCasts() returned nullptr"vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp(firstOp >= Instruction::CastOpsBegin) && (firstOp < Instruction::CastOpsEnd)is_ray_tracing_kernelenable-iv-rewriteDst && "Dst is NULL".termcondlsr.chaincomplete-loop-def-unroll-treshqgpu.tex.sam.in.loop.unroll.if.possiblellvm.loopunroll.enableMD->getNumOperands() == 2 && "Unroll hint metadata should have two operands."Max loop size to unswitchMemCpy OptimizationPhidisable-sel-convir-taildup-heur-min-num-callsSplit GEPs to a variadic base and a constant offset for better CSEagg-antidep-debugmodException handling preparation" [ shape=box ] unsupported GC: ifcvt-fn-starti < N && "Unsafe intervals"disable-rematerialization!empty() && "Call to beginIndex() on empty interval."FI >= 0 && "Cannot hold a negative frame index."livevars NumNops:VECTORavoid-speculationStandard converging scheduler.Live range: Block ends at Non-PHI, non-early clobber def must be at a register slot Valno #vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/include/llvm/CodeGen/LiveVariables.hstrong-phi-elimDisable Loop Strength Reduction PassAfter PrologEpilogCodeInserterAfter PostRASchedulerNumber of extension results reusedTargetRegisterInfo::isVirtualRegister(Reg) && "Can only enqueue virtual registers"SA->getUseBlocks().size() == 1 && "Not a local interval"Lower bound for a buffer to be considered for stack protectionCallStackCheckFailBlkNumber of identity moves eliminated after rewritinglivedebugvars ExpandedFloatssched-heur-min-int-insts-ratiodisable-sched-vrcycleCannot generate unaligned atomic storeBasicBlockfcopysignsaddofp_to_uint(samplerOpd) == nullptrterminator && "no null terminator."ifTrueopencl_kernel_argument_slotDisable simple pipeline entry points) llclib overheadqgpu.force.ray.tracingSupports DX11 specific featuresHas dedicated CL work dim regNOREGHR4_bHR11_cHR20_bHR21_dHR22_dHR38_cHR38_dHR42_dHW_AL2HW_SPIR4IR68IR74IR96IR103R4_cR4_dR5_bR9_dR21_aR28_bR43_aSR4_dUAV53UR3_bUR3_d.Lmccodeemitter, x[, p[getParent() == MF && "Ensure we only visit curent function"false && "invalid cmp opcode"0 && "Cannot set length for the instruction" rpt= rel-addr-range=Allow large combine_extract_basicblock != NULL && "basicblock must not be NULL"Enforce early preamble ON without any heuristics. Used for testing. Create Preamble operands in Oxili BC instructionspotential.unbound.resourceDon't generate NOPs in between instructions to guarantee latencyAttrInsertion && "Fail to create AttrInsertion pass"' needs Spilling but compile with simple pipeline _CL_local_mem_base0 && "Unsupported addrspacecast. Only to or from generic is allowed"0 && "CBase -1 reached in LoadFromMetadata"_CL_divided_group_idisHalfReg(op0Reg) && isHalfReg(op1Reg) && isHalfReg(op2Reg) && "sad instruction is in a wrong format"V_OpdTexAndSamID && "Instruction for TexSrc2 does not have TexSamIDVecIdx operand"(LIDConstValue < 128) && "LaneID only supported from 0 to 127"DstTy->isStructTy() && "Wrong Overflow Sub type"II && "bad branch intrinsic"(MemLayer >> 1) == 0 && "Unexpect global memory layer 0 for SOC or 1 for GPU"MemOrder && "Constant memory order and scope expected in pre.atomic.rmw intrinsic"false && "QGPUHandleAtomicFetchOpIntrinsic(I) should be handled by CL builtins now"ImgCoordVal && "Coordinate is null"IsFloatCoord && "LST_SAMPLER_GRADIENT is only for float coordinate".texhrpahl2.0stksatomic.b.cmpxchg!QTM.getCompileOptions().EnableBGPR && "no pgpr for OCL!"alu3.DstConvert == 1 && "Destination convert mask must be set"The data type of src0 must be signed half integer s16 for MOVA0 && "Unsupported Constant found"ReqdMinFootPrint <= 48 && "Max concurrent subgroups value is too low for this arch and wavesize combination"Disable the instruction validation is out of range. The value must must be >= 0 and < Source registers have different precisions.DstAndSrcRegPrecisionMismatchError: class is undefined.# of constant registers must be < : Out of range. It must be >= END instruction is not the last instruction of basicblockInteger ImmediateSMOD.NEGred,label="IID != Intrinsic::not_intrinsic && "Invalid combine intrinsic"BB != nullptr && "No valid BB"disable-vectorize-sampler-copysAddrOperand && "AddrOperand is Null"min-cse-num!MOVCVTInstrInfo::isCVTInstr(MI) && "Scalar unit WA not implemented for CVT instructions"!(QTM->getCompileOptions().EnableEarlyPreamble && QTM->isInPreamble(MBB)) && "relative addressing fixup should never happen in early preamble"_hi_1newVal && "Emulated vector NULL for subgroup arithmetic intrinsic"!opdTy->isIntegerTy(64) && (opdTy->getScalarType() == opdTy)Enable stress test for GRABBOpnd.isMBB() && "Unexpected PHI operand"SrcIdx != ~0u && "could not locate the src pos"Src->NumInEdges <= 1 && "uncertain writes"!TargetRegisterInfo::isPhysicalRegister(Reg) && "Virtual register only"Slots away a non-foldable use must be to be considered for castingPromote phis(rpt)out of dynamic memory in yy_create_buffer()LDC: LDC length is out of range. Allowed range for length is 2 bits, |1 - 4|.the source0 should use g with src0 operand. Usage: g[r0.x]STIB: src0 not allowed with a6x LDIB: packed mode expected for A7x+ LDIB: for src baseid 6/7 reserved for a6x and aboveLDIB.A: LDIB.A length is out of range. Allowed range is 4 .LoadStore: for Getfiberid instruction dst should be GPR LoadStore: for stsc instruction src1 should be IMM ALU2 CAT16: DST can be 32 bit only.MOVS: Destination of getcycle must be a full uGPRTexture: broadcast.active src0 type should be a GPRfloat32dcl_attributes_uav can be byte or pixelOUTPUT_TRIANGLE_CCWdcl_patch_const_size_in_bytes is allowed with HS onlyCOVU8S32INSTRCOVU16S16INSTRCOVF32S32INSTRJUMPINSTRLOADPU16INSTRSTGU32INSTRSTXU16INSTRSTXAF32INSTRATOMADDLU32INSTRLOADGBAT3DU32INSTRLOADGBAT3DF32INSTRSTGBUT3DINSTRICINVINSTRVGS_CTRL_SATOMADDGSOCS32INSTRATOMSUBGENS32INSTRATOMINCGSOCS32INSTRATOMMAXGGPUS32INSTRATOMXORGGPUS32INSTRATOMBAADDGU321D1LINSTRATOMBSUBGU32INSTRATOMBASUBGU321DINSTRATOMBAMINGU322DINSTRATOMBAANDGS323D1LINSTRATOMBAORGS32INSTRATOMBXORGU322D1LINSTRATOMBAXORGS323DINSTRATOMBXCHGGU643DINSTRATOMBXCHGGU641D1LINSTRATOMBXCHGGF323D1LINSTRATOMBINCGU32INSTRATOMBAINCGU322DINSTRATOMBAINCLNGS323D1LINSTRATOMBAINCRGGU32INSTRATOMBADECGS321DINSTRATOMBADECRGGU323D1LINSTRINST_REPEATCMPVSINSTRMOVA0INSTRMOVA0RINSTRMOVS32INSTRDSYTOKENATOMINCRGGU32INSTRRESFMT1DTINSTRANDG16INSTRRSQHINSTRSWZF16INSTRMOVSU32INSTRMOVSU16S16INSTRLDIBUNTYPEDU323DINSTRLDIBUNTYPEDS161DTINSTRLDIBUNTYPEDU163DRCKINSTRSTIBUNTYPEDU163DINSTRLDIBBLKLS163DINSTRLOADLBLKF32INSTRSTIBF161DTINSTRLDIBS161DTINSTRSTIBBLKS163DINSTRSCTF32U32INSTRENDLSINSTRGETFIBERIDU32INSTRMACROSAD_ENABLESHFLUPW4U32INSTRSHFLRUPW8U32INSTRDCL_LOCALDECLARE_MAX_OUTDECLARE_OUT_CP_COUNTDCL_UGPR_INDEX_WGIDDECLARE_CL_GPU_EX_LOCK$acceptSUBINSTRSWZINSTRQUADSHFL2SRCINSTRDCLICBVAL2DCLVAL22MOV/COV: MOVS with optional Lane ID can have src1 as immediate value in range 0-127textureUsageADRENO_GS_PER_STREAM_OUTPUTSADRENO_BINDLESS_MAPPING_DATAADRENO_OBJ_DATAADRENO_PATCHED_GATHER_TEXTURESADRENO_VSDS_PSO_PRIMITIVE_SIZEADRENO_DYNAMIC_CBCACHEADRENO_BINDLESSBASE_USAGE_INFOADRENO_SHADER_COLLECTION_SHADER_LISTclipCullInfoQCOM_SPARSE_TEXTURE_FOVEATEDdoProgramBinaryEnd of SpirvRGBA32I symbolID = %d unsized,symLists && "Assert Index:[11] symbolTables is Null"false && "Assert Index:[41] unexpected symbol type"Tessellation Factor Data Base Pointer (32-bit)An array of fragment sizes for foveationmaxVirtualReg < MAX_VARYING_COUNT && "Assert Index:[30]"packedGV && "Assert Index:[39] packedGV should not be Null here"enableSGPRenableSharedConstantconstantRAMModeenableVKPreRotationPatchingenableRelaxedVectorMatchingllvm.cos.f16llvm.qgpu.samplergq.v4f16.v10f16.v4f16llvm.qgpu.icombine3.i16llvm.qgpu.atomic.xchg.oob.i32offsetValdxOP && "Gradient operand dPdx is missing!".$typeretType && "retType is NULL!"raytracing.accelerationstructureget_intersection_primitive_indexget_intersection_barycentricsget_world_ray_directiongetAccelStructPtrGV && "GV is Null"viewIDGVPtr && "viewGV ptr is Null"false && "Can't find builtin input size!"imageIndex < unrollSize && "image index is bigger than arraySize"func && "No Main Function Exist"force-4vec4-alignedbyteOffset != NULLrelPrimIDTessLevelOutersamplerCubeArrayShadowutexture3DtextureExternalOESbufferfalse && "setGlobalComputeInfo called on invalid object"callee->arg_begin()->getType()->isPointerTy() && (callee->arg_begin()->getType()->getPointerElementType()->isStructTy() || callee->arg_begin()->getType()->getPointerElementType()->isArrayTy())meSize <= srcMe->getSize() && "invalid meSize!"baseNode && "left node not found"depth <= mOPStack.size()uimg2dmsareflectimageStore.glsl<<=ifndefcan't modify gl_DrawIDARBcan't modify gl_MaxGeometryInputComponentsvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/opengl/gl_parser/MachineIndependent/ParseHelper.cppcannot convert a voidcannot convert parameter %d from '%s' to '%s'Block layout qualifiers cannot be used on member declarationVarying IO struct var creation failedsamplerVar && "can not create pseudo sampler array variable"newNode != NULLgl_PerVertex declared in wrong shadergl_CullDistance array size is wrong!Invalid qualifier orderlocal group size value should be same if declared more than oncegl_WorkGroupSize was used before layout declaration!'constructor' : assigning non-constant to %sConvert Uint to FloatUsub with borrowTexture2DShadowProjGradOffsetBad promotion typeInvalid binary operator for constant foldinginterpolateAtCentroidimageAtomicAddatomicAndatomicXorinput array without size supported for Tessellation shaders onlyBinding is only allow for sampler/image/atomic and interface blockinternal preprocessor errormalformed preprocessor directiveSTDGL pragma syntax is incorrectstructTy && "structTy is NULL!"$RT_(sc == StorageClassCallableDataKHR || sc == StorageClassIncomingCallableDataKHR) && "Incompatible storage class" is not permitted in a (argVal && argVal->getType()->isVectorTy()) && "not supported yet!!!"0 && "wrong type"gl_EnqueuedWorkgroupSizeOpStoreOpImageSampleProjDrefImplicitLodOpImageQuerySamplesOpLogicalOrOpFOrdGreaterThanOpEmitVertexOpAtomicISubOpAtomicSMaxOpAtomicUMaxOpGroupNonUniformLogicalOrOpRayQueryGetIntersectionFrontFaceKHROpRayQueryGetRayTMinKHROpExecuteCallableKHROpTerminateInvocationAdding transform feedback entry: $qgpu.stable.const.raygenLoadFromPLCDstack.ptr0 && "Base parameter type"num.rays.startedrd.lbaseuintsfunc && "populateRays() should have been inserted in init()"currStackFrameBase && "allocInRayStack() implies its parent function has a call to m_currStackFrameBase"cur.tbl.idx( isa(LI->getOperand(0)) || isCallToStackPtr(LI->getOperand(0)) ) && "we expect an 'alloca; load' sequence"0 && "unsupported shader"chip id not specified! (SharedConstant) (SampleA) (TessellationEval)metadataStaticSize: [SMALL_BITMASK] (Ver ]: dynamicallyIndexesConstantBuffers: fullyMappedSlots: needsPrimitiveAttributeBuffer: viewIDVirtualRegID: packedFragcoordXYRegID: depthStencilInputAttachmentRead: [ADRENO_PATCHED_R24_UNORM_TEXTURE] (Ver bindlessAccelerationStructureSupport: innerCoverageRegID: numInputTargets: constantRAMMode: readBindlessNonBufferUAV: bufferOffset: ([GL_NAMED_CONST]*) surfFormat: [ADRENO_MS_VSPASSTHRU_LIST] (Ver [ADRENO_SHADER_COLLECTION_SUBSTATE_INFO][.numFullScalarRegsUsed.fetchFrameBuffer.sourceSlot.virtualRegAndComps.viewportArrayIndexVPCIndex.logString.TexSwizzleZ.constSlotID.sourceTextureSlotIndex.refValue[ADRENO_OBJ_DATA][GL_SYMBOL_INFO_ATOMIC_COUNTER].numScalarRegisters.textureSlotForIntGather.renderingDescriptorGroups.needsMeshPrimitiveID.usedBases.registerUsagePerFiberUnexpected descriptor type FragmentShaderpost_nop - rck : %8d max_number_of_waves_usptpnop_rpttex.immofftex.msconvmem.stpmem.emit_rptmem.preamble_ldca_rptmem.preamble_bindlessi_rptEnableBindlessCBufferInputAttachmentSRefShaderNameEnableSGPREnableSingleCommandStreamBinningEnableEndOfGlobalMemEnableR24UnormPatchingXXXEnable10Level9SupportEnableVPCDecouplingMaxRecursionDepthReallocateSystemMemoryCallbackGetRayTracingHWShadersUCHETrapBaseHibufferType A3x A6x Unable to parse DisableScheduler value 'Unable to parse EnableAlphaToCoverage value 'Unable to parse SimulateVariableRateShading value 'Unable to parse EnableDispatchBaseForWorkgroupID value 'Unable to parse ForceHighpTrigFunctions value 'Unable to parse VulkanPatchCPCount value ' EnableBindlessUAV (false): enable bindless UAV InputAttachmentInfoCount (0): number of input attachments ASICCHIPID (0): Which chip ID within the family to compile for EnableSGPR (false): (a5x+) enable shared GPR. ForceDoubleWaveSize (false): True: Use double wave size, overriding compiler determined value for a5x single pool EnableA6xColorSpaceConversion (false): (a6x+) enable color space conversion(RGB<->YUV) in RB EnableWorkGroupLikeVSHS (false): Enable Workgroup Like VS-HS NumViews (0): Number of views for multi-view BGEDataBufRef (__null): Location of Array of bind group elements DisableReuseSimpleVSAsBS (false): Disable reusing the render VS for the binning VS EnableDeviceIndexAsViewIndex (false): [Vulkan1.1] deviceIndex gets ViewIndex value ForceHighpTexCoord (false): Force shader texture coordinate variables to use high precision EnableBindlessSampler (false): allow bindless sampler usage EnableDP4ACCWithSignedWeights (): Enable signed weights (src1) in dp4acc instruction QGLCLinkA430A605pAllocPtr + pAllocDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"metadata section not found. Collision found in input symbol data, error in compiler-generated metadata. pStaticEntriesPtr + pStaticEntriesDesc->m_ElementSize * i && "memcpy dest pointer is NULL!"pEmulationMappingsPtr + pEmulationMappingsDesc->m_ElementSize * i && "memcpy dest pointer is NULL!" Defines a statically sized bitfield used to identify usage masks. This is intended for values that will stay small. Version 1.0: Added word The shader handles allocated and their meaning to the shader. Version 1.0: Added hwShader: The shader bytecode to execute. Added icb: The shader-provided immediate constant buffer (for access to large literal arrays accessed in the shader). Added dcb: The compiler-defined internal constant buffer used only to populate constant registers (for defining literals like 1.5 or 4922222. Information for patching a single-channel full-precision texture read immediately followed by a long sync. This scenario shows up in the manhattan shader, and in this case we can get better throughput by reimplementing this using a two-channel half-precision texture reads. The driver will call the patching interface to replace a set of nops embedded in the original shader which will combine the half results to generate the full precision result. Version 1.0: Added instructionOffset: The offset of a texture instruction in the bytecode. Added textureIndex: The index of the texture read in the instruction. Added samplerIndex: The index of the sampler read in the instruction. Information about all bindless resources used in a shader or bindless group layout. Version 1.0: Added numBindlessTypes: how many bindless types are declared in the bindless group layout Added bindlessTypes: list of bindless types Added bindlessTextureSupport: True if bindless textures were enabled by the driver and compiler. Added bindlessSamplerSupport: True if bindless samplers were enabled by the driver and compiler. Added bindlessCBufferSupport: True if bindless cbuffers were enabled by the driver and compiler. Added bindlessVertexSupport: True if bindless vertex buffers were enabled by the driver and compiler. Added bindlessRWBufferSupport: True if bindless r/w buffers were enabled by the driver and compiler. Added bindlessImageSupport: True if bindless images were enabled by the driver and compiler. Version 1.1: Added bindlessAccelerationStructureSupport: True if bindless acceleration structure were enabled by the driver and compiler. Data describing debug info related to shader. Version 1.0: Added HWCodeCRC: HW Code CRC. view-cfgView postdominance tree of functionNumber of URem insts ScalarNumber of Store insts ScalarNumber of FPTrunc instsNumber of AddrSpaceCast instsUnusual: Address one pointer dereferenceUnusual: noalias argument aliases another argumentLoop at depth containing: profile-estimator-loop-weightview-regions-only}< smax scalar-evolutionqglnext_cb_locationsUniformity analysisBasic CallGraph Constructioncgscc-passmgrTy && "Type to getValueType may not be null!"or.condoMiscPropagate Invariantvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Utils/ReplaceGlobalLoadStorePass.cppII != ai->getParent()->end() && "entry block has no instructions after the last alloca instruction?"ReplaceGlobalLoadStoreDon't try to vectorize getelementptr instructionsslp-vectorize-horvalOp && "Val Operand is NULL!"CI2 && "CI2 is NULL!"bb36-vectorize-max-cycle-check-pairsbb36-vectorize-no-castsbb36-vectorize-no-mem-op-boostvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/InstCombine/InstructionCombining.cppspirv_preserve_nan(I->getOpcode() == Instruction::FAdd || I->getOpcode() == Instruction::FSub) && "Expect add/sub"(A && B) && "A or B is a null ptr"Op0 && "The first operator for multiplicatin can not be null ".swappedvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Transforms/Scalar/ADCE.cppNumber of memory access targets propagatedDead Code Eliminationdisable-licm-promotionInnerLoopLatchPred && "InnerLoopLatchPred is NULL"lsr-icmp-zeroThe cut-off point for automatic loop unrollingUse this unroll count for all loops including those with unroll_count pragma values, for testing purposesqglnext_enable_bgprDemote all values to stack slotsDst && "Dst is NULL in RewriteMemIntrinUserOfAlloca"Debug control for aggressive anti-dep breakerNumber of resume calls loweredExpand ISel Pseudo-instructions bytes) NumLongSyncs:Number of uncondittional branchesPotential frequency of taking conditional branches, not tracking livenessopt:RegConstRegImgMachineLICM should avoid speculationNumber of high latency instructions hoistedswp-max-miiMBB exits via unconditional branch but doesn't have exactly one CFG successor!MBB exits via unconditional branch but the branch isn't a terminator instruction!MBB exits via conditional branch/branch but doesn't contain any instructions!Multiple virtual register defs in SSA formValno must be live through the block. No instruction at def indexBasic block starts at disable-branch-foldNumber of split global live rangesTargetRegisterInfo::isPhysicalRegister(HintPair.second)PBQP Register AllocatorVerify machine instrs before and after register coalescingNumber of register classes inflatedgc_frame.nextgc_map.shrink-wrapjbuf_fp_gepSuppress slot sharing during stack coloringStack Slot Coloringcombiner-alias-analysisDisable use of clusters during schedulingdisable-choose-between-burr-and-hybrid-sched-heursched-heur-long-latency-insts-ratiodisable-sched-cyclesAtomicFencesetolesetfalseENable FastISel for OpenCLcolor=blue,style=dashed__mulosi4__fixunssfsi__fixunssfti__sync_lock_test_and_set_8__sync_fetch_and_add_4__sync_fetch_and_nand_1disable-debug-info-printdata_begin__Invalid ENTRY recordInvalid type forward reference in TYPE_BLOCKError at end of use-list table blockInvalid MODULE_CODE_GCNAME recordInvalid MODULE_CODE_GLOBALVAR recordInvalid CMPXCHG recordinlinehint-thresholddisable-extra-passesvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/IRUpdater/LLVMIRUpdater.cppvendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/llclib/llclib.cppllc: invalid optimization level. - compiling with default footprint! GenericASSVMSupportsShare4ModeHR2_aHR4_cHR6_bHR26_dHR40_bIR22IR65IR93R0_bR0_cR13_dR19_bR25_aR25_cR35_bR46_dSAM26SR0_bUAV8UAV35FullFRChcs8_32QGPU::xorQGPU::sinQGPUInstrInfo::isInterpolationInstr(MI->getOpcode()) && "EI attached to non interp instr"!Cond.empty()false && "Inconsistent CFG"Bad $ operand number in inline asm string: 'vendor/qcom/proprietary/graphics/adreno200/shadercompiler/llvm/lib/Target/Oxili/QGPURegisterInfo.cppfalse && "Invalid scalarization of vector operand"Scalarize Oxili BC instructionsmodule && symbolInfo && "Null arguments in addPreambleSymbolMetadata !"Enforce preamble ON without any heuristics. Used for testing. EleTy->isIntegerTy() && "Invalid Type"digraph preambleBegin != NULL && preambleEnd != NULLIndexOp && BindlessOffsetOp && "LDC needs these two operands"false && "Unsupported integer type"false && "wrong NumRetEles !"false && "Unable to index non-hardwired value with large offset."0 && "cannot infer Register class from global"_CL_globalatomic_WaveSizeMinusOne!"Image offset was of invalid type."CIsPerspective && "isPerspective needs to be immediate int"Arg && "Arg can't be NULL"DstTy->getScalarType()->isHalfTy() && "RBI only allows half destination"NumExt > 0 && "NumExt should be more than 0"defArgIsFloatCoord && "LST_SAMPLER_BIAS is only for float coordinate".macroSAD.allsr???sel.f16mad.m32.f16f16f32mova.rgatsamlstpatomic.andshfl.rdownatomic.b.inc.rglock__qcom_internal_yield_restoreqgpu.raypipeline.dataKArg->ArgIdx < resArgSlotIDs.size()Integer immediate operand is not allowed.MIOpcodeUndefinedError: NumConstRegsError: , Wrong mask: M[a void-sam-in-lock-regionfalse && "Unexpected pattern"Enable macro expansion to wavemath around atomic instructionsto reduce the number of fibers affecting lock-trafficfalse && "No GRegInfo entry"false && "wrong value for L, H "VectorBegin == -1 && "VectorBegin/VectorEnd is not valid for constant registers"false && "unhandled src data type for mov instruction"false && "unrecognized logical rr opcode"MI.getParent() == &MBB && "Each instruction's parent must be the current basic block"neg_hi_orgllvm.qgpu.global.vec.get.reg.v2i32.p0i32false && "Loop info is not correctly constructed"MBB->canFallThrough() && MBB->isSuccessor(FallThrough) && "Invalid control flow"LI_Cur->getStackFrameIdx() == -1 && "stack location is already assigned!"LI_Representative && "No live interval aliased."false && "No live interval for live-in variable?"Changed && "did not change anything"!XG.hasAnyEdges() && "resolution failure"LI && "interval not found"PReg != 0 && "No physical register allocated"UI->isPHI() && "Expecting PHI->PHI" , size: QGPU Global Register Allocatoruppf-max-ugprsLastuGPRVreg + 1 == uGPRVReg && "failed to allocate adjacent vregs"STIB: for src mode0/1/2, baseid ignored for a6x and above LDIB: Out of Range Offset with ldib instruction. Allowed Range is 8bits, |0 - 255|.LDIBBLK(L|G|C): is supported only from A6x and above LDIBBLK(L|C): Source2 should always be Immediate/sGPR Value LDIBBLK(L|C): Only src mode0/1/4/5 modes are supportedLDIBBLK(L|C): for src mode 3/7 reserved for a6x and aboveLDIB.A: should not be used from a6x LoadStore: GetGPRBase instruction not supported in a6x and below TEXTURE: src1 should be a GPR/sGPR when .clp/.l option is used.Texture: Invalid quad shuffle instr opcodeTexture: img instr is allowed only in a6x and aboveA8XUINT32samplerPATCH28POINTLISTTHREADIDINGROUPFLATTENEDALL_CONTROL_POINTS_SIZETEX2DMSA' COVF16S32INSTRLOADGENS8INSTRLOADTHRCCHEAU8INSTRLOADTHRU16INSTRLOADXS16INSTRLOADGBAU1DU32INSTRBARINSTRFENCEGWINSTRFENCELRINSTRLOADGBT4DF32INSTRATOMBASUBGS323D1LINSTRATOMBMINGS322D1LINSTRATOMBAMAXGU321D1LINSTRATOMBAANDGS321D1LINSTRATOMBXORGU323D1LINSTRATOMBCMPXGNU642DINSTRATOMBACMPXGS323D1LINSTRATOMBAXCHGGU322D1LINSTRATOMBXCHGGS322D1LINSTRATOMBAXCHGGF321DINSTRATOMBAINCGS321D1LINSTRATOMBINCGU322D1LINSTRATOMBINCLNGS323D1LINSTRATOMBINCLNGU32INSTRATOMBAINCLNGU321DINSTRATOMBADECGU321DINSTRATOMBDECLNGS323DINSTRATOMBADECLNGU32INSTRATOMBADECRGGU323DINSTRSAMINSTRSETGINSTRQUADSHFLMODEHORIZU16INSTRATOMSUBGS32INSTRATOMXCHGLU32INSTRAROMINCRGLS32INSTRATOMDECRGGU32INSTRATOMDECRGGS32INSTRLDIBAF321DRCKINSTRLDIBAF323DINSTRLDIBAS321DINSTRSCALE16INSTRSWZS32INSTRATOMINCLNGENS32INSTRLDIBUNTYPEDU162DINSTRLDIBTYPEDU163DRCKINSTRSTIBTYPEDS323DINSTRSTIBUNTYPEDF321DTINSTRSTIBTYPEDU161DTINSTRSTIBUNTYPEDF162DINSTRWMMF16F32INSTRGATS32INSTRGATU32INSTRSCTS32INSTRSCTU16INSTRSCTS16S32INSTRSCTF32F16INSTRSHFLUPINSTRSHFLUPU32INSTRDCL_PC_OFFSET_YIELD_TOKENDCL_CL_PRIVATEMEMENDCONSTREGID_TOKENDCL_CL_WORK_DIMENSIONS_TOKENDIMEN_2DSDIMEN_2DFLOW_INSTR_5LOADPINSTRBFREVINSTRMOV_INSTRTEX_INSTR_3IMG_INSTR ALU2: Out of Range Immediate Value given for Source1 Operand.It should be in Range -2047 - 2047MOV/COV: For MOVS instruction, destination operand of MOVS can be sGPR/GPRMOV/COV: Destination operand of MOV/COV should be dummy register for INVSR instructionMOV/COV: Found full-width destination register where half-width was expectedLDST: Only Full GPR allowed inside Relative addresing mode.shaderBehaviorinputs_A5Xinputs_A4XVERSIONED_STRUCTURE_INFOADRENO_SO_BUFFERADRENO_BOOLEAN_CONSTANT_EXPRESSIONADRENO_BINDLESS_GROUP_EMULATION_DATAshaderOutputstesDescdescriptorUsageInfoInputBuiltIn_InputLoad program binary failedMAX_COMPUTE_WORK_GROUP_INVOCATIONSAMD_FOG_BLENDGEOMETRY_POINT_SIZE Shader ============MaxComputeWorkGroupInvocationsMaxComputeWorkGroupSize_XrenderTargetDisableMask" elementCount="" elementOffset="GL_BOOL_VEC3GL_SAMPLER_709Y2R_QCOMQGL_TEXTURE_EXTERNAL_UYVY_AMDQGL_TEXTURE_601R2Y_QCOMQGL_TEXTURE_2D_ARRAYQGL_TEXTURE_2D_RECT_SHADOWRGB2YUV709RGBA32F SSBOTopLevel, textureSlotIntGather = %d location = %dvendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/gl_core/ModuleCache.cpp location or component exceeds max allowed.InlineUniformBlock:$TFBuffer1BasePtr32$TessControlPointSizeUint32$ViewMaskUint32Transform Feedback Buffer 1 Base Pointer (64-bit)ComputeenableInitialTextureenableConstMulTextureenablePredicationenableFSInputPackingenableVRSgeometric_functionsforceTexCoordllvm.log2.f32llvm.qgpu.fract.f16llvm.ctpop.i16Error: Compute shader is linked with other shader(s)glnext.transform.feedback0 && "Unknown image format"qgpu.dummy.samplemaskinPre BE Codegen!vec0Opnd->isQuarter() && "i8 vec should go to generateIntDotProduct?"false && "Operator not handled yet in generateTwoOpndIntrinsic"false && "pre-primitive VRS not supported."rotationOpnd->getLLVMOperand()->getAddrPointer() && "No ShadingRateKHRRotation named constant addr pointer"insertPositiondyOP && "Gradient operand dPdy is missing!"yuv_test_true(insertPos == insertBB->end()) || (insertPos->getParent() == insertBB)(dstPtr == NULL) || (dstTy == NULL)(structRetTypeID != QGLC_INVALID_INDEX_VALUE) && "struct type return is expected"export_insert_point && "Terminator inst is expected"ray_initializeval && "OpRayQueryGetWorldRayOriginKHR" " is not supported"confirm_intersectionproceed__RTget_intersection_geometry_index__RTget_intersection_object_ray_origin__RTtemp.mat$VkPointerreg_vRelPatchIdGV && GV->getType()false && "Can't find builtin output size!"symbolIndex && "symbolIndex is Null"pVID != NULLload && "TES output is set to reg"constTessLevelInnergl_MaxDualSourceDrawBuffersEXTimage2DMSiimage2DMS(imageUsage == Image_Used_Without_Sampler) && "subpass is expected to be used without sampler"oldExitBB->getTerminator() && "Terminator inst is expected."newEntryBB->getTerminator() && "Terminator inst is expected."vendor/qcom/proprietary/graphics/adreno200/shadercompiler/HighLevelCompiler/lib/LA/opengl/gl_parser/CodeGen/AST_Patcher.cpp$DefaultUBOcontained && "expected to be active"s2yiimg1disnantextureGatherOffsetcopyOf.type.getObjectSize() == 1pragmacan't modify gl_MaxTessEvaluationAtomicCounterscan't modify gl_MaxFragmentAtomicCounterscan't modify gl_MaxComputeWorkGroupSizeunsupported constructionconstUnion not initialized in addConstVectorNode functionmatrix field selection out of range '%d'indexing into a sampler array using a non-constant expression is not permittedDo not support array of array outputfunction declaration not in global scopesamplers specified with subsampled layout can only be used with texture function.interpolant must be varying inputbuilt in unary operator function. Type: %sarray parameters dimension mismatches.Invalid atomic counter offset or offset conflictInvalid declaration, only invariant/precise allowedGL_EXT_gpu_shader5GL_EXT_fragment_invocation_density'constructor' : assigning non-constant to '%s'Vector * MatrixFunction - Construct ivec3Texture2DShadowLoop Body Branch: ContinuebarrierimageAtomicExchangeitofyuvNo default label can be nested inside other control flow nested within their corresponding switchvoid function cannot return a valueGL_EXT_separate_shader_objectsGENERIC' can not be activated for current shader typeToo many args in Macro unexpected tokens following #endif.#version needs a version number0 && "wrong forward reference type"ExecutionModeIDLocalIDList.size() == 3 && "expected size of ExecutionModeIDLocalIDList= 3"(!(fovPatch == rotationPatch && fovPatch)) && "enableFSFovPatching and enableVKPreRotationPatching can't be simultaneously on"OpTypeOpaqueOpTypePointerOpMemberDecorateOpISubBorrowOpSelectOpUGreaterThanEqualOpNotOpBitReverseOpGroupAllOpGroupReserveReadPipePacketsOpIsHelperInvocationEXTError: Exceed the maximum allowed UBO. Linking failed.] -> buf(currentBlockMemberSemId == nextBlockMemberSemId) && "gl_PerVertex layout does not match across stages"it != m_candidateFuncNames.end() && "function name not found in candidate functions"confirmstack.framerayList.executingRaysCount.fgtidframeSizeInBytes % sizeof(int) == 0 && "invalid alignment"func && "commitCurrHitT() should have been inserted in init()"scheduleContBB && "should have one instance of scheduleCont"not.from.tr (Full) (VS) (ROImage) (BindlessBase)useRasterizerAccessOrderUAV: usesRelativeAddressing: fetchFrameBuffer: numTexSamInst: [ADRENO_VSDSGS_OUTPUTS] (Ver [ADRENO_VS_INPUTS] (Ver viewIDConstRamLocation: conservativeZMode: [ADRENO_CS_INPUTS_V2] (Ver initialIJWriteDis: numLoads: [ADRENO_R24_UNORM_PATCHING_READ][emulatedGroups: ]: imageInfo: useTextureSlot: blockLayout: dataType: numTotalVAVar: usedBases: globalOrderingFlags: != .uavReadMask.hwShader.needsBaseVertex.mergedShaderInfoRegID.cullUsageMask.maxOutputVertices.extraLocalMemorySize.numClipPlanes.outputPrimitive.reuseGPRMode.hasBarrier.packFactorZ.isLeftShift.bindlessTextureSupport[ADRENO_INPUT_TARGET_DATA].useMultiPositionOutput.disableInstancePacking[GL_SHADER_DATA][GL_SYMBOL_INFO_NAMED_CONSTANT].isPrecise->.namedConst.declaredArraySize.numSubelements.numTotalPAVar.payloadSize.indexBufferSizePerWorkgroup.visibilityStreamSizePerWorkgroup - lod : %8d - stgba : %8d,%8d (rpt), ratio %5.2f - Single GPR Pool : %8d - Fiber Count : %8d tex.threedtex.getlodmem.ldpmem.stga_rptmem.resbase_rptQCCOptionStringListDisableCBCachingDisableMinPrecisionOpsEnablePreambleDisableSBufVectorizeGLShaderVersionEnableSafeNopInsertionVerifyObjNamedCompileStatsPatchConstantSignatureGenerateSPIRVEnableStateCacheWarmInPreambleEnablePackedSampleInstABGEBindlessIndexPtrPerInstanceAttributesMaskEnableBindlessVertexSOBGESizeScratchBindlessReservedMaskInstrumentationCallbackQGLC_COLORSPACE_MODEL specializationElementsError parsing reserved location tag data: Expected symbols with same virtual register index to be compatible, error in compiler-generated metadata. Invalid Texture * Const is only enable when fp16 is the return GPR format., error in compiler-generated metadata. Unable to get bindless group mapping entry. VPC index used in multiple stream out entries. pStreamOutBufPtr + pStreamOutBufDesc->m_ElementSize * i && "memcpy dest pointer is NULL!" Data describing special inputs used by the PS. Version 1.0: Added needsFragCoord: True if the shader reads the fragment coordinate (position.xy). Added needsZrhW: True if the shader reads the Z/W components (position.zw). Added needsFaceness: True if the shader reads the front facing component. Added needsPrimitiveID: True if the shader reads the primitive ID. Added fragCoordRegID: Scalar full precision register ID for fragment coordinate (full, .xy). Added fragCoordSamplePosition: Sampling position to use for the fragment coordinate. Added zrhWRegID: Scalar full precision register ID for Z/W components (full, .xy). Added facenessRegID: Scalar half precision register ID for front facing component (half, .x). Added primitiveIDVirtualRegID: Virtual register ID for primitive ID (for pass-through). Added primitiveIDVirtualComp: Virtual register component for primitive ID (for pass-through). Version 1.1: Renamed FragCoordInterpMode to FragCoordSamplePosition and changed type from QCC_InterpMode to QCC_PSSamplePosition. Version 1.2: Added fragCoordEnableMask: Bitmask of used raster position components (position.xy). Added zrhWEnableMask: Bitmask of used raster ZrhW components (position.zw). Version 1.3: Added pointSpriteUVVirtualRegID: Virtual register ID for sprite offset (gl_PointCoord.xy). Added pointSpriteUVVirtualComp: Virtual register component for sprite offset (gl_PointCoord.xy). Added needsPointSpriteUV: True if the shader reads the sprite offset (gl_PointCoord). Added pointSpriteUVEnableMask: Bitmask of used sprite offset components (gl_PointCoord.xy). Version 1.4: Added primitiveIDVPCIndex: VPC Index assigned for primitive ID input (for pass-through). Added pointSpriteUVVPCIndex: VPC Index for sprite offset (gl_PointCoord.xy). Version 1.5: Added needsViewID: True if the shader reads gl_ViewID_OVR. Added viewIDVirtualRegID: Virtual register ID for view ID (gl_ViewID_OVR). Added viewIDVirtualComp: Virtual register component for view ID (gl_ViewID_OVR). Added viewIDVPCIndex: VPC Index for viewID (gl_ViewID_OVR). Version 1.6: Added viewIDConstRamLocation: Constant RAM location assigned to View ID. Version 1.7: Added needsFoveationQuality: True if the shader reads foveation quality. Added foveationQualityRegID: GPR ID for foveation quality(full). Version 1.8: Added needsPackedFragcoordXY: True if the shader reads the packed fragment coordinate (a7p). Added packedFragcoordXYRegID: GPR ID for packed fragment coordinate. Version 1.9: Added needsBaryCentricCoord: True if the shader reads the barycentric coordinate (a7p). Added baryCentricCoordVPCIndex: VPC Index for barycentric coordinate. Version 1.10: Added needsSampleIDIfMSAA: True if the shader needs sample ID in case of MSAA. Version 1.11: Added needsPrimitiveAttributeBuffer: True if the shader reads from the primitive attribute buffer in a mesh pipeline. Information about statically indexed textures returned from the shader patching interface. The patched texture index will be used for gather on the texture since hardware performs per-channel-swizzle before gather, while GLES requires that per-channel-swizzle performed after gather. The driver will be responsible for duplicating the texture into the new slot using default swizzle. Version 1.0: Added sourceTextureSlotIndex: The original texture slot index referenced. Added patchedTextureSlotIndex: The texture slot index referenced in the patching code. Added isLinearSRGBA: The patching texture slot is for ASTC with linear SRGBA format Describes all mesh shader outputs being loaded directly into VPC local memory from a mesh shader output buffer. The format of the data is fixed to 32-bit formats and there is no GPR allocated for these outputs, as they are copied directly to local memory. VPC will copy the entire region into VPC memory, so holes should be discouraged. There are scenarios where we won't have enough space to fit everything into VPC memory, in which case a subset of the data will need to be read from a GMEM pointer in the fragment shader. Version 1.0: Added numTotalPAVar: How many VPC identifiers are used for primitive attributes Added startVaryID4PA: First VPC index used for a primitive attribute. Added offset: Offset from the beginning of the primitive data. Gives information that is common to a shader collection. Version 1.0: Added maxPayloadSizeInBytes: Maximum payload size for the collection. Added maxAttributeSizeInBytes: Maximum attribute size for the collection. Added maxRecursionDepth: Maximum recursion depth for the collection. Added rayDataSize: Size of ray data buffer per ray. Added skipTriangles: TraceRay will skip any triangles encountered. Added skipProcedural: TraceRay will skip any procedural primitives encountered. Added reservedBits Added localSizeX: The size of the thread group's first dimension. Added localSizeY: The size of the thread group's second dimension. Added localSizeZ: The size of the thread group's third dimension. false && "Compilation canceled due to callback failure return code"Create context failed printBSLFVTsixREG_0x%xloBitsSet <= numBits && "Too many bits to set!"DW_TAG_type_unitDW_LANG_lo_usersysteminfo-output-to-stdoutlinuxsolaris monotonic output ;